CN114264926A - Single-via hole cross-layer electromigration test structure of single-side lead-out voltage test bonding pad - Google Patents
Single-via hole cross-layer electromigration test structure of single-side lead-out voltage test bonding pad Download PDFInfo
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- CN114264926A CN114264926A CN202111426037.7A CN202111426037A CN114264926A CN 114264926 A CN114264926 A CN 114264926A CN 202111426037 A CN202111426037 A CN 202111426037A CN 114264926 A CN114264926 A CN 114264926A
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- 238000012360 testing method Methods 0.000 title claims abstract description 164
- 239000002184 metal Substances 0.000 claims abstract description 60
- 238000001465 metallisation Methods 0.000 claims abstract description 43
- 238000001514 detection method Methods 0.000 claims abstract description 33
- 230000000694 effects Effects 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 27
- 238000013461 design Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000005259 measurement Methods 0.000 description 8
- 230000035882 stress Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The invention relates to the technical field of semiconductors, in particular to a single-via hole cross-layer electromigration test structure with a voltage test bonding pad led out from one side, which comprises a silicon substrate layer and an insulating medium layer, wherein the insulating medium layer is arranged at the top of the silicon substrate layer, and the structure also comprises: the metallization test line, the interconnection detection line and the through hole are positioned in the insulating medium layer; the metallization test line: testing for electromigration effects; the interconnection detection line: metal lines for interconnection and detection; the through hole: for multi-hierarchy interconnects; large area metallized current test pad and voltage test pad: for current input and voltage reading, respectively. The interconnection detecting line includes: the device comprises a test line interconnection section, a metal interconnection line and a voltage detection line. The test structure comprises two metal layers and is used for evaluating the electromigration reliability problem caused in the manufacturing process of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a single-via-hole cross-layer electromigration test structure of a single-side lead-out voltage test bonding pad.
Background
Electromigration (Electromigration) refers to a phenomenon in which metal ions in a metal conductor material migrate under the action of a large amount of electron movement, and macroscopically represents the movement of a metal substance. This effect is particularly pronounced when large currents are passed through the metallic conductor material. After the integrated circuits have been successfully commercialized, electromigration has become one of the major concerns in the field of semiconductor reliability. A Test structure (Test Characterization field) is a wafer-level or package-level structure for evaluating the reliability of a semiconductor device, and aims to find out the reliability defect of the semiconductor device, take measures to solve the reliability defect, ensure that the device has good reliability in the whole product life, and measure physical parameters, process parameters, device parameters or circuit parameters by using the Test structure.
The test structure for electromigration is generally designed as a metal line type test structure, and is composed of metal lines of each layer and VIA holes connected with each other between different layers in a CMOS process. And simulating an electromigration test by specifically applying electric and thermal stress to the test structure, and evaluating the reliability of the tested process through test data.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a single-via cross-layer electromigration test structure of a single-side lead-out voltage test bonding pad, which is used for evaluating the electromigration reliability problem caused in the manufacturing process of a semiconductor device.
The invention is realized by the following technical scheme:
the utility model provides a single through-hole strides layer type electromigration test structure of voltage test pad is drawn forth to unilateral, includes silicon substrate layer and insulating medium layer, the top of silicon substrate layer is equipped with insulating medium layer still includes: the metallization test line, the interconnection detection line, the through hole, the current test pad and the voltage test pad are positioned in the insulating medium layer;
the metallization test line: testing for electromigration effects;
the interconnection detection line: metal lines for interconnection and detection;
the through hole: for multi-hierarchy interconnects;
large area metallized current test pad and voltage test pad: for current input and voltage reading, respectively.
Preferably, the interconnection detecting line includes: the device comprises a test line interconnection section, a metal interconnection line and a voltage detection line.
Preferably, the test structure comprises two metal layers;
wherein the metallization test line, the metal interconnect line, and the current test pad are located on a first layer; the metallization test wire is conducted with the metal interconnection wire through the test wire interconnection section, the leading-out end of the metal interconnection wire is connected with the current test bonding pad, and the current test bonding pad positioned in the insulating medium layer is exposed through an etching process;
the voltage detection line and the voltage test pad are located at a second layer; the voltage detection line is conducted with the metal interconnection line through the through hole to form a cross-layer structure, meanwhile, a leading-out end of the voltage detection line is connected with the voltage test bonding pad, and the voltage test bonding pad located inside the insulating medium layer is exposed through an etching process.
Preferably, the metallization test line adopts two process line widths, namely a fixed line width and a minimum line width;
the fixed line width is 2um, and the minimum line width conforms to the design rule of a product process line; the lengths of the two pieces are all larger than or equal to 800 um.
Preferably, the test line interconnection section: the length of the interconnection section of the test line is specified as the distance between the end part of the metallized test line and the through hole;
the line width of the metal test line is 2 times of the length of the metal test line;
the length of the test line needs to be satisfied, the ratio of the lengths of the interconnection sections of the metallization test line and the two ends of the metallization test line is greater than or equal to 95 percent and less than or equal to 8 um.
Preferably, the line width of the metal interconnection line is 2 times of the length of the metallization test line, and the length of the metal interconnection line is greater than or equal to 80 um.
Preferably, the line width of the voltage detection line is less than or equal to the line width of the metallization test line, and the length of the metallization test line is greater than or equal to 80 um.
Preferably, the number of the through holes for connecting the metal interconnection line and the voltage detection line is 1, and the through holes are of a single-through-hole structure.
Preferably, the size of a single through hole is the minimum value allowed by the design rule; and the edge covering distances between the through holes and the Metal layer Metal 1 and the Metal layer Metal 2 are the minimum values allowed by the design rule.
Preferably, the length and width of the voltage test pad and the current test pad should be designed to be not less than 5 times of the width of the metal interconnection line.
The invention has the beneficial effects that:
the method is used for representing the reliability of the electromigration effect of the metallization test line and the through hole of the tested process. When the test is carried out, current needs to be added to the two ends of the current source, the voltage at the two ends of the metal wire is measured through the independent voltage loop, and the resistance variation of the metal wire is observed. For evaluating electromigration reliability problems caused during the manufacture of semiconductor devices.
If the voltage between the PADs is measured directly, unnecessary parasitic parameters are introduced. The voltage measurement also needs to form a current loop, but the current is extremely small, and the current in the electromigration test is large, so that the voltage measurement loop and the current stress loop are combined together, that is, the voltage measurement accuracy is affected by measuring the voltage with a large current. If the current is cut off and the voltage measurement is carried out in the test process, the continuity of the stress is damaged, and the test result is inaccurate. Therefore, the current loop and the voltage loop in the electromigration test process need to be independent.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic plan view of the present invention;
FIG. 2 is a schematic plan view of a cross-layer structure of the voltage terminal of the present invention;
FIG. 3 is an enlarged partial view of a single via interconnect structure of the present invention;
FIG. 4 is a first longitudinal cross-sectional view of the present invention;
FIG. 5 is a second longitudinal cross-sectional view of the present invention;
FIG. 6 is a diagram of the interconnect detection line architecture of the present invention.
In the figure: the device comprises a 1-metallization test line, a 2-interconnection test line, a 21-test line interconnection section, a 22-metal interconnection line, a 23-voltage test line, a 3-through hole, a 4-current test pad and a 5-voltage test pad.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
referring to fig. 1 to 6, the present embodiment specifically discloses a technical solution for providing a single-via-hole cross-layer electromigration test structure with a voltage test pad led out from a single side, where the structure includes a silicon substrate layer and an insulating medium layer, and the top of the silicon substrate layer is provided with the insulating medium layer, and the structure further includes: the device comprises a metallization test line 1, an interconnection detection line 2, a through hole 3, a current test pad 4 and a voltage test pad 5 which are positioned in an insulating medium layer;
metallization test line 1: testing for electromigration effects;
interconnection detection line 2: metal lines for interconnection and detection;
through hole 3: for multi-hierarchy interconnects;
large area metallized current test pad 4 and voltage test pad 5: for current input and voltage reading, respectively.
Specifically, the interconnection detecting line 2 includes: test line interconnect section 21, metal interconnect line 22, and voltage detection line 23.
Specifically, the test structure comprises two metal layers;
wherein the metallization test line 1, the metal interconnect 22 and the current test pad 4 are located in a first layer; the metallization test wire 1 is conducted with the metal interconnection wire 22 through the test wire interconnection section 21, the leading-out end of the metal interconnection wire 22 is connected with the current test pad 4, and the current test pad 4 positioned in the insulating medium layer is exposed through an etching process;
the voltage detection line 23 and the voltage test pad 5 are located at the second layer; the voltage detection line 23 is communicated with the metal interconnection line 22 through the through hole 3 to form a cross-layer structure, meanwhile, a leading-out end of the voltage detection line 23 is connected with the voltage test pad 5, and the voltage test pad 5 located in the insulating medium layer is exposed through an etching process.
Specifically, the metallization test line 1 adopts two process line widths, namely a fixed line width and a minimum line width;
the fixed line width is 2um, and the minimum line width conforms to the design rule of a product process line; the lengths of the two pieces are all larger than or equal to 800 um.
Specifically, the test line interconnection section 21: the length of the test line interconnection section 21 is defined as the distance between the end of the metallized test line 1 and the through hole 3;
the line width of the test line is 2 times of the length of the metallization test line 1;
the length of the test line is required to satisfy that the length ratio of the metallization test line 1 to the metallization test line 1 plus the test line interconnection sections 21 at the two ends is greater than or equal to 95 percent and less than or equal to 8 um.
Specifically, the line width of the metal interconnection line 22 is 2 times of the length of the metallization test line 1, and the length is greater than or equal to 80 um.
Specifically, the line width of the voltage detection line 23 is less than or equal to the line width of the metallization test line 1, and the length thereof is greater than or equal to 80 um.
Specifically, the number of the through holes 3 for connecting the metal interconnection lines 22 and the voltage detection lines 23 is 1, and the through holes are in a single through hole 3 structure.
Specifically, the size of a single through hole 3 is the minimum value allowed by the design rule; the edge covering distances between the through holes 3 and the Metal layers Metal 1 and Metal 2 are the minimum values allowed by the design rule.
Specifically, the lengths and widths of the voltage test pad 5 and the current test pad 4 should be designed to be at least not less than 5 times the width of the metal interconnection line 22.
The metallization test line 1 is a long metallization resistor strip designed on an oxide layer, the cross-sectional area of the resistor strip needs to be kept uniform, and the purpose is to ensure that the test line has approximately uniform temperature before an obvious cavity is formed.
The length of the metallization test line 1 needs to be larger than or equal to 800um, so that the metallization electromigration effect can be well represented, the short-circuit effect and the thermal interference of two current pads can be avoided, and the metallization test line 1 can be guaranteed to have approximately uniform temperature distribution before an obvious cavity is formed.
The interconnection structure of the metallized through hole 3 is a single-end through hole 3 interconnection structure, and the voltage detection line 23 is led out from the middle position of the through hole 3.
In order to reduce the effect of the metallization layers of the current test pad 4 and the voltage test pad 5 on electromigration of the metallization interconnect lines, the length and width of the voltage test pad 5 and the current test pad 4 should be designed to be at least 5 times or more smaller than the width of the metal interconnect line 22.
In order to facilitate probe contact or bonding lead-out, it is recommended that the current test pad 4 and the voltage test pad 5 be designed to have a size of 90um × 90um or more.
The method is used for representing the reliability of the electromigration effect of the metallization test line 1 and the through hole 3 of the tested process. When the test is carried out, current needs to be added to the two ends of the current source, the voltage at the two ends of the metal wire is measured through the independent voltage loop, and the resistance variation of the metal wire is observed. For evaluating electromigration reliability problems caused during the manufacture of semiconductor devices.
If the voltage between the PADs is measured directly, unnecessary parasitic parameters are introduced. The voltage measurement also needs to form a current loop, but the current is extremely small, and the current in the electromigration test is large, so that the voltage measurement loop and the current stress loop are combined together, that is, the voltage measurement accuracy is affected by measuring the voltage with a large current. If the current is cut off and the voltage measurement is carried out in the test process, the continuity of the stress is damaged, and the test result is inaccurate. Therefore, the current loop and the voltage loop in the electromigration test process need to be independent.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. The utility model provides a voltage test pad's single through-hole strides layer type electromigration test structure is drawn forth to unilateral, includes silicon substrate layer and insulating medium layer, the top of silicon substrate layer is equipped with insulating medium layer, its characterized in that still includes: the metallization testing line (1), the interconnection detecting line (2), the through hole (3), the current testing pad (4) and the voltage testing pad (5) are positioned in the insulating medium layer;
the metallization test line (1): testing for electromigration effects;
the interconnection detection line (2): metal lines for interconnection and detection;
the through hole (3): for multi-hierarchy interconnects;
large area metallized current test pad (4) and voltage test pad (5): for current input and voltage reading, respectively.
2. The electromigration test structure of claim 1, wherein: the interconnection detection line (2) comprises: the testing device comprises a testing line interconnection section (21), a metal interconnection line (22) and a voltage detection line (23).
3. The electromigration test structure of claim 2, wherein: the test structure comprises two metal layers;
wherein the metallization test line (1), the metal interconnect line (22) and the current test pad (4) are located in a first layer; the metallization test wire (1) is communicated with the metal interconnection wire (22) through the test wire interconnection section (21), the leading-out end of the metal interconnection wire (22) is connected with the current test pad (4), and the current test pad (4) positioned in the insulating medium layer is exposed through an etching process;
the voltage detection line (23) and the voltage test pad (5) are located at a second layer; the voltage detection line (23) is communicated with the metal interconnection line (22) through the through hole (3) to form a cross-layer structure, meanwhile, the leading-out end of the voltage detection line (23) is connected with the voltage test pad (5), and the voltage test pad (5) located inside the insulating medium layer is exposed through an etching process.
4. The electromigration test structure of claim 1, wherein: the metallization test line (1) adopts two process line widths, namely a fixed line width and a minimum line width;
the fixed line width is 2um, and the minimum line width conforms to the design rule of a product process line; the lengths of the two pieces are all larger than or equal to 800 um.
5. The electromigration test structure of claim 2, wherein: the test line interconnection section (21):
the line width of the metal testing line is 2 times of the length of the metal testing line (1);
the length of the test line needs to be satisfied, the ratio of the lengths of the interconnection sections (21) of the metallization test line (1) and the two ends is greater than or equal to 95 percent and less than or equal to 8 um.
6. The electromigration test structure of claim 2, wherein: the line width of the metal interconnection line (22) is 2 times of the length of the metallization test line (1), and the length of the metal interconnection line is greater than or equal to 80 um.
7. The electromigration test structure of claim 2, wherein: the line width of the voltage detection line (23) is less than or equal to the line width of the metallization test line (1), and the length of the metallization test line is greater than or equal to 80 um.
8. The electromigration test structure of claim 3, wherein: the number of the through holes (3) for connecting the metal interconnection lines (22) and the voltage detection lines (23) is 1, and the through holes are of a single through hole (3) structure.
9. The electromigration test structure of claim 8, wherein: the size of the single through hole (3) is the minimum value allowed by a design rule; and the edge covering distances between the through holes (3) and the Metal layers Metal 1 and Metal 2 are the minimum values allowed by the design rule.
10. The electromigration test structure of claim 6, wherein: the length and the width of the voltage test pad (5) and the current test pad (4) are at least designed to be not less than 5 times of the width of the metal interconnection line (22).
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| CN202111426037.7A CN114264926B (en) | 2021-11-26 | 2021-11-26 | Single-through hole cross-layer electromigration test structure of single-side lead-out voltage test pad |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0448273A1 (en) * | 1990-03-21 | 1991-09-25 | AT&T Corp. | Integrated circuit electromigration monitor |
| JP2000174085A (en) * | 1998-12-08 | 2000-06-23 | Nec Corp | Semiconductor reliability evaluation device and method |
| US6680484B1 (en) * | 2002-10-22 | 2004-01-20 | Texas Instruments Incorporated | Space efficient interconnect test multi-structure |
| CN102446900A (en) * | 2010-10-12 | 2012-05-09 | 上海华虹Nec电子有限公司 | Electromigration reliability test structure and making method for multilayer of metal interconnected metal wires |
| CN212540578U (en) * | 2020-06-12 | 2021-02-12 | 长江存储科技有限责任公司 | Test structure |
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- 2021-11-26 CN CN202111426037.7A patent/CN114264926B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0448273A1 (en) * | 1990-03-21 | 1991-09-25 | AT&T Corp. | Integrated circuit electromigration monitor |
| JP2000174085A (en) * | 1998-12-08 | 2000-06-23 | Nec Corp | Semiconductor reliability evaluation device and method |
| US6680484B1 (en) * | 2002-10-22 | 2004-01-20 | Texas Instruments Incorporated | Space efficient interconnect test multi-structure |
| CN102446900A (en) * | 2010-10-12 | 2012-05-09 | 上海华虹Nec电子有限公司 | Electromigration reliability test structure and making method for multilayer of metal interconnected metal wires |
| CN212540578U (en) * | 2020-06-12 | 2021-02-12 | 长江存储科技有限责任公司 | Test structure |
Non-Patent Citations (2)
| Title |
|---|
| HARRY A. SCHAFFT, ET AL.: "Reproducibility of Electromigration Measurements", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》, vol. 34, no. 3, pages 673 - 681 * |
| 于赫薇 等: "金属电迁移测试过程中的电介质击穿效应", 《半导体技术》, vol. 40, no. 4, 30 April 2015 (2015-04-30), pages 314 - 317 * |
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