CN114264868B - Detection circuit and method of power receiving end equipment - Google Patents
Detection circuit and method of power receiving end equipment Download PDFInfo
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- CN114264868B CN114264868B CN202111442624.5A CN202111442624A CN114264868B CN 114264868 B CN114264868 B CN 114264868B CN 202111442624 A CN202111442624 A CN 202111442624A CN 114264868 B CN114264868 B CN 114264868B
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Abstract
Embodiments of the present application provide a detection circuit and method of a powered end device, the circuit including: a master control circuit; a power supply equipment identification circuit electrically connected with the main control circuit; the voltage acquisition circuit is electrically connected with the power supply equipment identification circuit; when the main control circuit controls the power supply voltage of the power supply equipment identification circuit to be in a power supply state, the voltage acquisition circuit is used for acquiring the voltage of a target measuring point of the power supply equipment identification circuit to obtain a detection result, the detection result is sent to a management chip electrically connected with the voltage acquisition circuit, and the management chip is used for monitoring the state of the power receiving end equipment in real time. The embodiment of the application realizes the real-time detection of the power consumption of the power receiving end equipment PD and can conveniently control and manage the PD equipment.
Description
Technical Field
The application relates to the technical field of Ethernet power supply, in particular to a detection circuit and method of powered end equipment.
Background
With rapid development of the internet of things technology, terminals which need to provide network services are more and more abundant, and power supply for various intelligent terminals by using a traditional strong current mode is more and more difficult, so that the popularization of the power over ethernet (PoE) technology is more and more advanced, and the power supply problem of various intelligent terminals is being solved one by one. The PoE technology is widely applied from traditional wireless local area networks (WLAN for short), network monitoring, IP phones and other application scenes to new retail, internet of things (IoT for short), smart cities and other scenes, and has the characteristics of low cost, convenient construction, stable power supply, high operation and maintenance efficiency and the like.
The PoE technology can be implemented to transmit data signals and provide dc power for IP-based terminals (e.g., IP phones, wireless APs, network monitoring, etc.) without any modification to the existing ethernet wiring structure, and maintains compatibility with existing ethernet and users. Therefore, the working procedures of slotting, pipe laying, threading, debugging, wall body and ground beautifying and the like are not needed to be added in the construction environment, the construction period is greatly shortened, and the cost is reduced.
However, the protocol chip of the current PSE (powersourcing equipment) technology performs a protocol, which generally has high cost, complex peripheral circuits, and complex control detection and control modes.
Disclosure of Invention
The application provides a detection circuit and a detection method of powered end equipment. The circuit structure is simple, the layout of the Printed Circuit Board (PCB) is convenient, the cost of the circuit is low, the power consumption of the power receiving end equipment PD can be detected in real time, and the PD equipment can be controlled and managed conveniently. In order to solve the above technical problems, the embodiments of the present application provide the following solutions:
a detection circuit of a power receiving end device, comprising:
a master control circuit;
a power supply equipment identification circuit electrically connected with the main control circuit;
the voltage acquisition circuit is electrically connected with the power supply equipment identification circuit;
when the main control circuit controls the power supply voltage of the power supply equipment identification circuit to be in a power supply state, the voltage acquisition circuit is used for acquiring the voltage of a target measuring point of the power supply equipment identification circuit to obtain a detection result, the detection result is sent to a management chip electrically connected with the voltage acquisition circuit, and the management chip is used for monitoring the state of the power receiving end equipment in real time.
Optionally, the master control circuit includes:
a main control chip;
the first resistor is electrically connected with the main control chip;
the base electrode of the first triode is electrically connected with the first resistor, the emitting electrode of the first triode is grounded, and the collecting electrode of the first triode is electrically connected with the power supply equipment identification circuit;
the two ends of the second resistor are respectively connected with the base electrode and the emitter electrode of the first triode;
when the main control chip sends a high level, the first triode is in a saturated working state, and a low-level power supply voltage is provided for the power supply equipment identification circuit through the collector electrode of the first triode;
when the main control chip sends low level, the first triode is in a cut-off working state, and the collector electrode of the first triode stops controlling the switch circuit in the power supply equipment identification circuit.
Optionally, the power supply device identification circuit includes:
a power receiving end device connection circuit;
a second triode electrically connected with the power receiving end equipment connecting circuit;
a switching circuit electrically connected to the power receiving-side device connection circuit and the second transistor;
a mirrored current source circuit electrically connected to the second transistor and the switching circuit; the switch circuit and the mirror current source circuit are electrically connected with the voltage acquisition circuit.
Optionally, the powered end device connection circuit includes:
a first port; the first port is used for being communicated with or disconnected from one end of the power receiving end equipment; the first port is electrically connected with one end of a first capacitor, and the other end of the first capacitor is electrically connected with the mirror current source circuit;
a second port; the second port is used for being communicated with or disconnected from the other end of the power receiving end equipment; the second port is electrically connected with one end of a first diode, and the other end of the first diode is electrically connected with the mirror current source circuit; the second port is electrically connected with one end of a first transient suppression diode, and the other end of the first transient suppression diode is electrically connected with the voltage acquisition circuit;
at least one bi-directional transient suppression diode electrically connected to the first port or the second port.
Optionally, the emitter of the second triode is electrically connected with the power receiving end device connection circuit, the base of the second triode is electrically connected with the mirror current source circuit, and the collector of the second triode is electrically connected with the switch circuit.
Optionally, the base electrode and the emitter electrode of the second triode further include:
one end of the second capacitor is electrically connected with the base electrode of the second triode, and the other end of the second capacitor is electrically connected with the emitter electrode of the second triode.
Optionally, the switching circuit includes:
a field effect transistor;
third and fourth resistors electrically connected to a third port of the field effect transistor; the other end of the third resistor is electrically connected with the collector electrode of the second triode; the other end of the fourth resistor is electrically connected with the mirror current source circuit;
a fifth resistor having one end electrically connected to the fourth and sixth ports of the field effect transistor and the other end electrically connected to the fifth port of the field effect transistor;
one end of the second transient suppression diode is electrically connected with the third port of the field effect transistor, and the other end of the second transient suppression diode is electrically connected with the third capacitor and the second transient suppression diode.
Optionally, the mirrored current source circuit includes:
a third triode; the collector electrode of the third triode is electrically connected with a power supply through at least three resistors; the emitter of the third triode is electrically connected with one end of the sixth resistor;
a fourth triode with a base electrically connected with the base of the third triode; the collector electrode of the fourth triode is electrically connected with one end of a seventh resistor, and the other end of the seventh resistor is electrically connected with the power supply; the emitter of the fourth triode is electrically connected with one end of the eighth resistor, and the emitter of the fourth triode is electrically connected with one end of the second diode; the other end of the eighth resistor and the other end of the second diode are electrically connected with the other end of the sixth resistor.
Optionally, the voltage acquisition circuit includes:
a ninth resistor with one end electrically connected with the mirror current source circuit and the other end electrically connected with the grounding end;
a voltage acquisition positive port arranged at one end of the ninth resistor;
a voltage acquisition negative port arranged at the other end of the ninth resistor;
the voltage acquisition positive port and the voltage acquisition negative port are arranged on the management chip.
The application also provides a detection method of the power receiving end equipment, which is applied to the circuit, and comprises the following steps:
acquiring a power supply state of a power supply voltage of a power supply equipment identification circuit;
according to the power supply state of the power supply voltage, the voltage of the target measuring point of the power supply equipment identification circuit is collected through the voltage collection circuit to obtain a detection result, the detection result is sent to a management chip electrically connected with the voltage collection circuit, and the management chip monitors the state of the power receiving end equipment in real time.
The scheme of the application at least comprises the following beneficial effects:
according to the scheme, the main control circuit is adopted; a power supply equipment identification circuit electrically connected with the main control circuit; the voltage acquisition circuit is electrically connected with the power supply equipment identification circuit; when the main control circuit controls the power supply voltage of the power supply equipment identification circuit to be in a power supply state, the voltage acquisition circuit is used for acquiring the voltage of a target measuring point of the power supply equipment identification circuit to obtain a detection result, the detection result is sent to a management chip electrically connected with the voltage acquisition circuit, and the management chip is used for monitoring the state of the power receiving end equipment in real time. The circuit has a simple structure, is convenient for the layout of a Printed Circuit Board (PCB), has low cost, can realize the real-time detection of the power consumption of PD (power end device) equipment, and can conveniently control and manage the PD equipment.
Drawings
Fig. 1 is a schematic structural diagram of a detection circuit of a power receiving end device according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a power supply device identification circuit in a detection circuit of a power receiving end device according to an embodiment of the present application;
fig. 3 is a flowchart illustrating a method for detecting a powered end device according to an embodiment of the present application;
reference numerals illustrate:
r7-a first resistor; r2-a second resistor; r191-a third resistor; r178-fourth resistance; r194-fifth resistance; r179-sixth resistance; r193-seventh resistance; r180-eighth resistor; r785-ninth resistor; 11-a mirrored current source circuit; 12-a switching circuit; 13-a power receiving end device connection circuit; q16-a first triode; q11-a second triode; q13-a third triode; q14-fourth triode; DX 12-first diode; DX 13-second diode; an N12-field effect transistor; d59—a first transient suppression diode; d58—a second transient suppression diode; a-a first port; b-a second port; a-a third port; b-a fourth port; c-a fifth port; d-a sixth port; c86-a first capacitance; c85-a second capacitance; c87-a third capacitance; PSE1_ADCin+ -voltage acquisition positive port; PSE1_ADCin- -negative voltage acquisition port; v_in-power supply.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.
As shown in fig. 1, the present application provides a detection circuit of a power receiving end device, including:
a master control circuit;
a power supply equipment identification circuit electrically connected with the main control circuit;
the voltage acquisition circuit is electrically connected with the power supply equipment identification circuit;
when the main control circuit controls the power supply voltage of the power supply equipment identification circuit to be in a power supply state, the voltage acquisition circuit is used for acquiring the voltage of a target measuring point of the power supply equipment identification circuit to obtain a detection result, the detection result is sent to a management chip electrically connected with the voltage acquisition circuit, and the management chip is used for monitoring the state of the power receiving end equipment in real time.
In this embodiment, the main control circuit controls the switch circuit 12 in the power supply device identification circuit to control power supply, and when in a power supply state, the voltage acquisition circuit acquires the voltage of the target measurement point of the power supply device identification circuit to obtain a detection result, and sends the detection result to the management chip, and the management chip can monitor the power supply device identification circuit in real time, where real-time monitoring includes real-time detection of power consumption of the power receiving end device and control of connection and disconnection of the power receiving end device, and by a circuit with a simple structure, a layout convenient for PCB (printed circuit board) is realized, the cost of the circuit is low, and the power consumption of the PD (power receiving end device) device can be detected in real time, so that the PD device can be controlled conveniently.
In an alternative embodiment of the present application, the master control circuit includes:
a main control chip;
the first resistor R7 is electrically connected with the main control chip;
the base electrode of the first triode Q16 is electrically connected with the first resistor R7, the emitter electrode of the first triode R16 is grounded, and the collector electrode of the first triode R16 is electrically connected with the power supply equipment identification circuit;
the two ends of the second resistor R2 are respectively connected with the base electrode and the emitter electrode of the first triode Q16;
when the main control chip sends a high level, the first triode Q16 is in a saturated working state, and a low-level power supply voltage is provided for the power supply equipment identification circuit through the collector electrode of the first triode Q16;
when the main control chip sends low level, the first triode Q16 is in a cut-off working state, and the collector electrode of the first triode Q16 stops controlling the switch circuit 12 in the power supply equipment identification circuit.
As shown in fig. 2, in this embodiment, the main control chip controls to provide a high level/low level to the PSE1_en of the power supply device identification circuit through the first triode Q16, a first resistor R7 is electrically connected between the main control chip and the base of the first triode Q16, one end of the first resistor R7 is electrically connected to the base of the first triode Q16, the other end of the first resistor R7 is electrically connected to the main control chip, the emitter of the first triode Q16 is grounded, the collector provides a high level/low level to the power supply device identification circuit, and preferably, a second resistor R2 is electrically connected between one end of the first resistor R7 and the emitter of the first triode Q16, and the second resistor R2 is used for ensuring reliable cut-off of the first triode Q16;
when the main control chip sends a high level to the first triode Q16 through the first resistor R7, the first triode Q16 is in a saturated working state, and a low-level power supply voltage is provided for the power supply equipment identification circuit through the collector electrode of the first triode Q16; conversely, when the main control chip sends a low level to the first triode Q6 through the first resistor R7, the first triode Q16 is in a cut-off working state, and the collector of the first triode Q16 does not provide a supply voltage to the switching circuit 12 in the power supply equipment identification circuit, i.e. the first triode Q16 stops controlling the switching circuit 12 in the power supply equipment identification circuit;
here, the high level/low level provided by the main control chip can control the third port a of the field effect transistor of the power supply equipment identification circuit, so that the power supply to the power supply equipment identification circuit is started and stopped, the power supply of the detection circuit of the power receiving end equipment is controllable, and the management of the detection circuit of the power receiving end equipment is facilitated.
In an alternative embodiment of the present application, the power supply apparatus identification circuit includes:
a power receiving-end device connection circuit 13;
a second transistor Q11 electrically connected to the power receiving-side device connection circuit 13;
a switching circuit 12 electrically connected to the power receiving-side device connection circuit 13 and the second transistor Q11;
a mirror current source circuit 11 electrically connected to the second transistor Q11 and the switch circuit 12; the switch circuit 12 and the mirror current source circuit 11 are electrically connected to the voltage acquisition circuit.
In this embodiment, the power supply device identification circuit includes a power receiving end device connection circuit 13, a second triode Q11, a switch circuit 12, and a mirror current source circuit 11, where the second triode Q11 is electrically connected to the power receiving end device connection circuit 13, the switch circuit 12 is electrically connected to the second triode Q11 and the power receiving end device connection circuit 13, and the mirror current source circuit 11 is electrically connected to the second triode Q11 and the switch circuit 12;
one end of the switch circuit 12 is electrically connected with the main control circuit, the main control circuit supplies power to the switch circuit 12, the current receiving end equipment connected in the current receiving end equipment connecting circuit 13 is detected through the mirror current source circuit 11 and the second triode Q11, a target measuring point is further arranged on the mirror current source circuit 11 and is electrically connected with the voltage acquisition circuit, and the target measuring point is used for detecting and/or controlling the current receiving end equipment in the current receiving end equipment connecting circuit 13 through the voltage acquisition circuit.
Specifically, in an alternative embodiment of the present application, the power receiving end device connection circuit 13 includes:
a first port a; the first port A is used for being communicated with or disconnected from one end of the power receiving end equipment; the first port a is electrically connected with one end of the first capacitor C86, and the other end of the first capacitor C86 is electrically connected with the mirror current source circuit 11;
a second port B; the second port B is used for being communicated with or disconnected from the other end of the power receiving end equipment; the second port B is electrically connected with one end of the first diode DX12, and the other end of the first diode DX12 is electrically connected with the mirror current source circuit 11; the second port B is electrically connected with one end of a first transient suppression diode D59, and the other end of the first transient suppression diode D59 is electrically connected with the voltage acquisition circuit;
at least one bi-directional transient suppression diode electrically connected to the first port a or the second port B.
In this embodiment, the powered device connection circuit 13 includes a first port a, a second port B and at least one bidirectional transient suppression diode, where the first port a may be used to connect a section of the powered device, the second port B may be used to connect another end of the powered device, it should be noted that, when the first port a and the second port B are not connected to the powered device, normal operation of a detection circuit of the powered device is not affected, when the first port a and the second port B are not connected to the powered device, the master control circuit supplies power to the power supply device identification circuit, a management chip of the voltage acquisition circuit may detect that the powered device in the power supply device identification circuit is in an off state, power consumption of the power supply device is 0, at least one bidirectional transient suppression diode is electrically connected between the first port a and the ground terminal, at least one bidirectional transient suppression diode is electrically connected between the second port B and the ground terminal, and the bidirectional transient suppression diode is electrically connected between the first port a and the second port B to provide voltage stabilizing effect to the detection circuit of the powered device and the protection circuit;
further, the first port a is electrically connected to one end of the first capacitor C86, and the other end of the first capacitor C86 is electrically connected to the mirror current source circuit 11; the second port B is electrically connected with one end of a first diode DX12, and the other end of the first diode DX12 is electrically connected with the mirror current source circuit 11; the second port B is electrically connected with one end of a first transient suppression diode D59, and the other end of the first transient suppression diode D59 is electrically connected with the voltage acquisition circuit; the other end of the first transient suppression diode D59 is preferably electrically connected with the target measuring point position of the voltage acquisition circuit;
in addition, the power receiving end device electrically connected to the first port a and the second port B is defined herein according to the standard power receiving end device PD in IEEE802.3, and the dc impedance is preferably between 19k ohms and 26.5k ohms, and the capacitance value thereof does not exceed 150nF, and when the voltage acquisition circuit detects and/or controls the power receiving end device in the power supply device identification circuit, the dc impedance and the capacitance value of the power receiving end device of the power supply output line are preferably detected with a detection voltage of 2.8V to 10V.
In an alternative embodiment of the present application, an emitter of the second triode Q11 is electrically connected to the receiving-end device connection circuit 13, a base of the second triode Q11 is electrically connected to the mirror current source circuit 11, and a collector of the second triode Q11 is electrically connected to the switch circuit 12.
The second triode Q11 further comprises, between the base and the emitter:
and one end of the second capacitor C85 is electrically connected with the base electrode of the second triode Q11, and the other end of the second capacitor C85 is electrically connected with the emitter electrode of the second triode Q11.
In this embodiment, an emitter of the second triode Q11 is electrically connected to the power receiving end device connection circuit 13 and the mirror current source circuit 11, a base of the second triode Q11 is electrically connected to the mirror current source circuit 11, a collector of the second triode Q11 is electrically connected to the switch circuit 12, and a second capacitor C85 is further disposed between the base and the emitter of the second triode Q11;
when the power receiving end device is connected to the power receiving end device connection circuit 13, the voltage is 48V, and divided so that the voltage V between the first port A and the second port B AB Greater than the voltage V between port F and port D in figure A FD I.e. V AB ＞V FD Whereby the voltage V between the F and C ports FC Rising to make the second triode Q11 in a saturated working state, and further make the voltage V of the E port E In the high state, the field effect transistor N12 is in an on state, and supplies 48V between the first port a and the second port B.
In an alternative embodiment of the present application, the switching circuit 12 includes:
a field effect transistor N12;
a third resistor R191 and a fourth resistor R178 electrically connected to the third port a of the field effect transistor N12; the other end of the third resistor R191 is electrically connected with the collector electrode of the second triode Q11; the other end of the fourth resistor R178 is electrically connected with the mirror current source circuit 11;
a fifth resistor R194 having one end electrically connected to the fourth port b and the sixth port d of the field effect transistor N12 and the other end electrically connected to the fifth port c of the field effect transistor N12;
one end of the second capacitor is electrically connected with the third port a of the field effect transistor N12, and the other end of the second capacitor is electrically connected with the fifth port C of the field effect transistor N12, and the second transient suppression diode D58 is electrically connected with the third capacitor C87.
In this embodiment, the field effect transistor N12 is an N-Metal-Oxide-Semiconductor (N-channel-Metal-Oxide-Semiconductor;
the switch circuit 12 includes a field effect transistor N12, a third resistor R191, a fourth resistor R178, a fifth resistor R194, a third capacitor C87, and a second transient suppression diode D58, where a third port a of the field effect transistor N12 is electrically connected to the master control circuit, the master control circuit controls the power supply state of the switch circuit 12 by providing a high level or a low level to the third port a of the field effect transistor N12, the third port a of the field effect transistor N12 is further connected with the third resistor R191 and the fourth resistor R178, an end of the third resistor R191 away from the third port a of the field effect transistor N12 is electrically connected to the collector of the second triode Q11, and an end of the fourth resistor R178 away from the third port a of the field effect transistor N12 is electrically connected to the mirror current source circuit 11;
one end of the fifth resistor R194 is electrically connected with the fourth port b and the sixth port d of the field effect transistor N12, and the other end of the fifth resistor R194 is electrically connected with the fifth port c of the field effect transistor N12; one end of the third capacitor C87 and the second transient suppression diode D58 are electrically connected to the third port a of the field effect transistor N12, and the other end is electrically connected to the fifth port C of the field effect transistor N12;
when the power receiving end device connection circuit 13 is connected with the power receiving end device, the voltage is divided between the first port A and the second port B, the fifth resistor R194 and the eighth resistor R180 to make V AB ＞V FD Thereby making V FC Rising, second transistor Q11 is in saturated operating state, V at third port c of field effect transistor N12 E In the high-level state, the third port a and the fifth port c of the field effect transistor N12 are in an off state, and the fourth port B, the fifth port c and the sixth port d are in an on state, so that power is supplied between the first port a and the second port B in the powered device connecting circuit 13.
In an alternative embodiment of the present application, the mirrored current source circuit 11 includes:
a third transistor Q13; the collector electrode of the third triode Q13 is electrically connected with a power supply V_IN through at least three resistors; an emitter of the third triode Q13 is electrically connected with one end of a sixth resistor R179;
a fourth triode Q14 with a base electrically connected to the base of the third triode Q13; the collector of the fourth triode Q14 is electrically connected with one end of a seventh resistor R193, and the other end of the seventh resistor R193 is electrically connected with the power supply V_IN; an emitter of the fourth triode Q14 is electrically connected with one end of the eighth resistor R180, and an emitter of the fourth triode Q14 is electrically connected with one end of the second diode DX 13; the other end of the eighth resistor R180 and the other end of the second diode DX13 are electrically connected to the other end of the sixth resistor R179.
IN this embodiment, a mirror current source is formed by a third triode Q13 and a fourth triode Q14, the collector of the third triode Q13 is electrically connected with a power source v_in through at least three resistors, the power source v_in is used for supplying power to a power receiving end device, the emitter of the third triode Q13 is electrically connected with one end of a sixth resistor R179, and the other end of the sixth resistor R179 is electrically connected with the other end of an eighth resistor R180 and the other end of a second diode DX13 respectively; the base electrode of the third triode Q13 is electrically connected with the base electrode of the fourth triode Q14;
the collector of the fourth triode Q14 is electrically connected with one end of a seventh resistor R193, and the other end of the seventh resistor R193 is electrically connected with the power supply V_IN; the emitter of the fourth triode Q14 is electrically connected with one end of the eighth resistor R180 and one end of the second diode DX13 respectively;
the target measuring point is preferably the other end of the sixth resistor R179, namely the other ends of the eighth resistor R180 and the second diode DX 13;
the current through the eleventh resistor R192 electrically connected to the collector of the third transistor Q13 is preferably referred to as IC 2 The current through the seventh resistor R193 is referred to as IC 1 The current through the sixth resistor R179 is denoted IE 2 ；
When the third port a and the fourth port b of the field effect transistor N12 are in the conducting state, the collector V of the fourth triode Q14 G The forward voltage drop from 70mV to the second diode DX13 is 1V, i.e. V G =1v, so that the third triode Q13 to 1V, and a current IE through a sixth resistor R179 2 Increase the current IC through the eleventh resistor R192 2 Increasing the voltage V between the F port and the C port FC The second triode Q11 is increased to be in a saturated working state, and the stable output of the circuit is supplied with power;
when the powered end device between the first port A and the second port B is in an off state, the collector V of the fourth triode Q14 G The forward voltage drop 1V from the second diode DX13 is reduced to 70mV, and the current IE passes through the sixth resistor R179 2 Approaching 0A, IE 2 ≈IC 2 ≈0A，V FC Approximately 0V, the second transistor Q11 is in an off state, and the fifth port c, the fourth port b and the sixth port d of the field effect transistor N12 are in an off state, so that power supply is stopped.
In an alternative embodiment of the present application, a voltage acquisition circuit includes:
a ninth resistor R785 having one end electrically connected to the mirror current source circuit 11 and the other end electrically connected to the ground;
a voltage acquisition positive port PSE1_ADCin+ arranged at one end of the ninth resistor R785;
a voltage acquisition negative port PSE1_ADCin < - > arranged at the other end of the ninth resistor R785;
the voltage acquisition positive port PSE1_ADCin+ and the voltage acquisition negative port PSE1_ADCin-are arranged on the management chip.
In this embodiment, the voltage acquisition circuit is disposed on a target measurement point, one end of the ninth resistor R785 is electrically connected to the target measurement point on the current mirror circuit 11, the other end is electrically connected to the ground terminal, one end of the ninth resistor R785 is provided with a voltage acquisition positive port PSE1_adcin+, and the other end is provided with a voltage acquisition negative port PSE1_adcin-, where the voltage acquisition positive port PSE1_adcin+ and the voltage acquisition negative port PSE1_adcin are disposed on the management chip, and the management chip is configured to monitor the status of the device at the receiving end in real time; ninth resistor R785 is used as current detection resistor when load current I E2 The voltages being varied simultaneously when they are varied, by ADC (Analog-to-digital converter )Conversion) function is fed back to the management chip, and the purpose of real-time monitoring can be achieved.
The application passes through the main control circuit; a power supply equipment identification circuit electrically connected with the main control circuit; the voltage acquisition circuit is electrically connected with the power supply equipment identification circuit; when the main control circuit controls the power supply voltage of the power supply equipment identification circuit to be in a power supply state, the voltage acquisition circuit is used for acquiring the voltage of a target measuring point of the power supply equipment identification circuit to obtain a detection result, the detection result is sent to a management chip electrically connected with the voltage acquisition circuit, and the management chip is used for monitoring the state of the power receiving end equipment in real time; the power consumption of the power receiving end equipment PD can be detected in real time, and the PD equipment can be conveniently controlled and managed.
As shown in fig. 3, the present application further provides a method for detecting a powered device, which is applied to the above circuit, and the method includes:
step 31, acquiring a power supply state of a power supply voltage of a power supply equipment identification circuit;
and step 32, according to the power supply state of the power supply voltage, acquiring the voltage of a target measuring point of the power supply equipment identification circuit through the voltage acquisition circuit to obtain a detection result, and sending the detection result to a management chip electrically connected with the voltage acquisition circuit, wherein the management chip monitors the state of the power receiving end equipment in real time.
As shown in fig. 1 and fig. 2, in a specific embodiment, the master control circuit controls the power supply state of the power supply identification circuit, specifically, when the master control chip sends a high level to the first triode Q16 through the first resistor R7, the first triode Q16 is in a saturated working state, and provides a low level power supply voltage to the power supply equipment identification circuit through the collector of the first triode Q16; conversely, when the main control chip sends a low level to the first triode Q16 through the first resistor R7, the first triode Q16 is in a cut-off working state, and a high-level power supply voltage is provided for the power supply equipment identification circuit through the collector electrode of the first triode Q16;
acquiring a power supply state of a power supply voltage of a power supply equipment identification circuit, wherein the power supply state of the power supply voltage of the power supply equipment identification circuit is provided by a high level or low level state of a third port a of a field effect transistor N12 in the power supply equipment identification circuit;
when the power receiving end device is connected to the power receiving end device connection circuit 13, the voltage provided by the power supply V_IN is divided between the first port A and the second port B, the fifth resistor R194 and the eighth resistor R180 to enable V AB ＞V FD Thereby making V FC Rising, second transistor Q11 is in saturated operating state, V at third port c of field effect transistor N12 E In a high level state, a third port a and a fifth port c of the field effect transistor N12 are in an off state, and a fifth port c and a fourth port B and a sixth port d of the field effect transistor N12 are in an on state to supply power between a first port a and a second port B in the receiving end device connection circuit 13;
when the third port a and the fourth port b of the field effect transistor N12 are in the conducting state, the collector V of the fourth triode Q14 G The forward voltage drop from 70mV to the second diode DX13 is 1V, i.e. V G =1v, so that the voltage at the collector of the third transistor Q13 rises to 1V, and the current IE through the sixth resistor R179 2 Increase the current IC through the eleventh resistor R192 2 Increasing the voltage V between the F port and the C port FC The second triode Q11 is increased to be in a saturated working state, and the stable output of the circuit is supplied with power;
when the powered end device between the first port A and the second port B is in an off state, the collector V of the fourth triode Q14 G The forward voltage drop 1V from the second diode DX13 is reduced to 70mV, and the current IE passes through the sixth resistor R179 2 Approaching 0A, IE 2 ≈IC 2 ≈0A，V FC The second triode Q11 is in a cut-off working state and the fifth port c, the fourth port b and the sixth port d of the field effect transistor N12 are in a cut-off state, so that power supply is stopped;
ninth resistor R785 is used as current detection resistor when load current I E2 The voltage changes simultaneously when the change occurs, through ADC functionAnd the data is fed back to the management chip, so that the purpose of real-time monitoring can be achieved.
It should be noted that the method is a method corresponding to the above circuit, and all implementation manners in the above circuit embodiment are applicable to the circuit embodiment, so that the same technical effect can be achieved.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.
Furthermore, it should be noted that in the apparatus and method of the present application, it is apparent that the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent aspects of the present application. Also, the steps of performing the series of processes described above may naturally be performed in chronological order in the order of description, but are not necessarily performed in chronological order, and some steps may be performed in parallel or independently of each other. It will be appreciated by those of ordinary skill in the art that all or any of the steps or components of the methods and apparatus of the present application may be implemented in hardware, firmware, software, or a combination thereof in any computing device (including processors, storage media, etc.) or network of computing devices, as would be apparent to one of ordinary skill in the art after reading this description of the application.
The object of the application can thus also be achieved by running a program or a set of programs on any computing device. The computing device may be a well-known general purpose device. The object of the application can thus also be achieved by merely providing a program product containing program code for implementing said method or apparatus. That is, such a program product also constitutes the present application, and a storage medium storing such a program product also constitutes the present application. It is apparent that the storage medium may be any known storage medium or any storage medium developed in the future. It should also be noted that in the apparatus and method of the present application, it is apparent that the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent aspects of the present application. The steps of executing the series of processes may naturally be executed in chronological order in the order described, but are not necessarily executed in chronological order. Some steps may be performed in parallel or independently of each other.
While the foregoing is directed to the preferred embodiments of the present application, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations are intended to be comprehended within the scope of the present application.
Claims (5)
1. A detection circuit of a power receiving end device, characterized by comprising:
a master control circuit;
a power supply equipment identification circuit electrically connected with the main control circuit;
the voltage acquisition circuit is electrically connected with the power supply equipment identification circuit;
when the main control circuit controls the power supply voltage of the power supply equipment identification circuit to be in a power supply state, the voltage acquisition circuit is used for acquiring the voltage of a target measuring point of the power supply equipment identification circuit to obtain a detection result, the detection result is sent to a management chip electrically connected with the voltage acquisition circuit, and the management chip is used for monitoring the state of the power receiving end equipment in real time;
the power supply apparatus identification circuit includes:
a power receiving end device connection circuit (13);
a second transistor (Q11) electrically connected to the power receiving-end device connection circuit (13);
a switching circuit (12) electrically connected to the power receiving-side device connection circuit (13) and the second transistor (Q11);
a mirrored current source circuit (11) electrically connected to the second transistor (Q11) and the switching circuit (12); the switch circuit (12) and the mirror current source circuit (11) are electrically connected with the voltage acquisition circuit;
the power receiving-end device connection circuit (13) includes:
a first port (A); the first port (A) is used for being connected with or disconnected from one end of the power receiving end equipment; the first port (A) is electrically connected with one end of a first capacitor (C86), and the other end of the first capacitor (C86) is electrically connected with the mirror current source circuit (11);
a second port (B); the second port (B) is used for being connected with or disconnected from the other end of the power receiving end equipment; the second port (B) is electrically connected with one end of a first diode (DX 12), and the other end of the first diode (DX 12) is electrically connected with a mirror current source circuit (11); the second port (B) is electrically connected with one end of a first transient suppression diode (D59), and the other end of the first transient suppression diode (D59) is electrically connected with a voltage acquisition circuit;
at least one bidirectional transient suppression diode electrically connected to the first port (a) or the second port (B);
the emitter of the second triode (Q11) is electrically connected with the power receiving end equipment connecting circuit (13), the base electrode of the second triode (Q11) is electrically connected with the mirror current source circuit (11), and the collector electrode of the second triode (Q11) is electrically connected with the switch circuit (12);
the switching circuit (12) includes:
a field effect transistor (N12);
a third resistor (R191) and a fourth resistor (R178) electrically connected to a third port (a) of the field effect transistor (N12); the other end of the third resistor (R191) is electrically connected with the collector electrode of the second triode (Q11); the other end of the fourth resistor (R178) is electrically connected with the mirror current source circuit (11);
a fifth resistor (R194) having one end electrically connected to the fourth port (b) and the sixth port (d) of the field effect transistor (N12) and the other end electrically connected to the fifth port (c) of the field effect transistor (N12);
one end of the second transient suppression diode is electrically connected with a third port (a) of the field effect transistor (N12), and the other end of the second transient suppression diode is electrically connected with a third capacitor (C87) and a second transient suppression diode (D58) of the fifth port (C) of the field effect transistor (N12);
the mirror current source circuit (11) includes:
a third transistor (Q13); the collector of the third triode (Q13) is electrically connected with a power supply (V_IN) through at least three resistors; an emitter of the third triode (Q13) is electrically connected with one end of a sixth resistor (R179);
a fourth triode (Q14) having a base electrically connected to the base of the third triode (Q13); the collector of the fourth triode (Q14) is electrically connected with one end of a seventh resistor (R193), and the other end of the seventh resistor (R193) is electrically connected with the power supply (V_IN); an emitter of the fourth triode (Q14) is electrically connected with one end of an eighth resistor (R180), and an emitter of the fourth triode (Q14) is electrically connected with one end of a second diode (DX 13); the other end of the eighth resistor (R180) and the other end of the second diode (DX 13) are electrically connected to the other end of the sixth resistor (R179).
2. The detection circuit of the power receiving-end apparatus according to claim 1, wherein the main control circuit includes:
a main control chip;
a first resistor (R7) electrically connected with the main control chip;
a first triode (Q16) with a base electrically connected with the first resistor (R7), wherein an emitter of the first triode (Q16) is grounded, and a collector of the first triode (Q16) is electrically connected with the power supply equipment identification circuit;
the two ends of the second resistor (R2) are respectively connected with the base electrode and the emitter electrode of the first triode (Q16);
when the main control chip sends high level, the first triode (Q16) is in a saturated working state, and low-level power supply voltage is provided for the power supply equipment identification circuit through the collector electrode of the first triode (Q16);
when the main control chip sends low level, the first triode (Q16) is in a cut-off working state, and the collector electrode of the first triode (Q16) stops controlling the switching circuit (12) in the power supply equipment identification circuit.
3. The detection circuit of the power receiving end device according to claim 1, wherein between the base and the emitter of the second transistor (Q11) further comprises:
and one end of the second capacitor (C85) is electrically connected with the base electrode of the second triode (Q11), and the other end of the second capacitor is electrically connected with the emitter electrode of the second triode (Q11).
4. The detection circuit of the power receiving-end apparatus according to claim 1, wherein the voltage acquisition circuit includes:
a ninth resistor (R785) having one end electrically connected to the mirror current source circuit (11) and the other end electrically connected to the ground;
a voltage acquisition positive port (PSE1_ADCin+), which is arranged at one end of the ninth resistor (R785);
a voltage acquisition negative port (PSE1_ADCin-);
the voltage acquisition positive port (PSE1_ADCin+) and the voltage acquisition negative port (PSE1_ADCin-) are disposed on the management chip.
5. A method of detecting a powered end device, applied to the circuit of any of claims 1 to 4, the method comprising:
acquiring a power supply state of a power supply voltage of a power supply equipment identification circuit;
according to the power supply state of the power supply voltage, the voltage of the target measuring point of the power supply equipment identification circuit is collected through the voltage collection circuit to obtain a detection result, the detection result is sent to a management chip electrically connected with the voltage collection circuit, and the management chip monitors the state of the power receiving end equipment in real time.
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| CN202111442624.5A CN114264868B (en) | 2021-11-30 | 2021-11-30 | Detection circuit and method of power receiving end equipment |
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