CN114257336A - Signal transmission system and transmitting terminal coding device - Google Patents

Abstract

A transmitting-end encoding apparatus includes a multiplexer and a transmitting-end encoder. The multiplexer is used for receiving the first digital signal and the second digital signal and generating an output. The output of the multiplexer includes a plurality of M-bit code words of the first digital signal and a plurality of M-bit code words of the second digital signal that are alternately arranged with the plurality of M-bit code words of the first digital signal. The transmitting end encoder is used for receiving the output of the multiplexer and generating a plurality of N-bit code words, wherein M and N are positive integers, and M is not equal to N. The transmitting-end encoder is used for determining the current N-bit code word in the N-bit code words according to the output of the multiplexer and the inequality of the previous N-bit code word in the N-bit code words, and transmitting the N-bit code words to a receiving-end decoding device comprising a receiving-end decoder and the demultiplexer.

Description

Signal transmission system and transmitting terminal coding device

Technical Field

The present invention relates to a signal transmission system and a transmitter encoding device thereof, and more particularly, to a dc-balanced high-speed signal transmission system and a transmitter encoding device thereof.

Background

Differential signals have excellent external interference resistance and steep rising and falling edges, and are therefore often used in high-speed data transmission technology. When a sequence of "1" s or "0" s is transmitted continuously using a differential signal, the impedance of the transmission line may be correspondingly increased to possibly distort signal attenuation because the frequency of the signal is decreased. In order to enable the differential signal to transmit the sequence of "1" and "0" equally, i.e. to achieve direct current balance (DC balance), many coding methods have been applied to high-speed data transmission systems, such as 8-bit to 10-bit (8B/10B) coding methods. In this coding method, each 8-bit codeword (code word) is converted into a 10-bit codeword having positive disparity (disparity), negative disparity, or no disparity, where positive disparity, negative disparity, and no disparity represent a number of "1" s in the sequence that is greater than a number of "0" s, a number of "1" s in the sequence that is less than a number of "0" s, and a number of "1" s and "0" s in the sequence that are equal, respectively. By arranging the order of occurrence of the 10-bit code words with these three kinds of inequalities reasonably, dc balance can be achieved.

Disclosure of Invention

The application provides a signal transmission system, which comprises a transmitting end coding device and a receiving end decoding device. The transmitting end coding device comprises a multiplexer and a first transmitting end coder. The multiplexer is used for receiving the first digital signal and the second digital signal and generating an output. The output of the multiplexer comprises a plurality of M-bit code words of the first digital signal and a plurality of M-bit code words of the second digital signal which are alternately arranged with the plurality of M-bit code words of the first digital signal, wherein M is a positive integer. The first transmitting end encoder is used for receiving the output of the multiplexer and generating a plurality of N-bit code words, wherein N is a positive integer and M is not equal to N. The first transmitting end encoder is used for determining a current N-bit code word in the N-bit code words according to the output of the multiplexer and the disparity (disparity) of a previous N-bit code word in the N-bit code words. The receiving end decoding device is coupled to the transmitting end encoding device and comprises a first receiving end decoder and a demultiplexer. The first receiving end decoder is used for decoding the N-bit code words to generate I-bit code words. I is a positive integer and I is not equal to N. The demultiplexer is used for distributing the I bit code words to a plurality of output ends of the demultiplexer alternately.

The application provides a transmitting end coding device, which comprises a multiplexer and a first transmitting end coder. The multiplexer is used for receiving the first digital signal and the second digital signal and generating an output. The output of the multiplexer comprises a plurality of M-bit code words of the first digital signal and a plurality of M-bit code words of the second digital signal which are alternately arranged with the plurality of M-bit code words of the first digital signal, wherein M is a positive integer. The first transmitting end encoder is used for receiving the output of the multiplexer and generating a plurality of N-bit code words, wherein N is a positive integer and M is not equal to N. The first transmitting end encoder is used for determining the current N-bit code word in the N-bit code words according to the output of the multiplexer and the inequality of the previous N-bit code word in the N-bit code words. The first transmitter encoder is configured to transmit the plurality of N-bit codewords to a receiver decoder. The receiving end decoding device comprises a demultiplexer and a first receiving end decoder used for decoding the plurality of N-bit code words.

The application provides a receiving end decoding device, which comprises a first receiving end decoder and a demultiplexer. The first receiving-end decoder is used for receiving a plurality of N-bit code words from the transmitting-end coding device. The transmitting end coding device comprises a multiplexer and a first transmitting end coder used for generating a plurality of N-bit code words. The first receiver decoder is configured to decode the plurality of N-bit codewords to generate a plurality of I-bit codewords. The plurality of N-bit codewords have substantially equal numbers of 0's and 1's, N and I being positive integers and N not equal to I. The demultiplexer is used for distributing the I bit code words to a plurality of output ends of the demultiplexer alternately.

An advantage of the various embodiments described above is that the need for the number of transmission lines is reduced without reducing the data rate.

Drawings

Fig. 1 is a simplified functional block diagram of a signal transmission system according to an embodiment of the present application.

Fig. 2 is a schematic diagram illustrating the multiplexer alternately arranging the codewords of different digital signals.

Fig. 3 is a diagram illustrating the encoding result of the encoder at the transmitting end.

Fig. 4 is a diagram illustrating a decoding result of a decoder at a receiving end.

FIG. 5 is a schematic diagram illustrating the demultiplexer alternately distributing codewords received at the same input to different outputs.

Fig. 6 is a simplified functional block diagram of a signal transmission system according to another embodiment of the present application.

Fig. 7 is a simplified functional block diagram of a signal transmission system according to another embodiment of the present application.

Detailed Description

Embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar components or process flows.

Fig. 1 is a simplified functional block diagram of a signal transmission system 100 according to an embodiment of the present application. The signal transmission system 100 includes a transmitting end encoding device 110, a transmitting end physical layer driver 120, a receiving end physical layer driver 130, a receiving end decoding device 140 and a cable 150. The transmitting-side encoding device 110 is used for receiving the digital signals DAa-DAd transmitted from an external device (not shown), such as a graphics processor or other suitable logic circuit. In some embodiments, the digital signals DAa-DAd include video data, audio data, or other control signals (such as, but not limited to, a vertical synchronization signal and a backlight control signal). The transmitting-side encoding device 110 is used for encoding the digital signals DAa-DAd into digital signals DBa-DBb and providing the digital signals DBa-DBb to the transmitting-side physical layer driver 120. In some embodiments, the digital signals DBa-DBb are direct current balanced (DC balance) signals.

The transmitting phy layer driver 120, the cable 150 and the receiving phy layer driver 130 are sequentially coupled in series. The transmit physical layer driver 120 is configured to convert the digital signals DBa-DBb into serialized differential signals and provide the serialized differential signals to the receive physical layer driver 130 via the cable 150. That is, although fig. 1 depicts cable 150 as dual channel, in some embodiments cable 150 includes 4 differential signal lines. The receiver physical layer driver 130 is configured to restore the differential signals to digital signals DBa to DBb, and provide the restored digital signals DBa to DBb to the receiver decoding apparatus 140. The receiver decoding device 140 is configured to be coupled to a video control chip or an audio control chip (not shown). The receiving-end decoding device 140 is further configured to convert the digital signals DBa-DBb into a data format compatible with the video control chip or the audio control chip to generate the digital signals DCa-DCd. In some embodiments, the transmitting physical layer driver 120, the cable 150, and the receiving physical layer driver 130 are compliant or compatible with one or more communication specifications, such as, but not limited to, peripheral component interconnect express (PCIe), Serial Advanced Technology Attachment (SATA), or High Definition Multimedia Interface (HDMI).

The transmitting-end encoding apparatus 110 includes a multiplexer 112 and a transmitting-end encoder 114 coupled to each other. The multiplexer 112 is used for receiving the digital signals DAa-DAd. For convenience of explanation, in the following embodiments of the present application, the digital signals DAa to DAd are assumed to each include a plurality of 8-bit code words (code words), but the present application is not limited thereto. In some embodiments, digital signals DAa-DAd each include a plurality of M-bit codewords, and M is a positive integer. The first output terminal of the multiplexer 112 is used for outputting 8-bit code words of the digital signals DAa and DAb, and the multiplexer 112 alternates the 8-bit code words of the digital signal DAa with the 8-bit code words of the digital signal DAb. Similarly, the second output terminal of the multiplexer 112 is used for outputting 8-bit code words of the digital signals DAc and DAd, and the multiplexer 112 alternates the 8-bit code words of the digital signal DAc with the 8-bit code words of the digital signal DAd.

Fig. 2 is a schematic diagram illustrating the multiplexer 112 alternately arranging the codewords of different digital signals. As shown in fig. 2, in an arbitrary period, the digital signal DAa sequentially provides the codewords "f 0", "f 2", "f 4", and "f 6", and the digital signal DAb sequentially provides the codewords "f 1", "f 3", "f 5", and "f 7". At the output of the first output of the multiplexer 112, the codeword "f 1" is arranged between the codewords "f 0" and "f 2", the codeword "f 3" is arranged between the codewords "f 2" and "f 4", and so on. In this application, the value of the codeword is represented by 16 carry for simplicity, for example, the codeword "f 0" represented by 16 carry is identical to the 8-bit codeword "11110000" represented by 2 carry. Multiplexer 112 alternates codewords of digital signals DAc and DAd in a similar manner, and for brevity, will not be described again.

The transmitter encoder 114 is configured to encode the 8-bit code words received from the first output terminal and the second output terminal of the multiplexer 112 into 10-bit code words to obtain the digital signals DBa and DBb, respectively, that is, the transmitter encoder 114 is an 8-bit to 10-bit (8B/10B) encoder, but the application is not limited thereto. In some embodiments, the transmitter encoder 114 is configured to encode the M-bit code words output by the multiplexer 112 into digital signals DBa and DBb having N-bit code words, where N is a positive integer and N is not equal to M.

Fig. 3 is a diagram illustrating the encoding result of the encoder 114 at the transmitting end. As shown in fig. 3, the transmitter encoder 114 encodes the 8-bit codewords "f 0" to "f 7" into 10-bit codewords "236", "3 b 1", "232", "1 d 3", "234", "1 d 5", "216", and "217", respectively, to generate the digital signal DBa. The 8B/10B code table is known to those skilled in the relevant art, and for brevity, will not be described again.

It is noted that, if any codeword in the codewords of the digital signal DBa output from the transmitter encoder 114 has a positive disparity (disparity), the codeword is adjacent to another codeword having a negative disparity. For example, "1" in the codeword "3 b 1" is more than "0" (6 1 s and 40 s in total) and has positive inequality, and thus "1" in the next codeword "232" is less than "0" (4 1 s and 60 s in total) and has negative inequality. Similarly, if any codeword has a negative disparity, that codeword will be adjacent to another codeword having a positive disparity. For example, codeword "234" has negative equality, and thus its next codeword "1 d 5" has positive equality.

As can be seen from the above, the transmitter encoder 114 determines the current codeword (e.g. codeword "232") of the digital signal DBa according to the inequality between the output of the multiplexer 112 (e.g. codeword "f 2") and the previous codeword of the digital signal DBa (e.g. the positive inequality of codeword "3 b 1"). Thereby, it is achieved that the digital signal DBa is a dc-balanced signal, i.e. that the plurality of code words of the digital signal DBa have a substantially equal number of "0" s and "1" s. The transmitter encoder 114 encodes the output of the second output terminal of the multiplexer 112 into the dc balanced digital signal DBb according to a similar method as described above, and for brevity, the description is omitted here.

Referring to fig. 1 again, the receiver decoding apparatus 140 includes a receiver decoder 142 and a demultiplexer 144 coupled to each other. The receiver decoder 142 is configured to receive the digital signals DBa and DBb from the receiver physical layer driver 130. The receiver decoder 142 decodes the 10-bit code words of the digital signals DBa and DBb into 8-bit code words, and provides the 8-bit code words corresponding to the digital signals DBa and DBb to a first input terminal and a second input terminal of the demultiplexer 144, respectively. The demultiplexer 144 further includes a first output terminal to a fourth output terminal. The demultiplexer 144 is configured to alternately distribute the codewords received at the first input to the first output and the second output of the demultiplexer 144 to form digital signals DCa and DCb, respectively. Similarly, the demultiplexer 144 alternately distributes the codewords received at the second input to the third output and the fourth output of the demultiplexer 144 to form digital signals DCc and DCd, respectively.

Fig. 4 is a diagram illustrating a decoding result of the receiver decoder 142. As shown in fig. 4, the receiver decoder 142 decodes the 10-bit code words "236", "3 b 1", "232", "1 d 3", "234", "1 d 5", "216" and "217" included in the digital signal DBa into 8-bit code words "f 0" to "f 7", respectively. Therefore, the receiver decoder 142 is a 10-bit to 8-bit (10B/8B) decoder, but the present application is not limited thereto. In some embodiments, the receiver decoder 142 decodes the digital signals DBa and DBb with N-bit code words into I-bit code words, where I is a positive integer and I is not equal to the aforementioned N.

Fig. 5 is a schematic diagram illustrating the demultiplexer 144 alternately distributing the codewords received by the same input to different outputs. As shown in FIG. 5, during an arbitrary time period, the demultiplexer 144 receives the codewords "f 0" to "f 7" in sequence from its first input. The demultiplexer 144 provides the codewords "f 0", "f 2", "f 4", and "f 6" through its first output terminal to form the digital signal DCa. Similarly, the demultiplexer 144 provides the codewords "f 1", "f 3", "f 5", and "f 7" through its second output terminal to form the digital signal DCb. That is, adjacent codewords are distributed to different outputs of the demultiplexer 144. The demultiplexer 144 generates the digital signals DCc and DCd in a similar manner, which is not described herein for brevity.

Referring to fig. 1 again, in an embodiment, the data transmission rates of the digital signals DAa-DAd may be 4Gbps (4gigabytes per second), and the data transmission rates of the digital signals DBa-DBb may be 10 Gbps. That is, the total data transmission rate of the digital signals DAa to DAd is 16Gbps, and the total data transmission rate of the digital signals DBa to DBb is 20 Gbps. As can be seen from the above, the signal transmission system 100 can reduce the requirement for the number of transmission lines without reducing the data transmission rate, thereby helping to reduce the width of the cable (e.g., the cable 150) between the electronic devices. However, the signal data transmission rate, the number of channels and the number of transmission lines in the present application are only examples and are not limited thereto.

Fig. 6 is a simplified functional block diagram of a signal transmission system 600 according to an embodiment of the present application. The signal transmission system 600 is similar to the signal transmission system 100 of fig. 1, except that the signal transmission system 600 further comprises a transmitting-end encoder 610 and a receiving-end decoder 620. The transmitter encoder 610 is used for encoding the digital signals DDa-DDd to generate digital signals DAa-DAd, respectively. In some embodiments, the digital signals DDa-DDd may be video signals, audio signals, or other control signals from a multimedia signal source (not shown). On the other hand, the receiver decoder 620 is configured to decode the digital signals DCa to DCd to generate digital signals DEa to DEd, respectively. In some embodiments, the receiver decoder 620 is configured to provide the digital signals DEa-DEd to a video control chip or an audio control chip (not shown).

In some embodiments, the transmitting encoder 610 is an 8B/10B encoder, and the receiving decoder 620 is a 10B/8B decoder, but the embodiment is not limited thereto. In other embodiments, the digital signals DAa-DAd output by the transmitter encoder 610 are dc balanced signals, i.e., the respective codewords of the digital signals DAa-DAd have substantially equal numbers of 0's and 1's.

Generally, a chip design employs a hierarchical design method (hierarchical design method), i.e., a chip is divided into a plurality of functional modules designed by a plurality of teams. In some embodiments, the multimedia signal source and signal transmission system 600 are designed by different teams, and the multimedia signal source is designed based on the assumption that the signal it generates will be provided to the encoder. Thus, the transmitting-side encoder 610 facilitates the signal transmission system 600 to be compatible with multimedia signal sources. Similarly, a video control chip or an audio control chip may be designed based on the assumption that an input signal is received from a decoder, unlike the design team of the signal transmission system 600. Accordingly, the receiver-side decoder 620 helps the signal transmission system 600 to be compatible with a video control chip or an audio control chip.

Fig. 7 is a simplified functional block diagram of a signal transmission system 700 according to an embodiment of the present application. The signal transmission system 700 is similar to the signal transmission system 100 of fig. 1, except that the signal transmission system 700 further includes a transmitting-end encoder 710, a transmitting-end decoder 720, a receiving-end encoder 730 and a receiving-end decoder 740. The transmitting-end encoder 710 is used for encoding the digital signals DDa-DDd to generate digital signals DFa-DFd, respectively. The transmitter decoder 720 is used for decoding the digital signals DFa-DFd to generate digital signals DAa-DAd, respectively. In some embodiments, the transmitter encoder 710 is an 8B/10B encoder and the transmitter decoder 720 is a 10B/8B decoder, i.e. the encoding/decoding algorithms of the transmitter encoder 710 and the transmitter decoder 720 correspond to each other, but the present application is not limited thereto. In some embodiments, the transmitter encoder 710 is configured to encode the digital signal DDa-DDd having M-bit codewords into a digital signal DFa-DFd having K-bit codewords, and the transmitter decoder 720 is configured to decode the digital signal DFa-DFd having K-bit codewords into a digital signal DAa-DAd having M-bit codewords, K and M being positive integers and K not being equal to M.

In other embodiments, the digital signals DFa-DFd output by the transmitter encoder 710 are dc balanced signals, i.e., the respective plurality of codewords of the digital signals DFa-DFd have substantially equal numbers of 0's and 1's.

The receiver-side encoder 730 is used for encoding the digital signals DCa-DCd to generate the digital signals DGa-DGd, respectively. The receiver decoder 740 is used for decoding the digital signals DGa-DGd to generate digital signals DEa-DEd, respectively. In some embodiments, the receiver encoder 730 is an 8B/10B encoder and the receiver decoder 740 is a 10B/8B decoder, i.e. the encoding/decoding algorithms of the receiver encoder 730 and the receiver decoder 740 correspond to each other, but the present disclosure is not limited thereto. In some embodiments, the receiving-end encoder 730 encodes the digital signals DCa-DCd having I-bit code words into digital signals DGa-DGd having J-bit code words, I and J are positive integers and I is not equal to J. In other embodiments, the receiver decoder 740 is configured to decode the digital signals DGa-DGd having J-bit code words into digital signals DEa-DEd having I-bit code words.

In other embodiments, the digital signals DGa-DGd outputted from the receiver-side encoder 730 are dc balanced signals, i.e., the respective codewords of the digital signals DGa-DGd have substantially equal numbers of 0 and 1.

Similar to the previous embodiments, the transmitter encoder 710 facilitates the signal transmission system 700 to be compatible with a multimedia signal source, and the receiver decoder 740 facilitates the signal transmission system 700 to be compatible with a video control chip or an audio control chip, which will not be described herein again. On the other hand, the transmitting side decoder 720 and the receiving side encoder 730 can reduce the minimum bandwidth requirements for the cable 150 in design.

For example, in one embodiment, both the transmitter encoder 114 and the transmitter encoder 710 are 8B/10B encoders, the transmitter decoder 720 is a 10B/8B decoder, and the respective data rates of the digital signals DDa-DDd are 4 Gbps. At this time, the data transmission rates of the digital signals DBa and DBb are only 10Gbps, respectively.

In another embodiment where the transmitter decoder 720 is omitted, the transmitter encoder 114 and the transmitter encoder 710 are both 8B/10B encoders, and the respective data rates of the digital signals DDa-DDd are 4 Gbps. At this time, the data transmission rate of each of the digital signals DBa and DBb is increased to 12.5 Gbps.

The present application provides several embodiments for converting 4 digital signals into 2 digital signals to reduce the number of signal lines, but the present application is not limited thereto. In practice, the circuit structure of these embodiments can also be applied to convert 8 digital signals into 4 digital signals, or 16 digital signals into 8 digital signals, and so on.

Certain terms are used throughout the description and claims to refer to particular components. However, it will be understood by those skilled in the art that the same elements may be referred to by different names. The specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect connection. Therefore, if the first component is coupled to the second component, it means that the first component can be directly connected to the second component through electrical connection or signal connection such as wireless transmission, optical transmission, etc., or indirectly connected to the second component through other components or connection means.

As used herein, the description of "and/or" includes any combination of one or more of the items listed. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

The above is merely a preferred embodiment of the present application and all equivalent changes and modifications made in the claims of the present application should be covered by the present application.

Description of the reference numerals

100,600,700 signal transmission system

110 transmitting end coding device

112 multiplexer

114,610,710 encoder of transmitting end

120 transmitting end physical layer driver

130 physical layer driver of receiving end

140 receiver side decoding device

142,620,740 decoder at receiving end

144 demultiplexer

150 cable

720 decoder at transmitting end

730 encoder at receiving end

DAa-DAd digital signal

DBa-DBb digital signals

DCa-DCd digital signals

DDa DDd digital signal

DEa-DEd digital signal

DFa DFd digital signal

DGa-DGd digital signal

Claims (10)

1. A signal transmission system, comprising:

a transmitting-side encoding apparatus, comprising:

a multiplexer for receiving a first digital signal and a second digital signal and generating an output, wherein the output comprises a plurality of M-bit codewords of the first digital signal and a plurality of M-bit codewords of the second digital signal alternately arranged with the plurality of M-bit codewords of the first digital signal, and M is a positive integer; and

a first transmitter encoder for receiving the output of the multiplexer and generating a plurality of N-bit codewords, N being a positive integer and M not equal to N, wherein the first transmitter encoder is configured to determine a current N-bit codeword of the plurality of N-bit codewords according to an inequality between the output of the multiplexer and a previous N-bit codeword of the plurality of N-bit codewords; and

a receiver decoding device, coupled to the transmitter encoding device, comprising:

a first receiver decoder for decoding the plurality of N-bit codewords to generate a plurality of I-bit codewords, wherein I is a positive integer and is not equal to N; and

a demultiplexer for alternately distributing the plurality of I-bit code words to a plurality of outputs of the demultiplexer.

2. The signal transmission system of claim 1, wherein if an arbitrary N-bit codeword among the plurality of N-bit codewords has a positive disparity, the arbitrary N-bit codeword is adjacent to one of the plurality of N-bit codewords having a negative disparity.

3. The signal transmission system according to claim 1, further comprising:

a second transmitter encoder for outputting the first digital signal and the second digital signal;

wherein the plurality of M-bit code words of the first digital signal have substantially equal numbers of 1's and 0's, and the plurality of M-bit code words of the second digital signal have substantially equal numbers of 1's and 0's.

4. The signal transmission system of claim 3, further comprising a second receiver decoder, wherein said second receiver decoder is configured to decode the outputs of said plurality of outputs of said demultiplexer.

5. The signal transmission system according to claim 1, further comprising:

a second transmitter encoder for outputting a third digital signal and a fourth digital signal, wherein the plurality of K-bit codewords of the third digital signal have substantially equal numbers of 1's and 0's, and the plurality of K-bit codewords of the fourth digital signal have substantially equal numbers of 1's and 0's, where K is a positive integer and K is not equal to M; and

a first transmitter decoder for decoding the third digital signal and the fourth digital signal to generate the first digital signal and the second digital signal, respectively.

6. The signal transmission system of claim 5, further comprising:

a first receiving-end encoder for encoding the outputs of the output ends of the demultiplexer to output a fifth digital signal and a sixth digital signal, wherein the J-bit code words of the fifth digital signal have substantially equal numbers of 1's and 0's, and the J-bit code words of the sixth digital signal have substantially equal numbers of 1's and 0's, wherein J is a positive integer and J is not equal to I; and

and the second receiving end decoder is used for decoding the fifth digital signal and the sixth digital signal.

7. A transmitting-side encoding apparatus, comprising:

a multiplexer for receiving a first digital signal and a second digital signal and generating an output, wherein the output comprises a plurality of M-bit codewords of the first digital signal and a plurality of M-bit codewords of the second digital signal alternately arranged with the plurality of M-bit codewords of the first digital signal, and M is a positive integer; and

a first transmitter encoder for receiving the output of the multiplexer and generating a plurality of N-bit codewords, N being a positive integer and M not equal to N, wherein the first transmitter encoder is configured to determine a current N-bit codeword of the plurality of N-bit codewords according to an inequality between the output of the multiplexer and a previous N-bit codeword of the plurality of N-bit codewords;

wherein the first transmitting encoder is configured to transmit the plurality of N-bit codewords to a receiving decoder, and the receiving decoder includes a demultiplexer and a first receiving decoder configured to decode the plurality of N-bit codewords.

8. The transmit-side encoding apparatus of claim 7, wherein if an arbitrary N-bit codeword among the N-bit codewords has a positive disparity, the arbitrary N-bit codeword is adjacent to one of the N-bit codewords having a negative disparity.

9. The transmitting-side encoding device according to claim 7, further comprising:

a second transmitter encoder for outputting the first digital signal and the second digital signal;

wherein the plurality of M-bit code words of the first digital signal have substantially equal numbers of 1's and 0's, and the plurality of M-bit code words of the second digital signal have substantially equal numbers of 1's and 0's.

10. The transmitting-side encoding device according to claim 7, further comprising:

a second transmitter encoder for outputting a third digital signal and a fourth digital signal, wherein the plurality of K-bit codewords of the third digital signal have substantially equal numbers of 1's and 0's, and the plurality of K-bit codewords of the fourth digital signal have substantially equal numbers of 1's and 0's, where K is a positive integer and K is not equal to M; and

a first transmitter decoder for decoding the third digital signal and the fourth digital signal to generate the first digital signal and the second digital signal, respectively.

Images