CN114255697B

CN114255697B - Control circuit, driving method thereof and display device

Info

Publication number: CN114255697B
Application number: CN202111618378.4A
Authority: CN
Inventors: 汪雅君; 孙建明; 张欢喜; 敦栋梁; 李孝文
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2023-01-31
Anticipated expiration: 2041-12-27
Also published as: CN114255697A

Abstract

The invention discloses a control circuit, a driving method thereof and a display device, which relate to the technical field of display and comprise the following steps: the circuit comprises a first circuit, a selection circuit and a second circuit, wherein the first circuit comprises a first node and a first output end, and the second circuit comprises a second node and a second output end; in the selection circuit, the control end of a first selection branch is connected with a first node, the control end of a second selection branch is coupled with a first output end, and the output ends of the first selection branch and the second selection branch are both connected with a second node; in a period, the first selection branch is used for transmitting a first level signal to the second node under the control of a signal of the first node; or the second selection branch is used for transmitting the first clock signal to the second node under the control of the signal of the first output end; the second circuit outputs a second level signal through a second output terminal under the action of a second node signal and a second clock signal. Therefore, the control signal with any duty ratio can be output, and the application flexibility is improved.

Description

Control circuit, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a control circuit, a driving method thereof, and a display device.

Background

From the CRT (Cathode Ray Tube) era to the liquid crystal era and now to the OLED (Organic Light-Emitting Diode) era, the display industry has been developing over decades. The display industry is closely related to our life, and display technologies cannot be separated from traditional mobile phones, flat panels, televisions and PCs to current intelligent wearable devices and VR and other electronic devices.

In general, a light-emitting control circuit is disposed in a display device to provide a light-emitting control signal to a pixel unit, so as to control a light-emitting device in the pixel unit to emit light, thereby implementing display of the display device. In the prior art, the minimum unit for dimming by the light-emitting control circuit is one cycle of the clock signal, and dimming with any duty ratio cannot be realized, which is not favorable for flexibility of light-emitting control.

Disclosure of Invention

In view of this, the present invention provides a control circuit, a driving method thereof, and a display device, wherein the control circuit can output a control signal with any duty ratio, and can achieve flexibility of light emission control when applied to the display device.

In a first aspect, the present invention provides a control circuit comprising: the circuit comprises a first circuit, a selection circuit and a second circuit, wherein the first circuit comprises a first node and a first output end, and the second circuit comprises a second node and a second output end;

the selection circuit comprises a first selection branch and a second selection branch, wherein the control end of the first selection branch is connected with the first node, the control end of the second selection branch is coupled with the first output end, and the output ends of the first selection branch and the second selection branch are both connected with the second node;

the first selection branch is used for transmitting a first level signal to the second node under the signal control of the first node in a period of time; or, the second selection branch is configured to transmit a first clock signal to the second node under the control of the signal at the first output terminal;

and the second circuit outputs a second level signal through the second output end under the action of a second node signal and a second clock signal.

In a second aspect, the present application provides a driving method of a control circuit, which is applied to the control circuit of the first aspect of the present invention, the driving method including:

controlling a signal of the first node in the first circuit to enable the first selection branch circuit to be conducted, and transmitting a first level signal to the second node; or, turning on the second selection branch, and transmitting the first clock signal to the second node;

and inputting a second clock signal to the second circuit, so that the second circuit outputs a second level signal through the second output end under the action of a second node signal and the second clock signal.

In a third aspect, the present invention further provides a display device including the control circuit provided in the first aspect of the present invention.

Compared with the prior art, the control circuit, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:

the control circuit, the driving method thereof and the display device are provided with a first circuit, a selection circuit and a second circuit, wherein the selection circuit comprises a first selection branch and a second selection branch, in a period of time, a signal of a first node can control the first selection branch to transmit a first level signal to the second node, and the second circuit outputs a second level signal of a first type under the action of a second node signal and a second clock signal; or, the signal at the first output terminal of the first circuit may control the second selection branch to transmit the first clock signal to the second circuit, and the second circuit outputs the second level signal of the second type under the action of the signal at the second node and the second clock signal. In the first type of second level signal and the second type of second level signal, one of the first type of second level signal and the second type of second level signal can be controlled to be a fixed level signal, the other one of the first type of second level signal and the second type of second level signal is a pulse signal, and the duty ratio of the output signal can be controlled by controlling the maintaining time of the two different types of second level signals, namely, the output signal with any duty ratio can be controlled and output. When the control circuit is applied to a display device, the control circuit can provide a light-emitting control signal for a pixel in the display device, so that the output of the light-emitting control signal with any duty ratio is realized, and the application flexibility of light-emitting control of the display device is favorably improved.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a block diagram of a control circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;

fig. 5 is a schematic diagram of another structure of the control circuit according to the embodiment of the present invention;

fig. 6 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;

fig. 7 is a schematic diagram of another structure of a control circuit according to an embodiment of the present invention;

fig. 8 is a schematic diagram illustrating another structure of a control circuit according to an embodiment of the present invention;

fig. 9 is a timing chart illustrating an operation of a first circuit in the control circuit according to the embodiment of the present invention;

fig. 10 is a timing diagram illustrating an operation of a control circuit in the control circuit according to the embodiment of the present invention;

FIG. 11 is a timing diagram illustrating another operation of a control circuit in the control circuit according to the embodiment of the present invention;

fig. 12 is a schematic structural diagram of a control circuit including a plurality of sub-circuits according to an embodiment of the present invention;

fig. 13 is a flowchart illustrating a driving method of a control circuit according to an embodiment of the invention;

fig. 14 is a top view of a display device according to an embodiment of the invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Fig. 1 is a block diagram of a control circuit according to an embodiment of the present invention, and referring to fig. 1, the control circuit according to the embodiment of the present invention includes: the circuit comprises a first circuit 10, a selection circuit 20 and a second circuit 30, wherein the first circuit 10 comprises a first node N1 and a first output end OUT1, and the second circuit 30 comprises a second node N2 and a second output end OUT2;

the selection circuit 20 includes a first selection branch 21 and a second selection branch 22, a control end of the first selection branch 21 is connected to the first node N1, a control end of the second selection branch 22 is coupled to the first output end OUT1, and output ends of the first selection branch 21 and the second selection branch 22 are both connected to the second node N2;

in one period, the first selection branch 21 is configured to transmit the first level signal VGH to the second node N2 under the signal control of the first node N1; alternatively, the second selection branch 22 is configured to transmit the first clock signal to the second node N2 under the control of the signal at the first output terminal OUT1;

the second circuit 30 outputs a second level signal through the second output terminal OUT2 under the action of the second node N2 signal and the second clock signal.

It is to be understood that fig. 1 only illustrates the block structure of the control circuit, and the specific structures of the first circuit 10, the selection circuit 20, and the second circuit 30 will be described in detail in the following embodiments.

The control circuit provided by the invention is provided with a first circuit 10, a selection circuit 20 and a second circuit 30, wherein the selection circuit 20 comprises a first selection branch 21 and a second selection branch 22, the first selection branch 21 and the second selection branch 22 can be selected to be conducted, and when the first selection branch 21 is conducted, the first selection branch 21 provides a signal for the second circuit 30; when the second selection branch 22 is turned on, a signal is provided to the second circuit 30 by the second selection branch 22; the second circuit 30, upon receiving the signal provided by the first selection branch 21 and the signal provided by the second selection branch 22, will output a different signal accordingly.

Specifically, in one period, the signal of the first node N1 may control the first selecting branch 21 to transmit the first level signal (e.g., the high level signal VGH) to the second node N2, and the second circuit 30 outputs the second level signal of the first type under the effect of the second node N2 signal and the second clock signal output by the second clock signal terminal CK2; alternatively, the signal at the first output terminal OUT1 of the first circuit 10 may control the second selecting branch 22 to transmit the first clock signal at the first clock signal terminal CK1 to the second circuit 30, and the second circuit 30 outputs the second level signal of the second type under the action of the signal at the second node N2 and the second clock signal. In the first type of second level signal and the second type of second level signal, one of the first type of second level signal and the second type of second level signal can be controlled to be a fixed level signal (for example, a high level signal or a low level signal), and the other one is a pulse signal. When the control circuit is applied to a display device, the control circuit can provide a light-emitting control signal for a pixel in the display device, so that the output of the light-emitting control signal with any duty ratio is realized, and the application flexibility of light-emitting control of the display device is favorably improved. Of course, the control circuit provided in the embodiment of the present invention may also be applied to other structures that require a duty ratio, and the present invention is not particularly limited to this.

Fig. 2 is a schematic structural diagram of a control circuit according to an embodiment of the present invention, which details the structure of the first selection branch 21.

Referring to fig. 2, in an alternative embodiment of the invention, the first selection branch 21 includes a first transistor M1, a gate of the first transistor M1 is connected to a first node N1, a first pole is connected to the first level signal terminal D1, and a second pole is connected to the second node N2.

In fig. 2, the first transistor M1 is merely an example of a P-type transistor, and the P-type transistor is turned on by a low-level signal and turned off by a high-level signal. In some other embodiments of the present invention, the first transistor M1 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the first transistor M1 is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The first selection branch 21 of the present invention will be described below by taking the first transistor M1 as a P-type transistor as an example.

Specifically, when the first selection branch 21 in the embodiment of the present invention includes the first transistor M1, the first transistor M1 is controlled by the signal of the first node N1 to be turned on or off. The first pole of the first transistor M1 is connected to the first level signal terminal D1, and the second pole is connected to the second node N2, when the first transistor M1 is turned on under the control of the first node N1 signal, the signal of the first level signal terminal D1 is transmitted to the second node N2 through the first transistor M1, and then is provided to the second circuit 30. When the second circuit 30 needs to receive the signal provided by the first selection branch 21, the first transistor M1 is controlled to be turned on by outputting a signal for controlling the first transistor M1 to be turned on to the first transistor M1 through the first node N1, and when the first transistor M1 is a P-type transistor, the first transistor M1 is controlled to be turned on by providing a low-level signal to the first transistor M1 through the first node N1. The first transistor M1 is adopted to form the first selection branch 21 in the present invention, which is beneficial to simplifying the structure of the control circuit, and further beneficial to simplifying the overall manufacturing process of the control circuit.

Fig. 3 is a schematic diagram of a structure of a control circuit according to an embodiment of the present invention, which details the structure of the second selection branch 22.

Referring to fig. 3, in an alternative embodiment of the present invention, the second selection branch 22 includes a second transistor M2, a gate of the second transistor M2 is coupled to the first output terminal OUT1, a first pole is connected to the first clock signal terminal CK1, and a second pole is connected to the second node N2.

In fig. 3, only the second transistor M2 is taken as an example of a P-type transistor, and the P-type transistor is turned on by a low-level signal and turned off by a high-level signal. In some other embodiments of the present invention, the second transistor M2 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the second transistor M2 is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The second selection branch 22 of the present invention will be described below by taking the second transistor M2 as a P-type transistor as an example.

Specifically, when the second selection branch 22 in the embodiment of the present invention includes the second transistor M2, the second transistor M2 is controlled by the signal of the first output terminal OUT1 of the first circuit 10 to be turned on or off. The first pole of the second transistor M2 is connected to the first clock signal terminal CK1, and the second pole is connected to the second node N2, when the second transistor M2 is turned on under the control of the signal of the first output terminal OUT1, the signal of the first clock signal terminal CK1 is transmitted to the second node N2 through the second transistor M2, and then is provided to the second circuit 30. When the second circuit 30 needs to receive the signal provided by the second selection branch 22, the first output terminal OUT1 of the first circuit 10 outputs a signal for controlling the second transistor M2 to be turned on to the second transistor M2, and when the second transistor M2 is a P-type transistor, the first output terminal OUT1 of the first circuit 10 provides a low-level signal to the second transistor M2 to control the second transistor M2 to be turned on. The second transistor M2 is used to form the second selection branch 22 in the present invention, which is beneficial to simplifying the structure of the control circuit, and further, is beneficial to simplifying the overall manufacturing process of the control circuit.

Since the first selection branch 21 and the second selection branch 22 are alternatively turned on, when the first transistor M1 and the second transistor M2 are of the same type, for example, both are P-type transistors, the signal output from the first output terminal OUT1 of the first circuit 10 and the signal at the first node N1 are different signals, and when one of the signals is a high level signal, the other signal is a low level signal.

Fig. 4 is a schematic diagram illustrating another structure of the control circuit according to an embodiment of the present invention, which further refines the structure of the second selection branch 22.

Referring to fig. 4, in an alternative embodiment of the invention, the second selection branch 22 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the gate of the second transistor M2, and a second end is connected to the first clock signal terminal CK1.

Specifically, in the embodiment of the present invention, the gate of the second transistor M2 in the second selection branch 22 is connected to a first capacitor C1, and a second end of the first capacitor C1 is connected to the first clock signal terminal CK1, for receiving the first clock signal sent by the first clock signal terminal CK1. When the second selection branch 22 is turned on and the first selection branch 21 is turned off, the second selection branch 22 transmits the first clock signal of the first clock signal terminal CK1 to the second node N2, and since the clock signal is in a transition state, in the present invention, when the gate of the second transistor M2 is connected to the first capacitor C1 and the first capacitor C1 is also connected to the first clock signal terminal CK1, it is advantageous to prevent the influence of the transition of the first clock signal on the output, thereby being advantageous to improve the output stability of the second selection branch 22.

Fig. 5 is a schematic diagram illustrating another structure of the control circuit according to an embodiment of the present invention, which further refines the structure of the second selection branch 22.

Referring to fig. 5, in an alternative embodiment of the invention, the second selection branch 22 further includes a third transistor M3, a gate of the third transistor M3 is connected to the second level signal terminal D2, a first pole is connected to the first output terminal OUT1, and a second pole is connected to the gate of the second transistor M2.

In the embodiment shown in fig. 5, the third transistor M3 in the second selection branch 22 is described by taking the third transistor M3 as a P-type transistor, and the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In some other embodiments of the present invention, the third transistor M3 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the third transistor M3 is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The second selection branch 22 of the present invention will be described by taking the third transistor M3 as a P-type transistor as an example.

Specifically, in the control circuit provided in the embodiment of the present invention, the second selecting branch 22 includes, in addition to the second transistor M2 and the first capacitor C1, a third transistor M3 connected to the gate of the second transistor M2, wherein an output end of the third transistor M3 is connected to the gate of the second transistor M2, and an input end of the third transistor M3 is connected to the first output end OUT1. Optionally, the signal of the second level signal terminal D2 can keep the third transistor M3 in a normally-on state, and when the third transistor M3 is a P-type transistor, the signal of the second level signal terminal D2 is kept in a low level signal, which is equivalent to introducing a normally-on transistor between the second transistor M2 and the first output terminal OUT1, so as to ensure that the signal output by the first output terminal OUT1 can be stably transmitted to the second transistor M2 when the second selecting branch 22 is turned on.

Fig. 6 is a schematic diagram of another structure of the control circuit according to an embodiment of the present invention, which details the module structure of the first circuit 10.

Referring to fig. 6, in an alternative embodiment of the present invention, the first circuit 10 further includes a first control unit 11, a second control unit 12, a first output unit 13, a third node N3 and a fourth node N4;

the first control unit 11 is configured to output a first control signal and control a potential of the third node N3; the second control unit 12 is configured to output a second control signal under the control of the signal of the third node N3; the first output unit 13 is configured to control signal output of the first output terminal OUT1 according to a first control signal and a second control signal.

Specifically, in the control circuit provided in the embodiment of the present invention, the first control unit 11, the second control unit 12, and the first output unit 13 are introduced into the first circuit 10, and the first control unit 11 and the second control unit 12 jointly control the signal output of the first output terminal OUT1 of the first output unit 13. It should be understood that fig. 6 only shows the scheme that the first output terminal OUT1 of the first circuit 10 is connected to only the selection circuit 20, and in some other embodiments of the present invention, the first output terminal OUT1 of the first circuit 10 may be connected to other circuit structures besides the selection circuit 20, which will be described in the following embodiments.

Optionally, the first control signal output by the first control unit 11 may include a first signal output to the third node N3 and a second signal output to the fourth node N4, and the second control signal output by the second control unit 12 also includes two signals output to the first output unit 13, where the signal of the first node N1 controls the first output unit 13 to output one level signal, and the signal of the fourth node N4 controls the first output unit 13 to output another level signal, so as to implement fine control on the signal output by the first output unit 13.

Fig. 7 is a schematic diagram illustrating another structure of the control circuit according to an embodiment of the present invention, which details the circuit structures of the first control unit 11, the second control unit 12, and the first output unit 13.

Referring to fig. 7, in an alternative embodiment of the present invention, the first control unit 11 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8, wherein a gate of the fourth transistor M4 is connected to the third clock signal terminal CK3, a first pole is connected to the second level signal terminal D2, and a second pole is connected to the third node N3; the grid electrode of the fifth transistor M5 is connected with the first electrode of the sixth transistor M6, the first electrode is connected with the third node N3, and the second electrode is connected with the third clock signal terminal CK3; the gate of the sixth transistor M6 is connected to the third clock signal terminal CK3, the first pole is connected to the fourth node N4, and the second pole is connected to the start trigger signal terminal STV1; the gate of the seventh transistor M7 is connected to the second pole of the fourth transistor M4, the first pole is connected to the first level signal terminal D1, and the second pole is connected to the first pole of the eighth transistor M8; the eighth transistor M8 has a gate connected to the fourth clock signal terminal CK4 and a second pole connected to the fourth node N4.

The embodiment shown in fig. 7 shows a scheme that the first control unit 11 includes 5 transistors, where the 5 transistors are the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8, and the embodiment in fig. 7 is described by taking as an example that each transistor in the first control unit 11 is a P-type transistor, and the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In some other embodiments of the present invention, each transistor in the first control unit 11 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the transistor is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The first control unit 11 of the present invention will be described below by taking an example in which each transistor in the first control unit 11 is a P-type transistor.

Specifically, referring to fig. 7, when the start trigger signal terminal STV1 inputs a high level signal to the sixth transistor M6, the signals of the third clock signal terminal CK3 and the second level signal terminal D2 are low level signals, and the signal of the fourth clock signal terminal CK4 is a high level signal, the fourth transistor M4, the sixth transistor M6 and the seventh transistor M7 are turned on, the fifth transistor M5 and the eighth transistor M8 are turned off, the high level signal of the start trigger signal terminal STV1 is transmitted to the fourth node N4, and the low level signal of the second level signal terminal D2 is transmitted to the third node N3. That is, one of the signals transmitted from the first control unit 11 to the third node N3 and the fourth node N4 is a low level signal and one is a high level signal.

When the start trigger signal terminal STV1 outputs a low level signal to the sixth transistor M6, the signal of the third clock signal terminal CK3 is a high level signal, and the signal of the fourth clock signal terminal CK4 is a low level signal, the fourth transistor M4 and the sixth transistor M6 are turned off, the eighth transistor M8 is turned on, the gate of the seventh transistor M7 maintains a low level and is also turned on, and the high level signal of the first level signal terminal D1 connected to the seventh transistor M7 is transmitted to the fourth node N4. The low level signal of the gate of the seventh transistor M7 will be transmitted to the third node N3.

With continued reference to fig. 7, in an alternative embodiment of the present invention, the second control unit 12 includes a second capacitor C2, a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11, wherein the first terminal of the second capacitor C2 and the gate of the ninth transistor M9 are both connected to the third node N3, the first pole of the ninth transistor M9 is connected to the fourth clock signal terminal CK4, and the second terminal of the second capacitor C2 is connected to the second pole of the ninth transistor M9; a gate of the tenth transistor M10 is connected to the fourth clock signal terminal CK4, a first pole thereof is connected to a second pole of the ninth transistor M9, and the second pole thereof is connected to the first node N1; the gate of the eleventh transistor M11 is connected to the fourth node N4, the first pole is connected to the first node N1, and the second pole is connected to the first level signal terminal D1.

The embodiment shown in fig. 7 shows a scheme that the second control unit 12 includes three transistors and one second capacitor C2, and the embodiment shown in fig. 7 is described by taking as an example that each transistor in the second control unit 12 is a P-type transistor, and the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In some other embodiments of the present invention, each transistor in the second control unit 12 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the transistor is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The first control unit 11 of the present invention will be described below by taking an example in which each transistor in the second control unit 12 is a P-type transistor.

Specifically, with continued reference to the second control unit 12 in fig. 7, when the third node N3 is a low level signal, the fourth node N4 is a high level signal, and the signal of the fourth clock signal terminal CK4 is a high level signal, the ninth transistor M9 is turned on, the tenth transistor M10 and the eleventh transistor M11 are turned off, and the high level signal of the fourth node N4 is transmitted to the first output unit 13.

When the third node N3 is a low level signal, the fourth node N4 is a high level signal, and the signal of the fourth clock signal terminal CK4 is a low level signal, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned off, and the low level signal of the fourth clock signal terminal CK4 is transmitted to the first node N1.

When the fourth node N4 is a low level signal and the signal of the fourth clock signal terminal CK4 is a high level signal, the eleventh transistor M11 is turned on, the tenth transistor M10 is turned off, and the high level signal of the first level signal terminal D1 can be transmitted to the first node N1 through the eleventh transistor M11.

By the control action of the first control unit 11 and the second control unit 12, it is possible to select to output a low level signal or a high level signal to the first node N1, so that it is possible to output a low level signal or a high level signal to the first output unit 13.

With continued reference to fig. 7, in an alternative embodiment of the present invention, the first output unit 13 includes a twelfth transistor M12, a thirteenth transistor M13, a third capacitor C3, and a fourth capacitor C4, wherein a first end of the third capacitor C3 and a gate of the twelfth transistor M12 are both connected to the first node N1, a second end of the third capacitor C3 and a first pole of the twelfth transistor M12 are both connected to the first level signal terminal D1, and a second pole of the twelfth transistor M12 is connected to the first output terminal OUT1; the gate of the thirteenth transistor M13 and the first end of the fourth capacitor C4 are both connected to the fourth node N4, the second end of the fourth capacitor C4 is connected to the fourth clock signal terminal CK4, the first pole of the thirteenth transistor M13 is connected to the second level signal terminal D2, and the second pole is connected to the first output terminal OUT1.

The embodiment shown in fig. 7 shows a scheme that the first output unit 13 includes two transistors and two capacitors, and the embodiment of fig. 7 is described by taking as an example that each transistor in the first output unit 13 is a P-type transistor, and the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In some other embodiments of the present invention, each transistor in the first output unit 13 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the transistor is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The first control unit 11 of the present invention will be described below by taking an example in which each transistor in the first output unit 13 is a P-type transistor.

Specifically, when the signal at the first node N1 is a low level signal and the signal at the fourth node N4 is a high level signal, the twelfth transistor M12 is turned on, the thirteenth transistor M13 is turned off, and the high level signal at the first level signal terminal D1 is output from the first output terminal OUT1. When the signal at the first node N1 is a high level signal and the signal at the fourth node N4 is a low level signal, the twelfth transistor M12 is turned off, the thirteenth transistor M13 is turned on, and the low level signal at the second level signal terminal D2 is outputted from the first output terminal OUT1. Therefore, by introducing the twelfth transistor M12 and the thirteenth transistor M13 in the first output unit 13 and by the control of the signals of the first node N1 and the fourth node N4, the first output unit 13 can be controlled to output a low level signal or a high level signal through the first output terminal OUT1.

The embodiment shown in fig. 6 details the circuit configuration of the third control unit 31, the fourth control unit 32, and the second output unit 33 of the second circuit 30.

Referring to fig. 6, in an alternative embodiment of the present invention, the second circuit 30 includes a third control unit 31, a fourth control unit 32, a second output unit 33, a fifth node N5, a sixth node N6, and a seventh node N7;

the third control unit 31 is configured to output a third control signal and control the potential of the fifth node N5; the fourth control unit 32 is configured to output a fourth control signal to the sixth node N6 under the control of the signal of the fifth node N5; the second output unit 33 is configured to control the second output terminal OUT2 to output the light emitting control signal according to the third control signal and the fourth control signal.

Specifically, in the control circuit provided in the embodiment of the present invention, the third control unit 31, the fourth control unit 32, and the second output unit 33 are introduced into the second circuit 30, and the third control unit 31 and the fourth control unit 32 jointly control the signal output of the second output terminal OUT2 of the second output unit 33.

Optionally, the third control signal output by the third control unit 31 may include a third signal output to the fifth node N5 and a fourth signal output to the seventh node N7, and the second control signal output by the fourth control unit 32 also includes two signals output to the second output unit 33, where the signal of the fifth node N5 controls the second output unit 33 to output one level signal, and the signal of the seventh node N7 controls the second output unit 33 to output another level signal, so as to implement fine control on the signal output by the second output unit 33.

Fig. 8 is a schematic diagram of another structure of the control circuit according to an embodiment of the present invention, which details the circuit structures of the third control unit 31, the fourth control unit 32, and the second output unit 33 of the second circuit 30.

Referring to fig. 8, in an alternative embodiment of the present invention, the third control unit 31 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17 and an eighteenth transistor M18, wherein a gate of the fourteenth transistor M14 is connected to the third clock signal terminal CK3, a first pole is connected to the second level signal terminal D2, and a second pole is connected to a first pole of the fifteenth transistor M15 and is connected to the fifth node N5; the gate of the fifteenth transistor M15 is connected to the first pole of the sixteenth transistor M16, the first pole is connected to the fifth node N5, and the second pole is connected to the third clock signal terminal CK3; the gate of the sixteenth transistor M16 is connected to the third clock signal terminal CK3, the first pole is connected to the seventh node N7, and the second pole is connected to the second clock signal terminal CK2; the gate of the seventeenth transistor M17 is connected to the second pole of the fourteenth transistor M14, the first pole is connected to the first level signal terminal D1, and the second pole is connected to the first pole of the eighteenth transistor M18; the gate of the eighteenth transistor M18 is connected to the fourth clock signal terminal CK4, and the second pole is connected to the seventh node N7.

The embodiment shown in fig. 8 shows a scheme that the third control unit 31 includes 5 transistors, where the 5 transistors are the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17 and the eighteenth transistor M18, and the embodiment in fig. 8 is described by taking as an example that each transistor in the third control unit 31 is a P-type transistor, and the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In some other embodiments of the present invention, each transistor in the third control unit 31 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the transistor is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The third control unit 31 of the present invention will be described below by taking an example in which each transistor in the third control unit 31 is a P-type transistor.

Specifically, referring to fig. 8, when the fourth clock signal terminal CK4 inputs a high level signal to the sixteenth transistor M16, the signals of the third clock signal terminal CK3 and the second level signal terminal D2 are low level signals, and the signal of the fourteenth clock signal terminal is a high level signal, the fourteenth transistor M14, the sixteenth transistor M16 and the seventeenth transistor M17 are turned on, the fifteenth transistor M15 and the eighteenth transistor M18 are turned off, the high level signal of the fourth clock signal terminal CK4 is transmitted to the seventh node N7, and the low level signal of the second level signal terminal D2 is transmitted to the fifth node N5. That is, one of the signals transmitted from the third control unit 31 to the fifth node N5 and the fourteenth node is a low level signal and one thereof is a high level signal.

When the signal of the fourth clock signal terminal CK4 is a low level signal and the signal of the third clock signal terminal CK3 is a high level signal, the fourteenth transistor M14 and the sixteenth transistor M16 are turned off, the eighteenth transistor M18 is turned on, the gate of the seventeenth transistor M17 maintains a low level and is also turned on, and the high level signal of the first level signal terminal D1 connected to the seventeenth transistor M17 is transmitted to the seventh node N7. The low level signal of the gate of the seventeenth transistor M17 will be transmitted to the fifth node N5.

With continued reference to fig. 8, in an alternative embodiment of the present invention, the fourth control unit 32 includes a fifth capacitor C5, a nineteenth transistor M19, a twentieth transistor M20 and a twenty-first transistor M21, wherein the first terminal of the fifth capacitor C5 and the gate of the nineteenth transistor M19 are both connected to the fifth node N5, the first pole of the nineteenth transistor M19 is connected to the fourth clock signal terminal CK4, and the second terminal of the fifth capacitor C5 is connected to the second pole of the nineteenth transistor M19; a gate of the twentieth transistor M20 is connected to the fourth clock signal terminal CK4, a first pole thereof is connected to the second pole of the nineteenth transistor M19, and a second pole of the twentieth transistor M20 is connected to the first pole of the twenty-first transistor M21 and to the sixth node N6; the gate of the twenty-first transistor M21 is connected to the second pole of the sixth transistor M6, and the second pole of the twenty-first transistor M21 is connected to the first level signal terminal D1.

The embodiment shown in fig. 8 shows a scheme that the fourth control unit 32 includes three transistors and a fifth capacitor C5, and the embodiment of fig. 8 is described by taking as an example that each transistor in the fourth control unit 32 is a P-type transistor, and the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In some other embodiments of the present invention, each transistor in the fourth control unit 32 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the transistor is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The first control unit 11 of the present invention will be described below by taking an example in which each transistor in the fourth control unit 32 is a P-type transistor.

Specifically, with continued reference to the fourth control unit 32 in fig. 8, when the fifth node N5 is a low level signal, the seventh node N7 is a high level signal, and the signal of the fourth clock signal terminal CK4 is a high level signal, the nineteenth transistor M19 is turned on, the twentieth transistor M20 and the twenty-first transistor M21 are turned off, and the high level signal of the seventh node N7 is transmitted to the second output unit 33.

When the fifth node N5 is a low level signal, the seventh node N7 is a high level signal, and the signal of the fourth clock signal terminal CK4 is a low level signal, the twentieth transistor M20 is turned on, the twenty-first transistor M21 is turned off, and the low level signal of the fourth clock signal terminal CK4 is transmitted to the sixth node N6.

When the seventh node N7 is a low level signal and the signal of the fourth clock signal terminal CK4 is a high level signal, the twenty-first transistor M21 is turned on, the twentieth transistor M20 is turned off, and the high level signal of the first level signal terminal D1 can be transmitted to the sixth node N6 through the twenty-first transistor M21.

By the control action of the third control unit 31 and the fourth control unit 32, it is possible to select to output a low level signal or a high level signal to the sixth node N6, and thereby it is possible to output a low level signal or a high level signal to the second output unit 33.

With continued reference to fig. 8, in an alternative embodiment of the present invention, the second output unit 33 includes a twenty-second transistor M22, a twenty-third transistor M23, a sixth capacitor C6 and a seventh capacitor C7, wherein the first terminal of the sixth capacitor C6 and the gate of the twenty-second transistor M22 are both connected to the sixth node N6, the second terminal of the sixth capacitor C6 is connected to the first clock signal terminal CK1, the first pole of the twenty-second transistor M22 is connected to the second node N2, and the second pole of the twenty-second transistor M22 is connected to the second output terminal OUT2; the gate of the twenty-third transistor M23 and the first end of the seventh capacitor C7 are both connected to the first pole of the sixteenth transistor M16, the second end of the seventh capacitor C7 is connected to the fourth clock signal terminal CK4, the first pole of the twenty-third transistor M23 is connected to the second level signal terminal D2, and the second pole is connected to the first output terminal OUT1.

The embodiment shown in fig. 8 shows a scheme that the second output unit 33 includes two transistors and two capacitors, and the embodiment of fig. 8 is described by taking as an example that each transistor in the second output unit 33 is a P-type transistor, and the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. In some other embodiments of the present invention, each transistor in the second output unit 33 may also be embodied as an N-type transistor, which is not specifically limited in this respect, and when the transistor is an N-type transistor, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The first control unit 11 of the present invention will be described below by taking an example in which each transistor in the second output unit 33 is a P-type transistor.

Specifically, when the signal at the sixth node N6 is a low-level signal and the signal at the seventh node N7 is a high-level signal, the twentieth transistor M22 is turned on, the twenty-third transistor M23 is turned off, and the second node N2 signal is output from the second output terminal OUT 2. When the signal at the sixth node N6 is a high level signal and the signal at the seventh node N7 is a low level signal, the twenty-second transistor M22 is turned off, the twenty-third transistor M23 is turned on, and the low level signal at the second level signal terminal D2 is output from the second output terminal OUT 2. Therefore, by introducing the twenty-second transistor M22 and the twenty-third transistor M23 in the second output unit 33 and by the control of the signals of the sixth node N6 and the seventh node N7, the second output unit 33 can be controlled to output a level signal or a low level signal corresponding to the second node N2 through the second output terminal OUT 2. The foregoing embodiment mentions that the second level signal output by the second output terminal OUT2 includes a level signal corresponding to the second node N2 and a low level signal. The level signal corresponding to the second node N2 is a signal output by the first selection branch 21 or a signal output by the second selection branch 22, and may be, for example, a high level signal or a clock signal. The time of the corresponding signal or low level signal of the second node N2 output by the second output end OUT2 is adjusted, so that the second output end OUT2 can output control signals with different duty ratios, the requirements of the circuit on signals with different duty ratios are met, and the application flexibility of the control circuit is favorably improved.

Fig. 9 is a timing chart illustrating an operation of the first circuit 10 in the control circuit according to the embodiment of the present invention, and the following describes an operation process of the first circuit 10 in the control circuit according to the present invention with reference to fig. 8 and fig. 9.

In the first stage t1, the signal of the start trigger signal terminal STV1 is at a high level, the signal of the third clock signal terminal CK3 is at a low level, and the signal of the fourth clock signal terminal CK4 is at a high level. At this time, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are turned on, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are turned off, the high level signal of the start trigger signal terminal STV1 is transmitted to the fourth node N4, and the eleventh transistor M11 and the thirteenth transistor M13 are turned off; the low level signal of the second level signal terminal D2 is transmitted to the third node N3, turning on the seventh transistor M7 and the ninth transistor M9. The gate potential of the twelfth transistor M12 is not changed, and the third storage capacitor maintains the gate potential of the twelfth transistor M12 in the previous frame, so that the twelfth transistor M12 is turned off, and thus the first output terminal OUT1 outputs the level of the previous frame, which is low.

In the second stage t2, the signal of the start trigger signal terminal STV1 is at a high level, the signal of the third clock signal terminal CK3 is at a high level, the signal of the fourth clock signal terminal CK4 is at a low level, the fourth transistor M4 and the sixth transistor M6 are turned off, the fifth transistor M5 and the tenth transistor M10 are turned on, the gates of the seventh transistor M7 and the ninth transistor M9 are maintained at a low level through the second capacitor C2, and the seventh transistor M7 and the ninth transistor M9 are turned on. A low level signal corresponding to the fourth clock signal terminal CK4 is transmitted to the tenth transistor M10 through the ninth transistor M9, and then transmitted to the first node N1, so as to control the twelfth transistor M12 to be turned on, and a high level signal of the first level signal terminal D1 is output through the first output terminal OUT1, that is, the first output terminal OUT1 outputs a high level signal. Meanwhile, the high level signal of the first level signal terminal D1 is transmitted to the thirteenth transistor M13 through the seventh transistor M7 and the eighth transistor M8, turning off the thirteenth transistor M13.

In the third stage t3, the signal of the start trigger signal terminal STV1 is at a high level, the signal of the third clock signal terminal CK3 is at a low level, and the signal of the fourth clock signal terminal CK4 is at a high level, at this time, the fourth transistor M4 and the sixth transistor M6 are turned on, the fifth transistor M5, the eighth transistor M8, the tenth transistor M10, and the eleventh transistor M11 are turned off, the third capacitor C3 maintains the gate potential of the twelfth transistor M12, so that the twelfth transistor M12 is turned on, and the first output terminal OUT1 outputs a high level signal of the first level signal terminal D1. The signal of the start triggering signal terminal STV1 and the signal of the fourth clock signal terminal CK4 control the thirteenth transistor M13 to be turned off.

In the fourth phase t4, the signal of the start trigger signal terminal STV1 is at a low level, the signal of the third clock signal terminal CK3 is at a high level, and the signal of the fourth clock signal terminal CK4 is at a low level, at this time, the fourth transistor M4 and the sixth transistor M6 are turned off, the eighth transistor M8 and the tenth transistor M10 are turned on, the gates of the seventh transistor M7 and the ninth transistor M9 maintain a low level through the second capacitor C2, and the seventh transistor M7 and the ninth transistor M9 are turned on. The low level signal of the fourth clock signal terminal CK4 is transmitted to the twelfth transistor M12 through the ninth transistor M9 and the tenth transistor M10, turning on the twelfth transistor M12, so that the first output terminal OUT1 outputs the high level signal of the first level signal terminal D1. Meanwhile, the high level signal of the first level signal terminal D1 is transmitted to the thirteenth transistor M13 through the seventh transistor M7 and the eighth transistor M8, turning off the thirteenth transistor M13.

In the fifth stage t5, the signal of the start trigger signal terminal STV1 is at a low level, the signal of the third clock signal terminal CK3 is at a low level, the signal of the fourth clock signal terminal CK4 is at a high level, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, and the eleventh transistor M11 are turned on, and the eighth transistor M8 and the tenth transistor M10 are turned off. The high level signal of the first level signal terminal D1 is transmitted to the twelfth transistor M12 through the eleventh transistor M11, so that the twelfth transistor M12 is turned off; the low level signal of the start triggering signal terminal STV1 is transmitted to the thirteenth transistor M13 through the sixth transistor M6, so that the thirteenth transistor M13 is turned on, and the low level signal of the second level signal terminal D2 is transmitted to the first output terminal OUT1, so that the first output terminal OUT1 outputs a low level signal.

It can be seen that the first output terminal OUT1 of the first circuit 10 outputs a low level signal in the first stage and the fifth stage, and outputs a high level signal in the second stage, the third stage and the fourth stage.

It should be noted that, the structure of the second circuit 30 is substantially the same as that of the first circuit 10, and the detailed timing sequence and the working process of the second circuit 30 can refer to the first circuit 10, which is not described herein again in this embodiment of the present invention.

Fig. 10 is a timing chart illustrating an operation of a control circuit in a control circuit according to an embodiment of the present invention, fig. 11 is a timing chart illustrating another operation of the control circuit in the control circuit according to the embodiment of the present invention, and an operation process of the control circuit according to the present invention will be described with reference to fig. 8, fig. 10, and fig. 11.

When the signal of the second clock signal terminal CK2 is at a low level, the signal of the fourth clock signal terminal CK4 is at a low level, and the signal of the sixth node N6 is at a high level, the signal of the seventh node N7 is at a low level, the twenty-third transistor M23 is turned on, the twenty-second transistor M22 is turned off, and the low-level signal of the second level signal terminal D2 is transmitted to the second output terminal OUT2, that is, the second output terminal OUT2 outputs a low level.

When the signal of the second clock signal terminal CK2 is at a high level, the signal of the third clock signal terminal CK3 is at a low level, and the signal of the sixth node N6 is at a low level, the twenty-third transistor M23 is turned off, the twenty-second transistor M22 is turned on, and the signal of the second node N2 is transmitted to the second output terminal OUT2, that is, the signal output by the second output terminal OUT2 is the signal of the second node N2.

The signal of the second node N2 is a signal output by the first selection branch 21 or a signal output by the second selection branch 22, and when the first selection branch 21 is turned on, the signal of the second node N2 is a high-level signal of the first level signal terminal D1; when the second selection branch 22 is turned on, the signal at the second node N2 is the signal at the first clock signal terminal CK1. As can be seen by comparing the timing charts of fig. 10 and 11, when the waveforms of the second clock signal terminal CK2 are different, the duty ratios of the signals output from the second output terminal OUT2 are different. Therefore, by adjusting the waveforms of the first clock signal terminal CK1 and the second clock signal terminal CK2, the second output terminal OUT2 can output signals with different duty ratios, thereby being beneficial to improving the control flexibility of the output signals of the control circuit.

Fig. 12 is a schematic structural diagram of a control circuit including a plurality of sub-circuits according to an embodiment of the present invention.

Referring to fig. 12, in an alternative embodiment of the present invention, the control circuit includes a plurality of cascaded sub-circuits, each of which includes a first circuit 10, a selection circuit 20 and a second circuit 30, a first output terminal OUT1 of the nth stage sub-circuit is connected to a start trigger signal terminal STV1 of the (n + 1) th stage sub-circuit, where n is greater than or equal to 1; each second output terminal OUT2 is used for connecting with a pixel driving circuit.

Specifically, each of the sub-circuits in the embodiment shown in fig. 12 includes the first circuit 10, the selection circuit 20 and the second circuit 30 in the foregoing embodiment, and each of the sub-circuits is cascaded, and a signal output by the first output terminal OUT1 of the first circuit 10 in this stage of sub-circuit serves as a start trigger signal for the first circuit 10 in the next stage of sub-circuit, so that the second output terminal OUT2 of the sub-circuit outputs a signal stage by stage. Optionally, the second output terminal OUT2 of the sub-circuit is connected to the pixel driving circuit, and a signal output by the second output terminal OUT2 is used as a light-emitting control signal of the pixel driving circuit and is connected to the light-emitting control signal terminal emit of the pixel driving circuit. Because the signal output by the second output end OUT2 in the control circuit can be controlled to be a signal with any duty ratio, when the signal is used as a light-emitting control signal, the signal can output the light-emitting control signal with any duty ratio, and when the signal is applied to a display device, the application flexibility of light-emitting control of the display device can be improved.

Based on the same inventive concept, the present invention further provides a driving method of a control circuit, which is applied to the control circuit provided in any of the above embodiments, fig. 13 is a flowchart of the driving method of the control circuit provided in the embodiment of the present invention, please refer to fig. 1 to 13, and the driving method includes:

controlling a signal of a first node N1 in the first circuit 10 to turn on the first selection branch 21, and transmitting a first level signal to a second node N2; alternatively, the second selection branch 22 is turned on, and the first clock signal is transmitted to the second node N2;

the second clock signal is input to the second circuit 30, so that the second circuit 30 outputs a second level signal through the second output terminal OUT2 under the action of the second node N2 signal and the second clock signal.

Specifically, in the penalty control method provided in the embodiment of the present invention, in a period of time, the signal of the first node N1 may control the first selecting branch 21 to transmit the first level signal to the second node N2, and the second circuit 30 outputs the second level signal of the first type under the action of the signal of the second node N2 and the second clock signal; alternatively, the signal at the first output terminal OUT1 of the first circuit 10 may control the second selecting branch 22 to transmit the first clock signal to the second circuit 30, and the second circuit 30 outputs the second level signal of the second type under the action of the signal at the second node N2 and the second clock signal. In the first type of second level signal and the second type of second level signal, one of the first type of second level signal and the second type of second level signal can be controlled to be a fixed level signal (for example, a high level signal and/or a low level signal), and the other one of the first type of second level signal and the second type of second level signal is a pulse signal. When the control circuit is applied to a display device, the control circuit can provide a light-emitting control signal for a pixel in the display device, so that the output of the light-emitting control signal with any duty ratio is realized, and the application flexibility of light-emitting control of the display device is favorably improved.

In an alternative embodiment of the present invention, when the second clock signal is the first state level signal, the second level signal output by the second output terminal OUT2 is the same as the second node N2 signal; when the second clock signal is the second state level signal, the second level signal output by the second output terminal OUT2 is the same as the third level signal. In this manner, by controlling the state of the second clock signal, for example, controlling the second clock signal to output a high level signal or a low level signal, the second output terminal OUT2 can be made to output a different level signal, for example, the same signal as the second node N2 signal, or the same signal as the third level signal. By controlling the duration of the second clock signal as a high-level signal or a low-level signal, the second output end OUT2 can output signals with different duty ratios, so that the requirements of the control signal on different duty ratios are met, and the application flexibility of the control circuit is improved.

Based on the same inventive concept, the present invention further provides a display apparatus, and fig. 14 is a top view of the display apparatus according to the embodiment of the present invention, wherein the display apparatus 200 includes the control circuit according to any one of the embodiments of the present invention. Because the control circuit can output control signals with different duty ratios, the control signals output by the control circuit can be used as light-emitting control signals in the display device, so that the light-emitting control signals realize different duty ratios, and the flexibility of the display device on light-emitting control is improved.

It should be noted that, for the embodiment of the display device provided by the present invention, reference may be made to the embodiment of the control circuit in the present invention, and repeated descriptions are omitted. The display device provided by the embodiment of the invention can be embodied as any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In summary, the control circuit, the driving method thereof and the display device provided by the invention at least achieve the following beneficial effects:

the control circuit, the driving method thereof and the display device are provided with a first circuit, a selection circuit and a second circuit, wherein the selection circuit comprises a first selection branch and a second selection branch, in a period of time, a signal of a first node can control the first selection branch to transmit a first level signal to a second node, and the second circuit outputs a second level signal of a first type under the action of a second node signal and a second clock signal; or, the signal at the first output terminal of the first circuit may control the second selection branch to transmit the first clock signal to the second circuit, and the second circuit outputs the second level signal of the second type under the action of the signal at the second node and the second clock signal. In the first type of second level signal and the second type of second level signal, one of the first type of second level signal and the second type of second level signal can be controlled to be a fixed level signal, the other one of the first type of second level signal and the second type of second level signal is a pulse signal, and the duty ratio of the output signal can be controlled by controlling the maintaining time of the two different types of second level signals, namely, the output signal with any duty ratio can be controlled and output. When the control circuit is applied to a display device, the control circuit can provide a light-emitting control signal for a pixel in the display device, so that the output of the light-emitting control signal with any duty ratio is realized, and the application flexibility of light-emitting control of the display device is favorably improved.

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A control circuit, comprising: the circuit comprises a first circuit, a selection circuit and a second circuit, wherein the first circuit comprises a first node and a first output end, and the second circuit comprises a second node and a second output end;

the first selection branch is used for transmitting a first level signal to the second node under the control of the signal of the first node in a period; or, the second selection branch is configured to transmit a first clock signal to the second node under the control of the signal at the first output terminal;

the second circuit outputs a second level signal through the second output end under the action of a second node signal and a second clock signal;

the first circuit further comprises a first control unit, a second control unit, a first output unit, a third node and a fourth node;

the first control unit is used for outputting a first control signal and controlling the potential of the third node; the second control unit is used for outputting a second control signal under the signal control of the third node; the first output unit is used for controlling the signal output of the first output end according to the first control signal and the second control signal;

the second circuit comprises a third control unit, a fourth control unit, a second output unit, a fifth node, a sixth node and a seventh node;

the third control unit is used for outputting a third control signal and controlling the potential of the fifth node; the fourth control unit is used for outputting a fourth control signal to a sixth node under the control of the signal of the fifth node; the second output unit is used for controlling the second output end to output a light-emitting control signal according to the third control signal and the fourth control signal.

2. The control circuit of claim 1, wherein the first selection branch comprises a first transistor, a gate of the first transistor is connected to the first node, a first pole of the first transistor is connected to the first level signal terminal, and a second pole of the first transistor is connected to the second node.

3. The control circuit of claim 1, wherein the second selection branch comprises a second transistor, a gate of the second transistor is coupled to the first output terminal, a first pole of the second transistor is connected to the first clock signal terminal, and a second pole of the second transistor is connected to the second node.

4. The control circuit of claim 3, wherein the second selection branch further comprises a first capacitor, a first terminal of the first capacitor is connected to the gate of the second transistor, and a second terminal of the first capacitor is connected to the first clock signal terminal.

5. The control circuit of claim 3, wherein the second selection branch further comprises a third transistor, a gate of the third transistor is connected to the second level signal terminal, a first pole of the third transistor is connected to the first output terminal, and a second pole of the third transistor is connected to the gate of the second transistor.

6. The control circuit according to claim 1, wherein the first control unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein a gate of the fourth transistor is connected to a third clock signal terminal, a first pole is connected to a second level signal terminal, and a second pole is connected to the third node; the grid electrode of the fifth transistor is connected with the first pole of the sixth transistor, the first pole of the fifth transistor is connected with the third node, and the second pole of the fifth transistor is connected with the third clock signal end; a grid electrode of the sixth transistor is connected with the third clock signal end, a first pole of the sixth transistor is connected with the fourth node, and a second pole of the sixth transistor is connected with a starting trigger signal end; the grid electrode of the seventh transistor is connected with the second pole of the fourth transistor, the first pole of the seventh transistor is connected with the first level signal end, and the second pole of the seventh transistor is connected with the first pole of the eighth transistor; and the grid electrode of the eighth transistor is connected with a fourth clock signal end, and the second pole of the eighth transistor is connected with the fourth node.

7. The control circuit according to claim 1, wherein the second control unit comprises a second capacitor, a ninth transistor, a tenth transistor and an eleventh transistor, wherein a first terminal of the second capacitor and a gate of the ninth transistor are both connected to the third node, a first pole of the ninth transistor is connected to a fourth clock signal terminal, and a second terminal of the second capacitor is connected to a second pole of the ninth transistor; a gate of the tenth transistor is connected to the fourth clock signal terminal, a first pole of the tenth transistor is connected to a second pole of the ninth transistor, and the second pole of the tenth transistor is connected to the first node; and the grid electrode of the eleventh transistor is connected with the fourth node, the first pole of the eleventh transistor is connected with the first node, and the second pole of the eleventh transistor is connected with the first level signal end.

8. The control circuit of claim 1, wherein the first output unit comprises a twelfth transistor, a thirteenth transistor, a third capacitor and a fourth capacitor, wherein a first terminal of the third capacitor and a gate of the twelfth transistor are both connected to the first node, a second terminal of the third capacitor and a first pole of the twelfth transistor are both connected to a first level signal terminal, and a second pole of the twelfth transistor is connected to the first output terminal; the gate of the thirteenth transistor and the first end of the fourth capacitor are both connected to the fourth node, the second end of the fourth capacitor is connected to the fourth clock signal end, the first pole of the thirteenth transistor is connected to the second level signal end, and the second pole of the thirteenth transistor is connected to the first output end.

9. The control circuit according to claim 6, wherein the third control unit comprises a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, wherein a gate of the fourteenth transistor is connected to the third clock signal terminal, a first pole is connected to the second level signal terminal, and a second pole is connected to the first pole of the fifteenth transistor and to the fifth node; a gate of the fifteenth transistor is connected to a first pole of the sixteenth transistor, the first pole is connected to the fifth node, and a second pole is connected to the third clock signal terminal; a gate of the sixteenth transistor is connected to the third clock signal terminal, a first pole of the sixteenth transistor is connected to the seventh node, and a second pole of the sixteenth transistor is connected to the second clock signal terminal; a gate of the seventeenth transistor is connected to a second pole of the fourteenth transistor, a first pole of the seventeenth transistor is connected to the first level signal terminal, and a second pole of the seventeenth transistor is connected to the first pole of the eighteenth transistor; and the grid electrode of the eighteenth transistor is connected with a fourth clock signal end, and the second pole of the eighteenth transistor is connected with the seventh node.

10. The control circuit of claim 9, wherein the fourth control unit comprises a fifth capacitor, a nineteenth transistor, a twentieth transistor and a twenty-first transistor, wherein a first terminal of the fifth capacitor and a gate of the nineteenth transistor are both connected to the fifth node, a first pole of the nineteenth transistor is connected to the fourth clock signal terminal, and a second terminal of the fifth capacitor is connected to a second pole of the nineteenth transistor; a gate of the twentieth transistor is connected to the fourth clock signal terminal, a first pole of the twentieth transistor is connected to the second pole of the nineteenth transistor, and a second pole of the twentieth transistor is connected to the first pole of the twenty-first transistor and to the sixth node; and the grid electrode of the twenty-first transistor is connected with the second pole of the sixth transistor, and the second pole of the twenty-first transistor is connected with the first level signal end.

11. The control circuit according to claim 10, wherein the second output unit comprises a twenty-second transistor, a twenty-third transistor, a sixth capacitor and a seventh capacitor, wherein a first end of the sixth capacitor and a gate of the twenty-second transistor are both connected to the sixth node, a second end of the sixth capacitor is connected to a first clock signal terminal, a first pole of the twenty-second transistor is connected to the second node, and a second pole of the twenty-second transistor is connected to the second output terminal; the grid electrode of the twenty-third transistor and the first end of the seventh capacitor are both connected with the first pole of the sixteenth transistor, the second end of the seventh capacitor is connected with the fourth clock signal end, the first pole of the twenty-third transistor is connected with the second level signal end, and the second pole of the twenty-third transistor is connected with the second output end.

12. The control circuit according to claim 1, wherein the control circuit comprises a plurality of cascaded sub-circuits, the sub-circuits respectively comprise the first circuit, the selection circuit and the second circuit, the first output terminal of the sub-circuit of the nth stage is connected with a start trigger signal terminal of the sub-circuit of the (n + 1) th stage, and n ≧ 1; and each second output end is used for being connected with a pixel driving circuit.

13. A driving method of a control circuit, applied to the control circuit of any one of claims 1 to 12, the driving method comprising:

controlling a signal of the first node in the first circuit to enable the first selection branch to be conducted, and transmitting a first level signal to the second node; or, the second selection branch is turned on, and the first clock signal is transmitted to the second node;

14. The driving method according to claim 13, wherein when the second clock signal is the first state level signal, the second level signal output from the second output terminal is the same as the second node signal; the second circuit comprises a twenty-third transistor, a first pole of the twenty-third transistor is connected with a second level signal end, a second pole of the twenty-third transistor is connected with the second output end, and when the second clock signal is a second state level signal, a second level signal output by the second output end is the same as a level signal of the second level signal end.

15. A display device comprising the control circuit of any one of claims 1-12.