CN114252775B - Current detection chip, battery and electronic equipment - Google Patents
Current detection chip, battery and electronic equipment Download PDFInfo
- Publication number
- CN114252775B CN114252775B CN202110213271.5A CN202110213271A CN114252775B CN 114252775 B CN114252775 B CN 114252775B CN 202110213271 A CN202110213271 A CN 202110213271A CN 114252775 B CN114252775 B CN 114252775B
- Authority
- CN
- China
- Prior art keywords
- current
- output
- input
- compensation
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 54
- 238000007599 discharging Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 17
- 238000010586 diagram Methods 0.000 description 16
- 230000008859 change Effects 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 4
- 230000001960 triggered effect Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910001416 lithium ion Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/382—Arrangements for monitoring battery or accumulator variables, e.g. SoC
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
- G01R19/16542—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies for batteries
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Secondary Cells (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The embodiment of the application provides a current detection chip, a battery and electronic equipment, wherein the current detection chip is used for detecting current of the battery in the charging and discharging processes, and comprises the following components: a current compensation circuit for generating a first compensation current that varies with a variation in a power supply voltage from the battery; the comparison circuit comprises a first input end and a second input end; the selection circuit is used for receiving the first compensation current and selecting the first compensation current to be input to the first input end of the comparison circuit or the second input end of the comparison circuit; the comparison circuit is used for outputting an indication signal according to the comparison result of the current of the second input end of the current of the first input end of the comparison circuit, and the indication signal is used for indicating whether the charging and discharging process of the battery is over-current or not. The application provides a current detection chip, a battery and electronic equipment for improving the current detection accuracy of the battery in the charging and discharging processes.
Description
Technical Field
The application relates to the technical field of quick charge, in particular to a current detection chip, a battery and electronic equipment.
Background
With the advent of the intelligent age, the continuous promotion of software and hardware has greatly increased the power consumption of electronic devices such as mobile phones, and thus, fast charging technology has been developed. In the battery fast charging technology, the voltage of the battery is changed rapidly, so that the on-resistance of a transistor in a battery protection circuit is changed, and the current detection of the battery in the charging and discharging processes is caused, and the use of a user is influenced.
Disclosure of Invention
The application provides a current detection chip, a battery and electronic equipment for improving the current detection accuracy of the battery in the charging and discharging processes.
In a first aspect, an embodiment of the present application provides a current detection chip for detecting a current of a battery in a charging and discharging process, including:
a current compensation circuit for generating a first compensation current that varies linearly with a variation in a power supply voltage from the battery;
the comparison circuit comprises a first input end and a second input end;
a selection circuit for receiving the first compensation current and selecting the first compensation current to be input to a first input terminal of the comparison circuit or a second input terminal of the comparison circuit;
the comparison circuit is used for comparing the current of the first input end of the comparison circuit with the current of the second input end of the comparison circuit and outputting an indication signal according to the comparison result, wherein the indication signal is used for indicating whether the charge and discharge process of the battery is over-current or not.
In a second aspect, an embodiment of the present application provides a battery, including a battery core and the current detection chip, where the current detection chip is electrically connected to the battery core, and the current detection chip is used for performing current detection in a charging and discharging process of the battery core.
In a third aspect, an embodiment of the present application provides an electronic device, including the battery.
By designing the current detection chip, the selection circuit receives the first compensation current and selects the first compensation current to be input to the first input end of the comparison circuit or the second input end of the comparison circuit, so that only one current compensation circuit is needed to generate the first compensation current, the first compensation current is selectively input to the first input end of the comparison circuit or the second input end of the comparison circuit through the selection circuit, and the problem that the current detection of the second input end is inaccurate due to the change of the on impedance of the MOS transistor in the charging and discharging loop is reduced under the condition of fewer current compensation circuits.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an application scenario of an electronic device according to an embodiment of the present application;
fig. 2 is a schematic structural view of a battery according to an embodiment of the present application;
fig. 3 is a schematic circuit diagram of a battery protection board according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a circuit for detecting a current in a first discharging mode according to an embodiment of the present application;
FIG. 5 is a circuit diagram of current detection in a discharge mode according to the prior art;
FIG. 6 is a schematic diagram of a circuit for detecting current in a charging mode according to an embodiment of the present application;
FIG. 7 is a circuit block diagram of a first current compensation circuit provided by an embodiment of the present application;
FIG. 8 is a schematic diagram of a first current compensation circuit according to an embodiment of the present application;
FIG. 9 is a schematic circuit diagram of current detection in a first discharge mode according to an embodiment of the present application;
FIG. 10 is a circuit block diagram of a second current compensation circuit provided by an embodiment of the present application;
FIG. 11 is a schematic diagram of a partial structure of a second current compensation circuit according to an embodiment of the present application;
FIG. 12 is a schematic diagram of a third current compensation circuit according to an embodiment of the present application;
FIG. 13 is a schematic diagram of a fourth current compensation circuit according to an embodiment of the present application;
FIG. 14 is a schematic diagram showing a partial structure of a fifth current compensation circuit according to an embodiment of the present application;
FIG. 15 is a circuit block diagram of a second current compensation circuit provided by an embodiment of the present application;
fig. 16 is a schematic diagram of a local structure of a sixth current compensation circuit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The illustrated embodiments of the application can be suitably combined with each other without mutual violations.
With the development of technology, electronic devices (such as smart phones, wearable devices, tablet computers, etc.) have become more and more powerful, and users can perform office work and entertainment through the electronic devices, so that the electronic devices have become an integral part of people's daily lives. However, the endurance of the electronic device is limited, requiring the user to constantly charge the electronic device. In order to ensure that a user can normally use an electronic device, quick charging is a mainstream scheme of charging.
The current common quick-charging technology can be mainly divided into two main categories: low-voltage high-current quick charge technology and high-voltage low-current quick charge technology. Whether low-voltage high-current quick charge or high-voltage low-current quick charge is carried out, the high-voltage high-current quick charge is converted into larger charging current (the charging current cannot exceed the maximum safe charging current carried by the battery or the safe charging current which does not damage the service life of the battery) when the high-voltage high-current quick charge is input to the battery in a charging circuit of the electronic equipment, and therefore, the charging safety of the quick charge is particularly important when the battery is charged with the high-current.
Referring to fig. 1, fig. 1 is an application scenario suitable for an embodiment of the present application. In the scenario shown in fig. 1, an electronic device 100, a charging cord 200, and a charger 300 are included. Electronic device 100 includes, but is not limited to, a mobile phone, a notebook computer, a palm top computer, a rechargeable headset, a rechargeable speaker, a rechargeable wearable device, a robot, a rechargeable household appliance, a rechargeable vehicle, a rechargeable transport, and the like. The charger 300 is electrically connected to the electronic device 100 through the charging wire 200. The electronic device 100 includes at least a battery 10, a connection interface 20, a charge management chip 30, a load 40, and the like. The connection interface 20 is electrically connected to the charge management chip 30. The battery 10 is electrically connected to the charge management chip 30 and the load 40, respectively. Wherein the battery 10 includes a battery protection plate 101 and a battery cell 102. The load 40 may be a power consumption device in the electronic device 100, and for example, the load 40 may be various power consumption devices such as a microphone, a camera, a display screen, a motor, and the like. The charge management chip 30 is a chip that manages the charging of the battery 10. During charging, the current flows to: charger 300 → charging wire 200 → connection interface 20 → charge management chip 30 → battery protection plate 101 → battery cell 102. During discharge, the current flows to: cell 102→battery protection plate 101→load 40.
In the charge and discharge process of the battery 10, particularly in the field of fast charge technology, current detection of the battery 10 is an important point of study. The current during the charge and discharge of the battery 10 is generally detected by designing a current detection chip. Battery 10 includes, but is not limited to, lithium ion batteries, metal lithium batteries, and the like.
Referring to fig. 2, the current detection chip 1 may be disposed on a battery protection board 101 of the battery 10, may be disposed in the electronic device 100 and located outside the battery 10 (e.g., on a motherboard of the electronic device 100), or may be disposed in the charger 300. The embodiment of the present application will be described by taking the example in which the current detection chip 1 is provided on the battery protection board 101. The current detection chip 1 is used for monitoring current information of the battery 10, and when the current reaches a protection threshold value, the corresponding charge-discharge transistor is turned off, so that the purpose of protecting the battery 10 is achieved.
In the related art, under different power supply voltages, a charge-discharge MOS (Metal-Oxide-Semiconductor) transistor may change according to the power supply voltage, resulting in inaccurate current values detected by the battery protection board 101 and inaccurate over-current protection of the battery by the battery protection board 101. The power supply voltage is the voltage of the port electrically connected with the positive terminal of the battery cell.
The application provides a current detection chip for improving the current detection accuracy of a battery 10 in the charge and discharge processes. The application scenario in the present application includes the battery cell 102, the battery protection plate 101, a discharge load (not shown) or an external charging device (not shown). The battery protection plate 101 is provided with a current detection chip 1. Of course, the battery protection plate 101 is further provided with a chip for functions such as voltage detection. The chips may be packaged independently into a plurality of chips, and pins of the chips are connected to each other, or the chips may be packaged together into a whole, in other words, the current detection chip 1 according to the present application may be a single chip package or a part of a chip package. For convenience of description, referring to fig. 3, the battery protection plate 101 is further provided with a first battery terminal interface bat+, a second battery terminal interface BAT-, a first external interface eb+ and a second external interface EB-. The first battery terminal interface BAT+ is electrically connected with the positive terminal of the battery cell 102, the second battery terminal interface BAT-is electrically connected with the negative terminal of the battery cell 102, the first external interface EB+ is electrically connected with the positive terminal of a discharging load or the positive terminal of external charging equipment, and the second external interface EB-is electrically connected with the negative terminal of the load or the negative terminal of the external charging equipment.
Referring to fig. 4, the current detecting chip 1 at least includes a comparing circuit 2, a current compensating circuit 3 and a selecting circuit 4.
Referring to fig. 4, the comparing circuit 2 includes a first input terminal 21 and a second input terminal 22. The first input 21 of the comparison circuit 2 may be a positive input and the second input 22 of the comparison circuit 2 may be a negative input; alternatively, the first input 21 of the comparison circuit 2 may be a negative input and the second input 22 of the comparison circuit 2 may be a positive input. In the present application, the first input terminal 21 of the comparison circuit 2 may be a positive input terminal, and the second input terminal 22 of the comparison circuit 2 may be a negative input terminal.
Referring to fig. 3 and 4, in the discharging mode, current flows through the positive terminal of the battery cell 102, the first battery terminal interface bat+, the first external interface eb+, the load positive terminal, the load negative terminal, the second external interface EB-, the second input terminal 22 of the comparison circuit 2, the first input terminal 21 of the comparison circuit 2, the second battery terminal interface BAT-, and the negative terminal of the battery cell 102 in order. In the charging mode, current flows through the external charging device anode, the first external interface eb+, the first battery terminal interface bat+, the positive terminal of the battery cell 102, the negative terminal of the battery cell 102, the first input terminal 21 of the comparison circuit 2, the second input terminal 22 of the comparison circuit 2, and the second battery terminal interface BAT-in this order.
The comparison circuit 2 is a current-mode comparison circuit. The comparison circuit 2 is configured to compare a current of the first input terminal 21 of the comparison circuit 2 with a current of the second input terminal 22 of the comparison circuit 2 during charging and discharging of the battery 10, and output an indication signal according to a comparison result, wherein the indication signal is configured to indicate whether the charging and discharging process of the battery 10 is over-current.
Specifically, the comparing circuit 2 may compare the current signal received by the first input terminal 21 with the current signal received by the second input terminal 22, and output an indication signal when the current signal value of the first input terminal 21 is greater than the current signal of the second input terminal 22. The indication signal may be high or low. When the indication signal is a high level signal, the indication signal is used for controlling the charge transistor of the charge-discharge loop of the battery 10 to be turned off and the discharge transistor to be turned on, so that the battery 10 ends the charge mode and is converted into the dischargeable mode, and the battery 10 is subjected to charge overcurrent protection; when the indication signal is a low level signal, the indication signal is used for controlling the discharge transistor of the charge-discharge loop of the battery 10 to be turned off and the charge transistor to be turned on, so that the battery 10 ends the discharge mode and is converted into the chargeable mode, and the battery 10 is subjected to discharge overcurrent protection.
It is understood that both the charge loop and the discharge loop have MOS transistors therein. The on-resistance of the MOS transistor is related to the voltage driving the gate. When the power supply voltage Vdd (Vdd is the voltage of the Vdd terminal in fig. 3) decreases, the driving voltage of the MOS transistor becomes small, resulting in an increase in the on-resistance of the MOS transistor, and when the power supply voltage Vdd increases, the voltage of the driving MOS transistor becomes large, resulting in a decrease in the on-resistance of the MOS transistor, which may cause inaccurate current detection in the comparison circuit 2 and cause a false triggering of the over-current protection.
Based on the above-mentioned problems, the current detection chip 1 provided by the present application includes a current compensation circuit 3 and a selection circuit 4. The current compensation circuit 3 is for generating a first compensation current. The first compensation current changes linearly along with the change of the power supply voltage Vdd to compensate the influence of the change of the on-resistance of the MOS transistor along with the change of the power supply voltage Vdd.
The selection circuit 4 is configured to receive the first compensation current and select the first compensation current to be input to the first input terminal 21 of the comparison circuit 2 or the second input terminal 22 of the comparison circuit 2. Specifically, in the discharging loop, the on-resistance variation of the MOS transistor causes inaccurate current detection at the first input terminal 21 of the comparison circuit 2, and the selection circuit 4 selects the first compensation current to compensate the first input terminal 21 of the comparison circuit 2, so as to reduce the problem that the on-resistance variation of the MOS transistor causes inaccurate current detection of the comparison circuit 2 and causes a false triggering over-current protection phenomenon. In the charging loop, the on-resistance variation of the MOS transistor causes inaccurate current detection of the second input terminal 22, and the selection circuit 4 selects the first compensation current to compensate the second input terminal 22, so as to reduce the problem that the on-resistance variation of the MOS transistor causes inaccurate current detection of the second input terminal 22 and causes a phenomenon of false triggering of over-current protection. In this way, only one current compensation circuit 3 is needed to generate the first compensation current, the first compensation current is selectively input to the first input terminal 21 of the comparison circuit 2 or the second input terminal 22 of the comparison circuit 2 through the selection circuit 4, and under the condition of less current compensation circuits 3, the problem that the current detection of the second input terminal 22 is inaccurate due to the on-resistance change of the MOS transistor in the charging and discharging loop, and the phenomenon of false triggering over-current protection is caused is reduced.
The application aims at the problem that the conduction resistance of the MOS transistor is increased due to the reduction of the power supply voltage Vdd; the power supply voltage Vdd increases, so that the on-resistance of the MOS transistor becomes smaller, and the on-resistance of the MOS transistor changes inversely with the change of the power supply voltage Vdd. In other words, the present application makes the trend of the first compensation current along with the dynamic change of the power supply voltage Vdd the same as or similar to the trend of the on-resistance of the MOS transistor along with the dynamic change of the power supply voltage Vdd, so as to improve the accuracy of compensation of the influence on the on-resistance of the MOS transistor. In the process of adjusting the magnitude of the first compensation current, the first compensation current has better linearity, and can be more easily adjusted to the current which counteracts all influences of the on-resistance of the MOS transistor.
In one possible embodiment, referring to fig. 3, the current detection chip 1 includes a power voltage terminal VDD, a first ground terminal GND, a charge management terminal DO, a discharge management terminal CO, and a second ground terminal VM.
The battery protection plate 101 is further provided with a first resistor R1, a first capacitor C1, a second resistor R2, a discharge MOS transistor Q1, a first parasitic diode D1, a charge MOS transistor Q2, and a second parasitic diode D2.
One end of the first resistor R1 is electrically connected to the positive terminal of the battery cell 102, and the other end of the first resistor R1 is electrically connected to the power voltage terminal VDD. The voltage of the power supply voltage terminal VDD is the power supply voltage VDD.
The first ground GND is electrically connected to the negative terminal of the battery 102. Two ends of the first capacitor C1 are respectively connected to the power voltage terminal VDD and the first ground terminal GND. The first resistor R1 and the first capacitor C1 play a filtering role. The first resistor R1 also has a voltage division protection function.
The source electrode of the discharging MOS transistor Q1 is connected with the negative electrode end of the battery cell 102, and the grid electrode of the discharging MOS transistor Q1 is a discharging protection control end and is connected with a discharging management end CO.
The drain electrode of the discharging MOS transistor Q1 is connected with the drain electrode of the charging MOS transistor Q2, the source electrode of the charging MOS transistor Q2 is connected with the second external interface EB-, and the grid electrode of the charging MOS transistor Q2 is a charging protection control end and is connected with the charging management end DO. The discharge MOS transistor Q1 may be turned on or off to turn on or off the discharge loop according to control of a signal of a control terminal thereof, and thus, the discharge MOS transistor Q1 may also be referred to as a discharge control switch; the charge MOS transistor Q2 may be turned on or off to turn on or off the charge loop according to control of a signal of a control terminal thereof, and thus the charge MOS transistor Q2 may also be referred to as a charge control switch.
The second ground terminal VM is a ground of the discharge load or a ground of the external charging device, and is connected to the load or the ground of the external charging device by the second resistor R2.
The first input end 21 of the comparison circuit 2 is electrically connected to the first ground end GND, the second input end 22 of the comparison circuit 2 is electrically connected to the second ground end VM, and the output end of the comparison circuit 2 is electrically connected to the charging management end DO and the discharging management end CO through logic circuits. The comparison circuit 2 outputs an indication signal by comparing the current difference between the first input terminal 21 and the second input terminal 22. For example, when the current value of the first input terminal 21 is greater than the current value of the second input terminal 22, the indication signal is at a high level. When the current value of the first input terminal 21 is less than or equal to the current value of the second input terminal 22, the indication signal is at a low level. The indication signal can control the discharging MOS transistor Q1 to be disconnected and the charging MOS transistor Q2 to be connected; or the discharging MOS transistor Q1 is controlled to be turned on and the charging MOS transistor Q2 is controlled to be turned off.
In the conventional art, in the discharging mode, the equivalent circuit diagram of the comparison circuit 2 is shown in fig. 5, wherein the resistor R provides the fixed offset voltage Vos of the comparator. R is a fixed resistor. When the discharge current is greater than k (VM-GND)/R, wherein k is a proportionality coefficient of the actual current and the detection current, GND is the voltage of the first grounding terminal GND, and VM is the voltage of the second grounding terminal VM. The output end OUT of the comparison circuit 2 outputs high level to trigger overcurrent protection; when the discharge current is smaller than k (VM-GND)/R, the output terminal OUT of the comparison circuit 2 is output at a low level, and overcurrent protection is not triggered.
Referring to fig. 4, when the on-resistance of the discharging MOS transistor Q1 and the charging MOS transistor Q2 in the discharging loop is equivalent to setting a variable resistor R0 between the first input terminal 21 and the first ground terminal GND of the comparing circuit 2, a variable voltage Δv (Vdd) related to the gate voltage exists between the first input terminal 21 and the first ground terminal GND of the comparing circuit 2, when the discharging current is greater than k { VM- [ gnd+Δv (Vdd) ]}/R0, the output terminal OUT of the comparing circuit 2 outputs a high level to trigger the over-current protection, and when the discharging current is less than k { VM- [ gnd+Δv (Vdd) ]}/R0, the output terminal OUT of the comparing circuit 2 outputs a low level to not trigger the over-current protection. Thus, the current threshold of the overcurrent protection is changed to cause a problem of inaccurate overcurrent protection. Referring to fig. 6, in the charging mode, the effect of the on-resistances of the discharging MOS transistor Q1 and the charging MOS transistor Q2 is equivalent to setting the variable resistor R0 between the second input terminal 22 and the second ground terminal VM of the comparison circuit 2, which is not described herein.
In the current detection chip 1 according to the embodiment of the present application, in the discharging mode, the selection circuit 4 conducts the output terminal of the current compensation circuit 3 with the first input terminal 21 of the comparison circuit 2. In the discharging process, the first compensation current generated by the current compensation circuit 3 can dynamically adjust the trigger threshold of the over-discharging current, so as to prevent the false triggering of the over-current protection. The lower the power supply voltage Vdd is, the larger the on-resistance of the charge-discharge MOS transistor is, the larger the current compensated for the variable resistor R0 is, so that the threshold value for triggering the overcurrent is higher, and the influence on the trigger threshold of the discharge current due to the increase of the on-resistance of the charge-discharge MOS transistor is counteracted; the higher the power supply voltage Vdd is, the smaller the on-resistance of the charge-discharge MOS transistor is, the smaller the current compensated for the variable resistor R0 is, and the threshold value triggering the overcurrent is lowered to offset the influence on the discharge current triggering threshold caused by the decrease of the on-resistance of the charge-discharge MOS transistor, so that the threshold value triggering the overcurrent protection is dynamically adjusted along with the power supply voltage Vdd, and the influence on the threshold value of the overcurrent protection caused by the change of the on-resistance of the charge-discharge MOS transistor is eliminated as much as possible.
In other words, when the power supply voltage Vdd is changed, the on-resistances of the discharging MOS transistor Q1 and the charging MOS transistor Q2 change, which is equivalent to the presence of a variable resistance R0 between the second ground terminal VM and the first ground terminal GND, resulting in a change of Δv (Vdd) related to the gate voltage between the second ground terminal VM and the first ground terminal GND. The higher the power supply voltage Vdd, the smaller the on-resistance of the charge-discharge MOS transistor becomes, and Δv (Vdd) becomes smaller. The power supply voltage Vdd decreases, the on-resistance of the charge-discharge MOS transistor increases, and Δv (Vdd) increases. When the first input 21 of the comparison circuit 2 is fed with the first compensation current, the higher the supply voltage Vdd is, the smaller the voltage Δv equivalent to the compensation at the second ground VM is; the lower the supply voltage Vdd, the greater the voltage Δv compensated at the second ground terminal VM; when the discharge current is greater than k { (VM+DeltaV) - [ GND + ]
V (Vdd) ] }/R0, the output end OUT of the comparison circuit 2 outputs high level, and overcurrent protection is triggered; when the discharge current is smaller than k { (VM+DeltaV) - [ GND+DeltaV (Vdd) ] } R0, the output terminal OUT of the comparison circuit 2 is output to a low level, and overcurrent protection is not triggered.
In a possible implementation, referring to fig. 7, the current compensation circuit 3 includes a first voltage generation module 31, a compensation load module 32, and a second voltage generation module 33.
The first voltage generating module 31 is configured to receive a first input voltage and output a first output voltage according to the first input voltage. The first input voltage is linearly related to the supply voltage Vdd. The first output voltage is linearly related to the first input voltage. The first output voltage is linearly related to the supply voltage Vdd. Further, the first input voltage is a times the power supply voltage Vdd. The value range of a is 0-1.
The second voltage generating module 33 is configured to receive a second input voltage and output a second output voltage according to the second input voltage. The second input voltage is a reference voltage Vref. The second output voltage is linearly related to the second input voltage. The reference voltage Vref is an internal bandgap reference (bandgap) generating reference voltage. In other words, the second output voltage is linearly related to the reference voltage Vref.
The second output voltage is applied to the input of the compensation load module 32. The first output voltage is applied to the output of the compensation load module 32 to generate a second compensation current I2. The first compensation current I1 is obtained according to the second compensation current I2. In other words, the first compensation current I1 may be generated according to the second compensation current I2.
The present embodiment is implemented to apply the first output voltage and the second output voltage to opposite ends of the compensating load module 32, so as to generate the second compensating current I2, where the first output voltage is linearly related to the power supply voltage Vdd, the second output voltage is linearly related to the reference voltage Vref, and the second compensating current I2 is further linearly related to the power supply voltage Vdd, so that the first compensating current I1 generated by the second compensating current I2 is also linearly related to the power supply voltage Vdd. The first compensation current I1 linearly dependent on the power supply voltage Vdd can be formed as above.
In one possible implementation, referring to fig. 8, the first voltage generating module 31 includes a first operational amplifier A1 and a first transistor P1. The first transistor P1 may be a PMOS transistor or an NMOS transistor. In this embodiment, the first transistor P1 is a PMOS transistor. The first input terminal a1+ of the first operational amplifier A1 is used for loading the first input voltage. The output end of the first operational amplifier A1 is electrically connected to the gate of the first transistor P1. The second input terminal A1 of the first operational amplifier A1 is connected with the source of the first transistor P1 and the output terminal of the compensation load module 32. The drain of the first transistor P1 is grounded.
In the ideal case of the first operational amplifier A1, the voltage at the second input terminal A1-of the first operational amplifier A1 is equal to the voltage at the first input terminal a1+ of the first operational amplifier A1, and the voltage at the first output terminal is equal to the voltage at the second input terminal 22. The voltage at the output of the compensation load module 32 is a times the supply voltage Vdd. The first operational amplifier A1 and the first transistor P1 are configured to output the input voltage of the first operational amplifier A1 completely in an ideal case, so that the voltage at the output terminal of the compensation load module 32 is a power supply voltage Vdd. In non-ideal cases, the voltage at the output of the compensating load module 32 is a voltage value linearly related to a times the supply voltage Vdd.
Referring to fig. 8, the second voltage generating module 33 includes a second operational amplifier A2 and a second transistor N1. The second transistor N1 may be a PMOS transistor or an NMOS transistor. In this embodiment, the second transistor N1 is an NMOS transistor. The first input terminal a2+ of the second operational amplifier A2 is used for loading the second input voltage. The output end of the second operational amplifier A2 is electrically connected to the gate of the second transistor N1. The second input terminal A2 of the second operational amplifier A2 is connected to the source of the second transistor N1 and the input terminal of the compensation load module 32.
In the ideal case of the second operational amplifier A2, the voltage at the second input terminal A2-of the second operational amplifier A2 is equal to the voltage at the first input terminal a2+ of the second operational amplifier A2, and the second output voltage is equal to the voltage at the second input terminal 22. The voltage at the input of the compensation load module 32 is the reference voltage Vref. The second operational amplifier A2 and the second transistor N1 are provided to output the input voltage of the second operational amplifier A2 completely in an ideal case, so that the voltage at the input terminal of the compensation load module 32 is the reference voltage Vref. In the non-ideal case, the voltage at the input of the compensation load module 32 is a voltage value linearly related to the reference voltage Vref.
By the above design, the reference voltage Vref is applied to the input terminal of the compensation load module 32, and the power voltage Vdd a times is applied to the output terminal of the compensation load module 32, so that the second compensation current I2 linearly related to the power voltage Vdd is generated.
Of course, in other embodiments, the input terminal of the compensation load module 32 may be loaded with a power voltage Vdd, and the output terminal of the compensation load module 32 may be loaded with the reference voltage Vref, so as to generate the second compensation current I2 linearly related to the power voltage Vdd.
Referring to fig. 7 and 8, the current compensation circuit 3 further includes a current mirror module 34. The current mirror module 34 includes a first output unit 341 and a second output unit 342 that are mirror-symmetrical and electrically connected. The power supply voltage Vdd is applied to both the input terminal of the first output unit 341 and the input terminal of the second output unit 342. The output terminal of the first output unit 341 outputs a second compensation current I2. The output end of the second output unit 342 is used for outputting the first compensation current I1. The first compensation current I1 is linearly related to the second compensation current I2.
Specifically, the first output unit 341 and the second output unit 342 are transistors, wherein the types of the first output unit 341 and the second output unit 342 may be PMOS transistors or NMOS transistors. In this embodiment, the first output unit 341 and the second output unit 342 are PMOS transistors.
Since the first output unit 341 and the second output unit 342 are arranged in a mirror symmetry manner, the current at the output end of the second output unit 342 is equal to the current at the output end of the first output unit 341, and thus, the first compensation current I1 is generated according to the second compensation current I2, and the magnitude of the first compensation current I1 is the same as the magnitude of the second compensation current I2.
Specifically, referring to fig. 8, the current compensation circuit 3 at least includes: the first transistor P1, the third transistor P2, the fourth transistor P3, the second transistor N1, the third resistor R3, the first operational amplifier A1, the second operational amplifier A2. The gate of the third transistor P2 is connected to the gate of the fourth transistor P3, and the source of the third transistor P2 and the source of the fourth transistor P3 are both connected to the power supply voltage Vdd. The drain electrode of the fourth transistor P3 is connected with the output of the first compensation current I1, the drain electrode of the third transistor P2 is connected with the drain electrode of the second transistor N1, the drain electrode of the second transistor N1 is connected with the drain electrode of the third transistor P2, the grid electrode of the second transistor N1 is connected with the output section of the second operational amplifier A2, the grid electrode of the second transistor N1 is connected with the second input end A2-of the second operational amplifier A2, the first input end A2+ of the second operational amplifier A2 is connected with the reference voltage Vref, the second input end A2-of the second operational amplifier A2 is connected with the source electrode of the second transistor N1, and the output end of the second operational amplifier A2 is connected with the grid electrode of the second transistor N1. One end of the third resistor R3 is connected with the source electrode of the second transistor N1, and the other end is connected with the source electrode of the first transistor P1. The source of the first transistor P1 is connected with the second input end A1-of the first operational amplifier A1, the drain of the first transistor P1 is grounded, and the grid of the first transistor P1 is connected with the output end of the first operational amplifier A1. The second input end A1-of the first operational amplifier A1 is connected with the source electrode of the first transistor P1, the second input end A1-of the first operational amplifier A1 is connected with a voltage dividing circuit of a power supply voltage Vdd, the input voltage of the voltage dividing circuit is Vbat, the magnitude of the Vbat is a, wherein a is a Vdd voltage dividing proportion, and the magnitude of the second compensation current I2 is I2= (Vref-a, vdd)/R3. After compensation, it can be obtained that when the discharge current is greater than k { (vm+i1×r0) - [ gnd+Δv (Vdd) ] } R0, the output terminal OUT of the comparison circuit 2 outputs a high level, triggering overcurrent protection; when the discharge current is smaller than k { (vm+i1×r0) - [ gnd+Δv (Vdd) ] } R0, the output terminal OUT of the comparison circuit 2 is output at low level, and overcurrent protection is not triggered. Wherein, I1R 0 can offset the influence voltage Δv (Vdd) caused by the on-resistance change of the charge-discharge MOS transistor, so that the accuracy of the overcurrent protection can be improved.
Referring to fig. 9, the selection circuit 4 includes a first control module 41, a first switch module 42, and a second switch module 43. The first switch module 42 is electrically connected to the first input terminal 21 of the comparison circuit 2 and the output terminal of the second output unit 342. The second switch module 43 is electrically connected to the second input terminal 22 of the comparison circuit 2 and the output terminal of the second output unit 342. The first control module 41 is configured to control the first switch module 42 to be turned on and the second switch module 43 to be turned off in a discharging mode, so that the first input end 21 of the comparison circuit 2 receives the first compensation current I1, and further perform current compensation in the discharging mode, so as to improve the accuracy of the over-current protection.
The first control module 41 is configured to control the second switch module 43 to be turned on and the first switch module 42 to be turned off in a charging mode, so that the second input end 22 of the comparison circuit 2 receives the first compensation current I1, and further perform current compensation in the charging mode, so as to improve accuracy of detecting the overcurrent protection current.
It should be noted that, when the first compensation current I1 is compensated, multiple detections may be performed, where the magnitudes of the detected first compensation currents I1 are different, in other words, the magnitudes of the first compensation currents I1 are continuously adjusted during multiple detections, and the preferred first compensation current I1 is determined according to the output value of the comparison circuit 2, so as to offset the influence caused by the on-resistance of the MOS transistor more, and improve the accuracy of current detection in the over-current protection.
In one possible embodiment, referring to fig. 10 and 11, the number of the second output units 342 is plural. Each of the second output units 342 is disposed in mirror symmetry with the first output unit 341. The plurality of second output units 342 are arranged in parallel. The current compensation circuit 3 further comprises an output selection module 35. One end of the output selecting module 35 is electrically connected to an output end of each of the second output units 342. The other end of the output selecting module 35 is electrically connected to the first switching module 42 and the second switching module 43. The first control module 41 is configured to control the output selection module 35 to select the first compensation current I1 received by one or more second output units 342.
Referring to fig. 11, the output selecting module 35 includes a plurality of first switch units 351, and one end of each first switch unit 351 is electrically connected to one second output unit 342. The other end of each first switching unit 351 is electrically connected to the first switching module 42 and the second switching module 43. The first switch units 351 may be transistors, and the first control module 41 is configured to control a gate level of each of the first switch units 351 to control an on-state amount of the first switch units 351. Referring to fig. 9 in combination, the first switching module 42 includes a second switching unit 421, and the second switching module 43 includes a third switching unit 431. One end of the second switching unit 421 is connected to the output terminal of the output selection module 35, one end of the third switching unit 431 is connected to the output terminal of the output selection module 35, the second switching unit 421 is electrically connected to the first input terminal 21 of the comparison circuit 2, and the third switching unit 431 is electrically connected to the second input terminal 22 of the comparison circuit 2.
In the discharging mode, the first control module 41 controls the second switch unit 421 to be turned on and the third switch unit 431 to be turned off, and controls the number of turned-on first switch units 351 to control the compensation current received by the first input terminal 21 of the comparison circuit 2. For example, the first control module 41 controls the first switch unit 351 to be turned on to control the compensation current received by the first input terminal 21 of the comparison circuit 2 to be the first compensation current I1 outputted by the output unit; the first control module 41 controls the 2 first switch units 351 to be turned on to control the first compensation current I1 received by the first input terminal 21 of the comparison circuit 2 to be 2 times the compensation current. In the charging mode, the first control module 41 controls the third switching unit 431 to be turned on and the second switching unit 421 to be turned off, and controls the number of turned-on first switching units 351 to control the compensation current received by the second input terminal 22 of the comparison circuit 2.
The number of branches of the first compensation current I1 outputted from the plurality of second output units 342 is selected by the control output selecting module 35 by providing the plurality of second output units 342 connected in parallel, so that the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 receives N times of the first compensation current I1, N being a positive integer, thereby increasing the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 based on the second compensation current I2.
In another possible embodiment, referring to fig. 12, the present embodiment is substantially the same as the above embodiment, except that the plurality of second output units 342 are disposed in series. One end of the output selecting module 35 is electrically connected to an output end of each of the second output units 342. The other end of the output selecting module 35 is electrically connected to the first switching module 42 and the second switching module 43. The first control module 41 is configured to control the output selection module 35 to select the first compensation current I1 received by one or more second output units 342.
In the discharging mode, the first control module 41 controls the second switch unit 421 to be turned on and the third switch unit 431 to be turned off, and controls the number of turned-on first switch units 351 to control the compensation current received by the first input terminal 21 of the comparison circuit 2. For example, the total number of the second output units 342 is 10, the 10 second output units 342 are sequentially connected in series, and the gates of the second output units 342 are electrically connected to the gates of the first output units 341. The first control module 41 controls the first switch unit 351 to be turned on to control the first compensation current I1 received by the first input terminal 21 of the comparison circuit 2 to be 1 times the compensation current; the first control module 41 controls the first 5 first switch units 351 to be turned on to control the first compensation current I1 received by the first input terminal 21 of the comparison circuit 2 to be 0.5 times of the compensation current; the first control module 41 controls the 10 first switch units 351 to be turned on to control the first compensation current I1 received by the first input terminal 21 of the comparison circuit 2 to be 0.1 times. The charging mode is similar to the discharging mode, and will not be described here.
By providing a plurality of second output units 342 connected in series and controlling the output selection module 35 to select the effective number of the plurality of second output units 342, the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 receives N times of the first compensation current I1, N ranges from 0 to 1, so that the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 is reduced based on the second compensation current I2.
In yet another possible embodiment, the main difference between the present embodiment and the above two embodiments is that one part of the plurality of second output units 342 is disposed in series, and the other part is disposed in parallel. The first switch module 42 is electrically connected to an output terminal of each of the second output units 342. The first control module 41 is configured to control the first switch module 42 to select one or more output terminals of the second output unit 342 to be conducted with the first input terminal 21 of the comparison circuit 2 or the second input terminal 22 of the comparison circuit 2.
By providing a plurality of second output units 342 connected in series and in parallel, and controlling the output selection module 35 to select an effective number of the plurality of second output units 342, the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 receives N times the first compensation current I1, N may be greater than 1 or less than 1, and N is not limited to be an integer, so that the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 is more flexibly compared based on the second compensation current I2. The adjustment range of the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 of the present embodiment is more flexible than the two embodiments described above, and the adjustable parameter range is relatively larger.
In one possible embodiment, referring to fig. 13, the number of the second output units 342 is plural. The plurality of second output units 342 includes a first sub-output unit 343 and a second sub-output unit 344. The output terminal of the first sub-output unit 343 is used for outputting a first sub-compensation current. The output terminal of the second sub-output unit 344 is used for outputting a second sub-compensation current. The first compensation current I1 is generated according to the first sub-compensation current or the second sub-compensation current. The first sub-output unit 343 is mirror symmetrical to the first output unit 341, and the first sub-output unit 343 is electrically connected to the gate of the first output unit 341, and the first sub-output unit 343 is electrically connected to the source of the first output unit 341. The second sub-output unit 344 is mirror symmetrical to the first output unit 341, and the second sub-output unit 344 is electrically connected to the gate of the first output unit 341, and the second sub-output unit 344 is electrically connected to the source of the first output unit 341. The first sub-output unit 343 and the second sub-output unit 344 can be transistors. The first sub-compensation current has the same magnitude as the second compensation current I2, and the second sub-compensation current has the same magnitude as the second compensation current I2.
Further, the selection circuit 4 comprises a first control module 41, a first switching module 42 and a second switching module 43. The first switch module 42 is electrically connected to the first input terminal 21 of the comparison circuit 2 and the output terminal of the first sub-output unit 343. The second switch module 43 is electrically connected to the second input terminal 22 of the comparison circuit 2 and the output terminal of the second sub-output unit 344. The first control module 41 is configured to control the first switch module 42 to be turned on and the second switch module 43 to be turned off in a discharging mode, so that the first sub-compensation current is input to the first input terminal 21 of the comparison circuit 2; alternatively, the first control module 41 is configured to control the second switching module 43 to be turned on and the first switching module 42 to be turned off in the charging mode, so that the second sub-compensation current is input to the second input terminal 22 of the comparison circuit 2.
The first input 21 of the comparison circuit 2 is also arranged to receive a first input current. The second input 22 of the comparison circuit 2 is also arranged to receive a second input current. The first input current is the current of the first grounding terminal, and the second input current is the current of the second grounding terminal.
Optionally, the first input current is a current flowing from the battery 10 terminal. The second input current is a current flowing into a load end. The load side is a device for discharging the battery 10. The first input current is used to synthesize the current at the first input 21 of the comparison circuit 2 with the first compensation current I1.
Still alternatively, the first input current is a current flowing into the battery 10 terminal. The second input current is a current flowing from the charging equipment end. The charging device side is an external charging device that charges the battery 10. The second input current is used to synthesize the current at the second input 22 of the comparison circuit 2 with the second compensation current I2.
In one possible implementation, referring to fig. 14, the compensation load module 32 includes a plurality of first load units 321, a first load selection module 322, and a second control module 323. The plurality of first load units 321 are arranged in parallel; alternatively, the plurality of first load units 321 are arranged in series; alternatively, one part of the plurality of first load units 321 is disposed in series, and the other part is disposed in parallel. The first load selection module 322 is electrically connected to the first input terminal 21 of the first voltage generation module 31 and the output terminals of all the first load units 321. The second control module 323 is configured to control the first load selection module 322 to select one or more of the first load units 321 to be turned on with the first voltage generation module 31.
The first load unit 321 may be a resistor. The first load selection module 322 may be a plurality of fourth switch units 324, and each fourth switch unit 324 is electrically connected to one first load unit 321 and the first input terminal 21 of the first voltage generation module 31. The second control module 323 controls the on/off of the fourth switch unit 324 to control the parallel number or the serial number of the first load units 321, so as to adjust the total resistance of the first load units 321, thereby adjusting the magnitude of the second compensation current I2, and further adjusting the compensation current received by the first input end 21 or the second input end 22 of the comparison circuit 2. The load resistance adjustment can be performed on the compensation load module 32 to realize the output of different second compensation currents I2, so that the complexity and occupied area of the current mirror module 34 can be reduced without increasing the number of the second output units 342.
In one possible implementation, referring to fig. 15, the current compensation circuit 3 further includes an input voltage adjustment circuit 36. The input voltage adjustment circuit 36 is configured to generate the first input voltage and adjust a magnitude of the first input voltage.
Referring to fig. 16, the input voltage adjusting circuit 36 includes a plurality of second load units 361, a second load selecting module 362, and a third control module 363. The plurality of second load units 361 are arranged in parallel; alternatively, the plurality of second load units 361 are arranged in series; alternatively, a part of the plurality of second load units 361 are serially connected, and another part thereof is parallelly connected; the second load selection module 362 electrically connects all the output terminals of the second load units 361 with the second input terminal 22 of the first voltage generation module 31. The third control module 363 is configured to control the second load selection module 362 to select one or more of the second load units 361 to be turned on with the first voltage generation module 31.
The second load unit 361 may be a resistor. The second load selection module 362 may be a plurality of fifth switch units 364, where each fifth switch unit 364 is electrically connected to one second load unit 361 and the second input terminal 22 of the first voltage generation module 31. The third control module 363 controls the number of parallel or series connection of the second load units 361 by controlling the on/off of the fifth switch unit 364, thereby adjusting the total resistance of the plurality of second load units 361, and thus adjusting the voltage Vbat of the voltage dividing circuit, that is, adjusting the value of a, and further adjusting the second compensation current I2, so as to adjust the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2.
In this embodiment, the voltage dividing circuit is designed, and the second control module 323 is provided to control the on/off of the fifth switch unit 364 in the second load selection module 362, so as to form different voltage dividing resistors, thereby adjusting the first input voltage of the first voltage generation module 31, and further adjusting the second compensation current I2. The present embodiment can perform voltage adjustment on the first input voltage to realize the output of different second compensation currents I2, without increasing the number of the second output units 342, and can reduce the complexity and occupied area of the current mirror module 34.
It will be appreciated that the above ways of adjusting the compensation current may be combined with each other to achieve a more flexible adjustment.
When the power supply voltage Vdd is too low, the current detection chip 1 provided by the application performs internal resistance compensation on the charge-discharge MOS transistor so as to prevent false triggering of the protection circuit. When the power supply voltage Vdd is too low, the internal resistance compensation is performed on the charge-discharge MOS transistor, so that the amplitude of the change of the charge-discharge MOS transistor along with the gate voltage becomes smaller, and the false triggering of the protection circuit is prevented.
The embodiment of the application also provides a battery 10, which comprises a battery core 102 and the current detection chip 1 in any of the above embodiments. The current detection chip 1 is electrically connected to the battery cell 102. The current detection chip 1 is used for detecting current in the charging and discharging process of the battery cell 102.
The embodiment of the application also provides the electronic equipment 100, and the electronic equipment 100 comprises the battery 10.
What has been described above is a part of the embodiments of the present application. It should be noted that. As would be apparent to one of ordinary skill in the art. Without departing from the principles of the application. Several improvements and modifications may also be made. Such modifications and variations are also considered to be within the purview of the application.
Claims (10)
1. A current detection chip for detecting current of a battery in a charge and discharge process, comprising:
A current compensation circuit for generating a first compensation current that varies linearly with a variation in a power supply voltage from the battery;
the comparison circuit comprises a first input end and a second input end;
a selection circuit for receiving the first compensation current and selecting the first compensation current to be input to a first input terminal of the comparison circuit or a second input terminal of the comparison circuit;
the comparison circuit is used for outputting an indication signal according to the comparison result of the currents of the first input end and the second input end of the comparison circuit, wherein the indication signal is used for indicating whether the charge and discharge process of the battery is over-current or not;
wherein,
the first input end of the comparison circuit is also used for receiving a first input current, and the second input end of the comparison circuit is also used for receiving a second input current;
the first input current is a current flowing from the battery, and the second input current is a current flowing into a load end, or the first input current is a current flowing into the battery, and the second input current is a current flowing from a charging equipment end.
2. The current sense die of claim 1, wherein the current compensation circuit comprises a first voltage generation module, a compensation load module, and a second voltage generation module, the first voltage generation module to receive a first input voltage and to output a first output voltage based on the first input voltage, the first output voltage being linearly related to the supply voltage; the second voltage generating module is configured to receive a second input voltage and output a second output voltage according to the second input voltage, where the second output voltage is loaded at an input end of the compensating load module, and the first output voltage is loaded at an output end of the compensating load module to generate a second compensating current, where the first compensating current is obtained according to the second compensating current.
3. The current detection chip of claim 2, wherein the first voltage generation module comprises a first operational amplifier and a first transistor, a first input terminal of the first operational amplifier is used for loading the first input voltage, an output terminal of the first operational amplifier is electrically connected with a gate of the first transistor, a second input terminal of the first operational amplifier is connected with a source of the first transistor and an output terminal of the compensation load module, and a drain of the first transistor is grounded;
and/or the number of the groups of groups,
the second voltage generation module comprises a second operational amplifier and a second transistor, wherein a first input end of the second operational amplifier is used for loading the second input voltage, an output end of the second operational amplifier is electrically connected with a grid electrode of the second transistor, and a second input end of the second operational amplifier is connected with a source electrode of the second transistor and an input end of the compensation load module;
and/or the first input voltage is a times of the power supply voltage, the value range of a is 0-1, and the second input voltage is a reference voltage;
and/or the current compensation circuit further comprises a current mirror module, wherein the current mirror module comprises a first output unit and a second output unit which are in mirror symmetry and are electrically connected, the input end of the first output unit and the input end of the second output unit are both loaded with the power supply voltage, the output end of the first output unit outputs a second compensation current, the output end of the second output unit is used for outputting the first compensation current, and the first compensation current is in linear correlation with the second compensation current.
4. The current sense die of claim 3, wherein the selection circuit includes a first control module, a first switch module, and a second switch module, the first switch module electrically connecting a first input of the comparison circuit with an output of the second output unit, the second switch module electrically connecting a second input of the comparison circuit with an output of the second output unit, the first control module for controlling the first switch module to turn on and the second switch module to turn off so that the first input of the comparison circuit receives the first compensation current; or, the second switch module is controlled to be turned on and the first switch module is controlled to be turned off, so that the second input end of the comparison circuit receives the first compensation current.
5. The current detection chip of claim 4, wherein the number of the second output units is plural, and the plural second output units are arranged in parallel; alternatively, a plurality of the second output units are arranged in series; or, one part of the plurality of second output units is arranged in series, and the other part of the plurality of second output units is arranged in parallel; the current compensation circuit further comprises an output selection module, one end of the output selection module is electrically connected with the output end of each second output unit, the other end of the output selection module is electrically connected with the first switch module and the second switch module, and the first control module is used for controlling the output selection module to selectively receive the first compensation current of one or more second output units.
6. The current detection chip of claim 3, wherein the number of the second output units is plural, and the plural second output units include a first sub-output unit and a second sub-output unit, the output terminal of the first sub-output unit is configured to output a first sub-compensation current, the output terminal of the second sub-output unit is configured to output a second sub-compensation current, and the first compensation current is generated according to the first sub-compensation current or the second sub-compensation current.
7. The current sense die of claim 6, wherein the selection circuit includes a first control module, a first switch module, and a second switch module, the first switch module electrically connecting a first input of the comparison circuit with an output of the first sub-output unit, the second switch module electrically connecting a second input of the comparison circuit with an output of the second sub-output unit, the first control module being configured to control the first switch module to be turned on and the second switch module to be turned off so that the first sub-compensation current is input to the first input of the comparison circuit; or controlling the second switch module to be turned on and the first switch module to be turned off so that the second sub-compensation current is input to the second input end of the comparison circuit.
8. The current detection chip according to any one of claims 2 to 7, wherein the load terminal is a battery discharge device, and the first input current is used to synthesize a current of the first input terminal of the comparison circuit with the first compensation current; or the charging equipment terminal is equipment for charging the battery, and the second input current is used for combining the current of the second input terminal of the comparison circuit with the second compensation current.
9. A battery, comprising a battery core and the current detection chip according to any one of claims 1 to 8, wherein the current detection chip is electrically connected to the battery core, and the current detection chip is used for detecting current in the charging and discharging process of the battery core.
10. An electronic device comprising the battery of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110213271.5A CN114252775B (en) | 2020-09-23 | 2020-09-23 | Current detection chip, battery and electronic equipment |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110213271.5A CN114252775B (en) | 2020-09-23 | 2020-09-23 | Current detection chip, battery and electronic equipment |
| CN202011009871.1A CN111929594B (en) | 2020-09-23 | 2020-09-23 | Current detection chip, battery and electronic equipment |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011009871.1A Division CN111929594B (en) | 2020-09-23 | 2020-09-23 | Current detection chip, battery and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114252775A CN114252775A (en) | 2022-03-29 |
| CN114252775B true CN114252775B (en) | 2023-12-05 |
Family
ID=73335012
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011009871.1A Active CN111929594B (en) | 2020-09-23 | 2020-09-23 | Current detection chip, battery and electronic equipment |
| CN202110213271.5A Active CN114252775B (en) | 2020-09-23 | 2020-09-23 | Current detection chip, battery and electronic equipment |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011009871.1A Active CN111929594B (en) | 2020-09-23 | 2020-09-23 | Current detection chip, battery and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN111929594B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113687682A (en) * | 2021-08-23 | 2021-11-23 | 珠海极海半导体有限公司 | Power supply signal compensation circuit and consumable chip |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5557192A (en) * | 1993-09-21 | 1996-09-17 | Sanyo Electric Co., Ltd. | Charging apparatus with a compensation circuit |
| EP1047174A1 (en) * | 1999-04-21 | 2000-10-25 | EM Microelectronic-Marin SA | Battery protection circuit |
| KR20060013899A (en) * | 2004-08-09 | 2006-02-14 | 엘지이노텍 주식회사 | Over current protection module |
| KR101549545B1 (en) * | 2014-05-26 | 2015-09-04 | 충북대학교 산학협력단 | Battery Protection Integrated Circuit with Temperature Compensation of Over Current |
| CN105846493A (en) * | 2016-04-19 | 2016-08-10 | 无锡中感微电子股份有限公司 | Overcurrent detection circuit, overcurrent protection circuit and battery |
| CN205544488U (en) * | 2016-04-19 | 2016-08-31 | 无锡中感微电子股份有限公司 | Detection, protection circuit and battery overflow |
| CN106054086A (en) * | 2016-07-11 | 2016-10-26 | 深圳天珑无线科技有限公司 | Battery self-discharge detection method and apparatus |
| CN106230051A (en) * | 2016-08-15 | 2016-12-14 | 珠海市魅族科技有限公司 | A kind of charging circuit, system, method and electronic installation |
| CN107196374A (en) * | 2017-07-04 | 2017-09-22 | 南京矽力杰半导体技术有限公司 | Battery electric quantity indicating circuit and method and battery management integrated circuit |
| CN109154638A (en) * | 2016-06-23 | 2019-01-04 | 英特尔公司 | System, method and apparatus for battery charging state detection |
| CN211508661U (en) * | 2020-01-10 | 2020-09-15 | 上海众链科技有限公司 | Portable power supply equipment |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102455381A (en) * | 2010-10-29 | 2012-05-16 | 登丰微电子股份有限公司 | Current detecting circuit and current overcurrent protection controller |
| CN203225506U (en) * | 2013-04-02 | 2013-10-02 | 重庆徐港电子有限公司 | A program controlled over-current protection circuit with a settable threshold |
| CN104485635A (en) * | 2014-12-30 | 2015-04-01 | 青岛歌尔声学科技有限公司 | Overcurrent protection circuit and overcurrent protection device |
| CN104821555B (en) * | 2015-05-11 | 2017-12-08 | 无锡中感微电子股份有限公司 | The battery protecting circuit of precision current sampling can be carried out |
| CN107425507B (en) * | 2016-05-23 | 2019-03-29 | 宁德时代新能源科技股份有限公司 | Battery overcurrent protection circuit and battery overcurrent protection method |
| CN107248769B (en) * | 2017-07-31 | 2019-04-12 | 维沃移动通信有限公司 | Wireless charging circuit, wireless charging method, wireless charging system and mobile terminal |
| CN107579508B (en) * | 2017-09-23 | 2019-06-11 | 华为技术有限公司 | A kind of apparatus for protecting power supply and the terminal using described device |
| CN207234470U (en) * | 2017-09-29 | 2018-04-13 | 欣旺达电子股份有限公司 | Fast charge protects circuit and electronic equipment |
| CN207426737U (en) * | 2017-09-29 | 2018-05-29 | 欣旺达电子股份有限公司 | Lithium battery low-resistance protects circuit |
| CN207884279U (en) * | 2018-01-24 | 2018-09-18 | 广州市方瞳科技有限责任公司 | A kind of battery protecting plate |
-
2020
- 2020-09-23 CN CN202011009871.1A patent/CN111929594B/en active Active
- 2020-09-23 CN CN202110213271.5A patent/CN114252775B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5557192A (en) * | 1993-09-21 | 1996-09-17 | Sanyo Electric Co., Ltd. | Charging apparatus with a compensation circuit |
| EP1047174A1 (en) * | 1999-04-21 | 2000-10-25 | EM Microelectronic-Marin SA | Battery protection circuit |
| KR20060013899A (en) * | 2004-08-09 | 2006-02-14 | 엘지이노텍 주식회사 | Over current protection module |
| KR101549545B1 (en) * | 2014-05-26 | 2015-09-04 | 충북대학교 산학협력단 | Battery Protection Integrated Circuit with Temperature Compensation of Over Current |
| CN105846493A (en) * | 2016-04-19 | 2016-08-10 | 无锡中感微电子股份有限公司 | Overcurrent detection circuit, overcurrent protection circuit and battery |
| CN205544488U (en) * | 2016-04-19 | 2016-08-31 | 无锡中感微电子股份有限公司 | Detection, protection circuit and battery overflow |
| CN109154638A (en) * | 2016-06-23 | 2019-01-04 | 英特尔公司 | System, method and apparatus for battery charging state detection |
| CN106054086A (en) * | 2016-07-11 | 2016-10-26 | 深圳天珑无线科技有限公司 | Battery self-discharge detection method and apparatus |
| CN106230051A (en) * | 2016-08-15 | 2016-12-14 | 珠海市魅族科技有限公司 | A kind of charging circuit, system, method and electronic installation |
| CN107196374A (en) * | 2017-07-04 | 2017-09-22 | 南京矽力杰半导体技术有限公司 | Battery electric quantity indicating circuit and method and battery management integrated circuit |
| CN211508661U (en) * | 2020-01-10 | 2020-09-15 | 上海众链科技有限公司 | Portable power supply equipment |
Non-Patent Citations (1)
| Title |
|---|
| 锂电池管理芯片的过流保护功能设计及实现;朱卓娅;程剑平;魏同立;;电路与***学报(01);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114252775A (en) | 2022-03-29 |
| CN111929594A (en) | 2020-11-13 |
| CN111929594B (en) | 2020-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10790679B2 (en) | Battery protection circuit and device, battery pack, and battery protection method | |
| US7847519B2 (en) | Smart battery protector with impedance compensation | |
| US10594146B2 (en) | Battery control circuit for multiple cells employing level shift circuits to avoid fault | |
| US8058845B2 (en) | Battery state monitoring circuit and battery apparatus | |
| US10749358B2 (en) | Rechargeable battery protection integrated circuit, rechargeable battery protection device, and battery pack | |
| US7567116B2 (en) | Voltage converting circuit and battery device | |
| CN102738775B (en) | Battery protecting circuit and battery protecting apparatus and battery pack | |
| US10090690B2 (en) | Secondary battery protection circuit | |
| US8471526B2 (en) | Protection device for secondary batteries, and battery pack and electronic equipment employing same | |
| CN101356706A (en) | Back-gate voltage generator circuit, four-terminal back gate switching FET, and charge and discharge protection circuit using same | |
| US11183858B2 (en) | Rechargeable battery protection circuit, rechargeable battery protection device, battery pack, and method of controlling rechargeable battery protection circuit | |
| US20230090857A1 (en) | Power protection apparatus and terminal using the apparatus | |
| CN109256827A (en) | Secondary battery protection circuit, rechargeable battery protection integrated circuit and battery pack | |
| CN112583079A (en) | Battery protection circuit and device | |
| CN114252775B (en) | Current detection chip, battery and electronic equipment | |
| KR20110043473A (en) | Battery state monitoring circuit and battery device | |
| JP2925241B2 (en) | Rechargeable battery device | |
| US6225779B1 (en) | Power supply monitoring integrated circuit device for individually monitoring voltages of cells | |
| CN105529690B (en) | Battery protecting circuit, battery protecting apparatus, battery pack and battery protecting method | |
| CN103647259A (en) | Battery protection circuit and voltage protection circuit therein | |
| US11688896B2 (en) | Cell count determination device, charger, battery pack, and charging system | |
| US8867246B2 (en) | Communication device and battery pack in which the communication device is provided | |
| US20220368141A1 (en) | Secondary battery protection circuit, battery pack, battery system, and method for protecting secondary battery | |
| JP6912744B1 (en) | Control system, control method and secondary battery protection integrated circuit | |
| US11159028B2 (en) | Battery control circuit, battery control device, and battery pack |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |