CN114245046A - Circulating ADC (analog-to-digital converter) for CMOS (complementary metal oxide semiconductor) image sensor and circulating method thereof - Google Patents
Circulating ADC (analog-to-digital converter) for CMOS (complementary metal oxide semiconductor) image sensor and circulating method thereof Download PDFInfo
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Abstract
The embodiment of the application discloses a circulating ADC for a CMOS image sensor and a circulating method thereof, wherein the ADC comprises: the circuit comprises a transconductance amplifier, a chopper, a plurality of capacitors with the same capacitance value and a plurality of control switches; the switching states of the chopper and the control switch enable the ADC to have a first working mode, a second working mode, a third working mode and a fourth working mode which are sequentially executed in a circulating mode; capacitors in the first group of capacitors are respectively connected in series to the input end and the output end in a first working mode and a second working mode, the polarities of the capacitors in the two working modes are opposite, and different capacitors in the second group of capacitors in the two working modes are respectively used for voltage sampling; in the first working mode, the positions of the first group of capacitors and the second group of capacitors are exchanged to obtain a third working mode; and in the second working mode, the first group of capacitors and the second group of capacitors are exchanged in position to obtain a fourth working mode. The scheme of the embodiment solves the problems of capacitance mismatch and offset voltage of the transconductance amplifier.
Description
Technical Field
The present invention relates to ADC design technologies, and in particular, to a cyclic ADC for a CMOS image sensor and a cyclic method thereof.
Background
CMOS (Complementary Metal Oxide Semiconductor) image sensors usually adopt a structure of reading out in parallel by columns, the voltage values of the pixels are read out by columns, and each column shares one ADC (analog-to-digital converter). The CYCLIC (CYCLIC) ADC has the characteristics of low input capacitance, small area, simple structure, etc., so that it is very suitable for CMOS image sensors. However, the capacitance mismatch of current cyclic ADCs and the offset voltage of the amplifier again limit the conversion accuracy of CYCLIC ADC.
Disclosure of Invention
The embodiment of the application provides a circulating ADC for a CMOS image sensor and a circulating method thereof, which can solve the problems of capacitor mismatch and offset voltage of a transconductance amplifier.
The embodiment of the present application provides a cyclic ADC for a CMOS image sensor, which may include: the circuit comprises a transconductance amplifier, a chopper, a plurality of capacitors with the same capacitance value and a plurality of control switches;
the chopper is arranged to control the connection mode of the input end and the output end of the transconductance amplifier and the capacitor; the input terminal includes: a forward input and a reverse input, the output comprising: a forward output terminal and a reverse output terminal;
the control switch is set to control the access modes of the transconductance amplifier and the capacitor in each working mode;
wherein the switching states of said chopper and said plurality of control switches cause the cyclic analog-to-digital converter ADC to have a plurality of said operating modes; the plurality of operating modes include: a first working mode, a second working mode, a third working mode and a fourth working mode; the first working mode, the second working mode, the third working mode and the fourth working mode are sequentially and circularly executed; the capacitors with the same capacitance value comprise: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are respectively connected to the input end and the output end in series; at least two capacitors are connected with the input end and the output end of the digital-to-analog converter (DAC), and the polarity of the input end and the output end connected with at least two capacitors in the first group of capacitors in the first working mode is opposite to that of the input end and the output end connected with at least two capacitors in the first group of capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
in the third working mode, the positions of the first group of capacitors and the second group of capacitors in the first working mode are exchanged; in the fourth working mode, the positions of the first group of capacitors and the second group of capacitors in the second working mode are exchanged; to cancel the offset voltage by charge incorporation on the second set of capacitors.
In an exemplary embodiment of the present application, the plurality of operation modes may further include: an initial sampling mode;
in the initial sampling mode, the first group of capacitors are used as sampling capacitors to carry out signal acquisition, and initial acquisition voltage is obtained; and the chopper and the transconductance amplifier and the chopper and the capacitor are in a disconnected state, and the capacitors in the second group of capacitors are in a floating state.
In an exemplary embodiment of the present application, the chopper may include a first chopper and a second chopper;
wherein the first chopper and the second chopper are used for connecting the first group of capacitors or the second group of capacitors with the forward input end and the reverse input end;
the DAC output includes: a first DAC output and a second DAC output;
the first set of capacitances may include: the first capacitor, the second capacitor, the third capacitor and the fourth capacitor; the second set of capacitances comprises: a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor;
the first capacitor, the second capacitor, the fifth capacitor and the sixth capacitor are used for connecting an input end or an output end of a first side of the transconductance amplifier;
the third capacitor, the fourth capacitor, the seventh capacitor and the eighth capacitor are used for connecting an input end or an output end of a second side of the transconductance amplifier.
In an exemplary embodiment of the present application, the first operation mode may include:
the first capacitor is connected between the output end of the first DAC and the reverse input end in series;
the second capacitor is connected between the reverse input end and the forward output end in series;
the first end of the fifth capacitor is connected with the positive output end, and the second end of the fifth capacitor is applied with a common mode level;
the sixth capacitor is suspended;
the third capacitor is connected between the output end of the second DAC and the positive input end in series;
the fourth capacitor is connected between the positive input end and the negative output end in series;
the first end of the seventh capacitor is connected with the inverted output end, and the common mode level is applied to the second end of the seventh capacitor;
the eighth capacitor is suspended.
In an exemplary embodiment of the present application, the second operation mode may include:
the second capacitor is connected between the output end of the first DAC and the positive input end in series;
the first capacitor is connected between the positive input end and the negative output end in series;
the first end of the sixth capacitor is connected with the reverse output end, and the second end of the sixth capacitor is applied with a common mode level;
the fifth capacitor is suspended;
the fourth capacitor is connected between the output end of the second DAC and the reverse input end in series;
the third capacitor is connected between the reverse input end and the forward output end in series;
the first end of the eighth capacitor is connected with the positive output end, and the common mode level is applied to the second end of the eighth capacitor;
the seventh capacitor is suspended.
In an exemplary embodiment of the present application, the third operation mode may include:
the fifth capacitor is connected between the output end of the first DAC and the reverse input end in series;
the sixth capacitor is connected in series between the reverse input end and the forward output end;
the first end of the first capacitor is connected with the positive output end, and a common mode level is applied to the second end of the first capacitor;
the second capacitor is suspended;
the seventh capacitor is connected between the output end of the second DAC and the positive input end in series;
the eighth capacitor is connected in series between the positive input end and the negative output end;
the first end of the third capacitor is connected with the reverse output end, and the common mode level is applied to the second end of the third capacitor;
the fourth capacitor is suspended.
In an exemplary embodiment of the present application, the fourth operation mode may include:
the sixth capacitor is connected between the output end of the first DAC and the positive input end in series;
the fifth capacitor is connected between the positive input end and the negative output end in series;
the first end of the second capacitor is connected with the reverse output end, and a common mode level is applied to the second end;
the first capacitor is suspended;
the eighth capacitor is connected between the output end of the second DAC and the reverse input end in series;
the seventh capacitor is connected in series between the reverse input end and the forward output end;
the first end of the fourth capacitor is connected with the positive output end, and the common mode level is applied to the second end of the fourth capacitor;
the third capacitor is suspended.
In an exemplary embodiment of the present application, the initial sampling pattern may include:
the first capacitor and the second capacitor are connected in parallel;
the first ends of the first capacitor and the second capacitor are connected with a forward input signal Vip, and the second ends are applied with a common mode level;
the third capacitor and the fourth capacitor are connected in parallel;
the first ends of the third capacitor and the fourth capacitor are connected with an inverted input signal Vin, and the common mode level is applied to the second ends of the third capacitor and the fourth capacitor.
The embodiment of the application also provides a circulating method of the circulating ADC for the CMOS image sensor, which can be suitable for the circulating ADC for the CMOS image sensor; the method may include:
sequentially and circularly executing a plurality of preset working modes; in a plurality of working modes, different capacitors in the circulating ADC sample the output voltage of the transconductance amplifier, and the connection mode of the capacitors and the polarity of the connected ends are changed when the modes are changed, so that the charges on the capacitors are combined to eliminate offset voltage.
In an exemplary embodiment of the present application, the plurality of operation modes may include: a first working mode, a second working mode, a third working mode and a fourth working mode; the capacitance may include: a first set of capacitors and a second set of capacitors;
in the first operating mode and the second operating mode, at least two capacitors in the first group of capacitors are respectively connected in series to the input end and the output end of a transconductance amplifier in the cyclic ADC; at least two capacitors are connected with the input end and the output end of the digital-to-analog converter (DAC), and the polarity of the input end and the output end connected with at least two capacitors in the first group of capacitors in the first working mode is opposite to that of the input end and the output end connected with at least two capacitors in the first group of capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
in the third working mode, the positions of the first group of capacitors and the second group of capacitors in the first working mode are exchanged; in the fourth working mode, the positions of the first group of capacitors and the second group of capacitors in the second working mode are exchanged; to cancel the offset voltage by charge incorporation on the second set of capacitors.
Compared with the related art, the embodiment of the application can comprise the following steps: the circuit comprises a transconductance amplifier, a chopper, a plurality of capacitors with the same capacitance value and a plurality of control switches; the chopper is arranged to control the connection mode of the input end and the output end of the transconductance amplifier and the capacitor; the input terminal includes: a forward input and a reverse input, the output comprising: a forward output terminal and a reverse output terminal; the control switch is set to control the access modes of the transconductance amplifier and the capacitor in each working mode; wherein the switching states of the chopper and the plurality of control switches cause the cyclic analog-to-digital converter ADC to have a plurality of operating modes; the various modes of operation include: a first working mode, a second working mode, a third working mode and a fourth working mode; the first working mode, the second working mode, the third working mode and the fourth working mode are sequentially and circularly executed; the capacitors with the same capacitance value comprise: a first set of capacitors and a second set of capacitors; in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are respectively connected to the input end and the output end in series; at least two capacitors are connected with the input end and the output end of the digital-to-analog converter (DAC), and the polarity of the input end and the output end connected with at least two capacitors in the first group of capacitors in the first working mode is opposite to that of the input end and the output end connected with at least two capacitors in the first group of capacitors in the second working mode; in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors; in the third working mode, the positions of the first group of capacitors and the second group of capacitors in the first working mode are exchanged; in the fourth working mode, the positions of the first group of capacitors and the second group of capacitors in the second working mode are exchanged; to cancel the offset voltage by charge incorporation on the second set of capacitors. By the scheme of the embodiment, the problems of capacitor mismatch and offset voltage of the transconductance amplifier are solved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
FIG. 1 is a block diagram of a cyclic ADC according to an embodiment of the present application;
FIG. 2 is a circuit diagram illustrating a first operating mode according to an embodiment of the present application;
FIG. 3 is a circuit diagram illustrating a second operating mode according to an embodiment of the present application;
FIG. 4 is a circuit diagram illustrating a third operating mode according to an embodiment of the present application;
FIG. 5 is a circuit diagram illustrating a fourth operating mode according to an embodiment of the present application;
FIG. 6 is a circuit diagram illustrating an initial sampling mode according to an embodiment of the present application;
FIG. 7 is a block diagram of a CMOS image sensor system according to an embodiment of the present application;
fig. 8 is a flowchart of a cyclic ADC cycle method according to an embodiment of the present application.
Detailed Description
The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
The embodiment of the present application provides a cyclic ADC for a CMOS image sensor, as shown in fig. 1, which may include: the circuit comprises a transconductance amplifier A, a chopper, a plurality of capacitors C with the same capacitance value and a plurality of control switches B;
the chopper is arranged to control the connection mode of the input end and the output end of the transconductance amplifier and the capacitor C; the input terminal includes: a forward input and a reverse input, the output comprising: a forward output terminal and a reverse output terminal;
the control switch B is set to control the access modes of the transconductance amplifier and the capacitor C in each working mode;
wherein the switching states of said chopper and said plurality of control switches cause the cyclic analog-to-digital converter ADC to have a plurality of said operating modes; as shown in fig. 2, 3, 4, and 5, the plurality of operation modes include: a first working mode, a second working mode, a third working mode and a fourth working mode; the first working mode, the second working mode, the third working mode and the fourth working mode are sequentially and circularly executed; the capacitors with the same capacitance value comprise: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are respectively connected to the input end and the output end in series; at least two capacitors are connected with the input end and the output end of the digital-to-analog converter (DAC), and the polarity of the input end and the output end connected with at least two capacitors in the first group of capacitors in the first working mode is opposite to that of the input end and the output end connected with at least two capacitors in the first group of capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
in the third working mode, the positions of the first group of capacitors and the second group of capacitors in the first working mode are exchanged; in the fourth working mode, the positions of the first group of capacitors and the second group of capacitors in the second working mode are exchanged; to cancel the offset voltage by charge incorporation on the second set of capacitors.
In an exemplary embodiment of the present application, all capacitors employ the same magnitude of capacitance.
In an exemplary embodiment of the present application, the present application may adopt a structure of 1.5 bits per cycle. As shown in fig. 6, the input signal is first sampled and quantized to a 1.5bit digital output, and then can be cyclically operated in the order of first operation mode (fig. 2) → second operation mode (fig. 3) → third operation mode (fig. 4) → fourth operation mode (fig. 5). The first mode of operation (fig. 2) and the second mode of operation (fig. 3), or the third mode of operation (fig. 4) and the fourth mode of operation (fig. 5) may be defined as one conversion cycle, each conversion cycle producing a 1.5bit digital output, and 14 conversion cycles plus one sampling cycle (fig. 6) may be used in order to obtain an overall 16-bit analog-to-digital conversion result. In one conversion period, the elimination of capacitance mismatch and the elimination of offset voltage of the transconductance amplifier are realized by exchanging the position of a capacitor and the positive and negative polarities of the transconductance amplifier, wherein the former can be called as a capacitance mismatch averaging technology, and the latter can be called as a chopping loss-of-modulation technology.
In an exemplary embodiment of the present application, the chopper may include a first chopper1 and a second chopper 2;
wherein the first chopper1 and the second chopper2 are each configured to connect the first set of capacitors or the second set of capacitors to the forward input terminal and the reverse input terminal.
In an exemplary embodiment of the present application, there may be four switches in the chopper (chopper), with lateral conduction or cross conduction being selected according to different operating phases.
In an exemplary embodiment of the present application, the first set of capacitances may include: a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4; the second set of capacitances comprises: a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8;
wherein the first capacitor C1, the second capacitor C2, the fifth capacitor C5 and the sixth capacitor C6 are used for connecting the input end or the output end of the first side of the transconductance amplifier A;
the third capacitor C3, the fourth capacitor C4, the seventh capacitor C7 and the eighth capacitor C8 are used for connecting the input end or the output end of the second side of the transconductance amplifier a.
In an exemplary embodiment of the present application, as shown in fig. 6, the plurality of operation modes may further include: an initial sampling mode;
in the initial sampling mode, the first group of capacitors are used as sampling capacitors to carry out signal acquisition, and initial acquisition voltage is obtained; and the chopper and the transconductance amplifier and the chopper and the capacitor are in a disconnected state, and the capacitors in the second group of capacitors are in a floating state.
In an exemplary embodiment of the present application, the DAC output terminal may include: a first DAC output terminal and a second DAC output terminal.
In an exemplary embodiment of the present application, the initial sampling mode may include:
the first capacitor C1 and the second capacitor C2 are connected in parallel;
the first end of the first capacitor C1 and the second end of the second capacitor C2 are connected to the positive input signal Vip as shown in fig. 6, and the second end is applied with a common mode level VCM;
the third capacitor C3 and the fourth capacitor C4 are connected in parallel;
the third capacitor C3 and the fourth capacitor C4 have first terminals connected to the inverted input signal Vin as shown in fig. 6, and second terminals to which the common mode level VCM is applied.
In an exemplary embodiment of the present application, as shown in fig. 2, the first operation mode may include:
the first capacitor C1 is connected in series between the output end of a first DAC (digital-to-analog converter) and the inverting input end;
the second capacitor C2 is connected in series between the inverting input terminal and the forward output terminal;
the first end of the fifth capacitor C5 is connected with the positive output end, and the common mode level is applied to the second end;
the sixth capacitor C6 is floating;
the third capacitor C3 is connected in series between the output end of the second DAC and the positive input end;
the fourth capacitor C4 is connected in series between the positive input end and the negative output end;
the first end of the seventh capacitor C7 is connected with the inverted output end, and the common mode level is applied to the second end;
the eighth capacitor C8 is floating.
The VDACp (which can comprise VDACp1 and VDACp2) and VDACn (which can comprise VDACn1 and VDACn2) can be accessed to the VRP, VRN or VCM according to the value of the comparator in the analog-to-digital converter; VRP represents a reference voltage high level; VRN represents a reference voltage low level; VCM represents the common mode level.
In an exemplary embodiment of the present application, as shown in fig. 3, the second operation mode may include:
the second capacitor C2 is connected in series between the first DAC output end and the positive input end;
the first capacitor C1 is connected in series between the positive input end and the negative output end;
the first end of the sixth capacitor C6 is connected with the inverted output end, and the common mode level is applied to the second end;
the fifth capacitor C5 is floating;
the fourth capacitor C4 is connected in series between the output end of the second DAC and the inverting input end;
the third capacitor C3 is connected in series between the inverting input terminal and the forward output terminal;
the first end of the eighth capacitor C8 is connected with the positive output end, and the common mode level is applied to the second end;
the seventh capacitor C7 is floating.
In an exemplary embodiment of the present application, as shown in fig. 4, the third operation mode may include:
the fifth capacitor C5 is connected in series between the output end of the first DAC and the inverting input end;
the sixth capacitor C6 is connected in series between the inverting input terminal and the forward output terminal;
the first end of the first capacitor C1 is connected with the positive output end, and the common mode level is applied to the second end;
the second capacitor C2 is suspended;
the seventh capacitor C7 is connected in series between the output end of the second DAC and the positive input end;
the eighth capacitor C8 is connected in series between the positive input end and the negative output end;
the first end of the third capacitor C3 is connected with the inverted output end, and the common mode level is applied to the second end;
the fourth capacitor C4 is floating.
In an exemplary embodiment of the present application, as shown in fig. 5, the fourth operation mode may include:
the sixth capacitor C6 is connected in series between the first DAC output end and the positive input end;
the fifth capacitor C5 is connected in series between the positive input end and the negative output end;
the first end of the second capacitor C2 is connected with the inverted output end, and the common mode level is applied to the second end;
the first capacitor C1 is suspended;
the eighth capacitor C8 is connected in series between the output end of the second DAC and the inverting input end;
the seventh capacitor C7 is connected in series between the inverting input terminal and the forward output terminal;
the first end of the fourth capacitor C4 is connected with the positive output end, and the common mode level is applied to the second end;
the third capacitor C3 is floating.
In the exemplary embodiment of the present application, which can be illustrated by using fig. 2 and 3 as an example, in one conversion process, to simplify the adoption of single-ended analysis, two residual voltages are sampled by C5 and C6 respectively by exchanging the positions of C1 and C2 and the polarities of transconductance amplifiers, and in the next conversion process, the charges on C5 and C6 are combined together, so that the capacitance mismatch of C1 and C2 and the offset voltage of transconductance amplifiers are eliminated.
In an exemplary embodiment of the present application, the above-described cyclic ADC may be applied to a CMOS image sensor as shown in fig. 7. The Pixel Array is a detector part of an embodiment of the present application, and the analog-to-digital converter ADC is responsible for converting a signal of the PD into a digital signal, and outputting the digital signal through an LVDS Driver (low voltage differential signal Driver) port after passing through an Algorithm & Timing Control (Algorithm and Timing Control) module and a FIFO (first in first out) module in sequence. The Global Timing Control module is connected with the Vertical Scanning Block module to generate all Timing Control signals, and the Vertical Scanning Block module is responsible for addressing and resetting the PD. The other end of the Global Timing Control module is connected with an I2C Port (inter-Integrated Circuit bus interface). A temperature Sensor (Temp Sensor) may also be provided in the CMOS image Sensor. The CMOS image sensor may further include a Voltage & Current Generator (Voltage Current Generator) that supplies power to the Pixel Array and the ADC.
The embodiment of the application also provides a circulating method of the circulating ADC for the CMOS image sensor, which can be suitable for the circulating ADC for the CMOS image sensor; as shown in fig. 8, the method may include step S101:
s101, sequentially and circularly executing a plurality of preset working modes; in a plurality of working modes, different capacitors in the circulating ADC sample the output voltage of a transconductance amplifier (OTA), and the connection mode and the polarity of a connected end of the capacitor are changed when the mode is changed, so that the charges on the capacitor are combined to eliminate offset voltage.
In an exemplary embodiment of the present application, the plurality of operation modes may include: a first working mode, a second working mode, a third working mode and a fourth working mode; the capacitance may include: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are respectively connected to the input end and the output end of an amplifier in the cyclic ADC in series, at least two capacitors are connected to the input end and the output end of a digital-to-analog converter (DAC), and the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the first working mode is opposite to that of the input end and the output end of the at least two capacitors in the first group of capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
in the third working mode, the positions of the first group of capacitors and the second group of capacitors in the first working mode are exchanged; in the fourth working mode, the positions of the first group of capacitors and the second group of capacitors in the second working mode are exchanged; to cancel the offset voltage by charge incorporation on the second set of capacitors.
In the exemplary embodiment of the application, on the basis of the conventional CYCLIC ADC, the performance of CYCLIC ADC is greatly improved by adding a capacitance averaging technology and a chopping and detuning technology, and the conversion precision of 16 bits can be realized.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (10)
1. A cyclic ADC for a CMOS image sensor, comprising: the circuit comprises a transconductance amplifier, a chopper, a plurality of capacitors with the same capacitance value and a plurality of control switches;
the chopper is arranged to control the connection mode of the input end and the output end of the transconductance amplifier and the capacitor; the input terminal includes: a forward input and a reverse input, the output comprising: a forward output terminal and a reverse output terminal;
the control switch is set to control the access modes of the transconductance amplifier and the capacitor in each working mode;
wherein the switching states of said chopper and said plurality of control switches cause the cyclic analog-to-digital converter ADC to have a plurality of said operating modes; the plurality of operating modes include: a first working mode, a second working mode, a third working mode and a fourth working mode; the first working mode, the second working mode, the third working mode and the fourth working mode are sequentially and circularly executed; the capacitors with the same capacitance value comprise: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are respectively connected to the input end and the output end in series; at least two capacitors are connected with the input end and the DAC output end of the digital-to-analog converter, and the polarity of the input end and the output end connected with the at least two capacitors in the first working mode is opposite to that of the input end and the output end connected with the at least two capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
in the third working mode, the positions of the first group of capacitors and the second group of capacitors in the first working mode are exchanged; in the fourth working mode, the positions of the first group of capacitors and the second group of capacitors in the second working mode are exchanged; to cancel the offset voltage by charge incorporation on the second set of capacitors.
2. The cyclic ADC for a CMOS image sensor according to claim 1, wherein said plurality of operating modes further comprises: an initial sampling mode;
in the initial sampling mode, the first group of capacitors are used as sampling capacitors to carry out signal acquisition, and initial acquisition voltage is obtained; and the chopper and the transconductance amplifier and the chopper and the capacitor are in a disconnected state, and the capacitors in the second group of capacitors are in a floating state.
3. The cyclic ADC for a CMOS image sensor according to claim 1 or 2, wherein said chopper comprises a first chopper and a second chopper;
wherein the first chopper and the second chopper are used for connecting the first group of capacitors or the second group of capacitors with the forward input end and the reverse input end;
the DAC output includes: a first DAC output and a second DAC output; the first set of capacitors includes: the first capacitor, the second capacitor, the third capacitor and the fourth capacitor; the second set of capacitances comprises: a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor;
the first capacitor, the second capacitor, the fifth capacitor and the sixth capacitor are used for connecting an input end or an output end of a first side of the transconductance amplifier;
the third capacitor, the fourth capacitor, the seventh capacitor and the eighth capacitor are used for connecting an input end or an output end of a second side of the transconductance amplifier.
4. The cyclic ADC of claim 3, wherein the first operating mode comprises:
the first capacitor is connected in series between the first DAC output end and the reverse input end;
the second capacitor is connected between the reverse input end and the forward output end in series;
the first end of the fifth capacitor is connected with the positive output end, and the second end of the fifth capacitor is applied with a common mode level;
the sixth capacitor is suspended;
the third capacitor is connected in series between the second DAC output end and the positive input end;
the fourth capacitor is connected between the positive input end and the negative output end in series;
the first end of the seventh capacitor is connected with the inverted output end, and the common mode level is applied to the second end of the seventh capacitor;
the eighth capacitor is suspended.
5. The cyclic ADC of claim 3, wherein the second operating mode comprises:
the second capacitor is connected in series between the first DAC output end and the positive input end;
the first capacitor is connected between the positive input end and the negative output end in series;
the first end of the sixth capacitor is connected with the reverse output end, and the second end of the sixth capacitor is applied with a common mode level;
the fifth capacitor is suspended;
the fourth capacitor is connected in series between the second DAC output end and the inverting input end;
the third capacitor is connected between the reverse input end and the forward output end in series;
the first end of the eighth capacitor is connected with the positive output end, and the common mode level is applied to the second end of the eighth capacitor;
the seventh capacitor is suspended.
6. The cyclic ADC of claim 3, wherein the third operating mode comprises:
the fifth capacitor is connected in series between the first DAC output end and the inverting input end;
the sixth capacitor is connected in series between the reverse input end and the forward output end;
the first end of the first capacitor is connected with the positive output end, and a common mode level is applied to the second end of the first capacitor;
the second capacitor is suspended;
the seventh capacitor is connected in series between the second DAC output end and the positive input end;
the eighth capacitor is connected in series between the positive input end and the negative output end;
the first end of the third capacitor is connected with the reverse output end, and the common mode level is applied to the second end of the third capacitor;
the fourth capacitor is suspended.
7. The cyclic ADC of claim 3, wherein the fourth mode of operation comprises:
the sixth capacitor is connected in series between the first DAC output end and the positive input end;
the fifth capacitor is connected between the positive input end and the negative output end in series;
the first end of the second capacitor is connected with the reverse output end, and a common mode level is applied to the second end;
the first capacitor is suspended;
the eighth capacitor is connected in series between the second DAC output end and the inverting input end;
the seventh capacitor is connected in series between the reverse input end and the forward output end;
the first end of the fourth capacitor is connected with the positive output end, and the common mode level is applied to the second end of the fourth capacitor;
the third capacitor is suspended.
8. The cyclic ADC for a CMOS image sensor of claim 3, wherein the initial sampling mode comprises:
the first capacitor and the second capacitor are connected in parallel;
the first ends of the first capacitor and the second capacitor are connected with a forward input signal Vip, and the second ends are applied with a common mode level;
the third capacitor and the fourth capacitor are connected in parallel;
the first ends of the third capacitor and the fourth capacitor are connected with an inverted input signal Vin, and the common mode level is applied to the second ends of the third capacitor and the fourth capacitor.
9. A method for cycling a cyclic ADC for a CMOS image sensor, which is applied to the cyclic ADC for a CMOS image sensor according to any one of claims 1 to 8; the method comprises the following steps:
sequentially and circularly executing a plurality of preset working modes; in a plurality of working modes, different capacitors in the circulating ADC sample the output voltage of the transconductance amplifier, and the connection mode of the capacitors and the polarity of the connected ends are changed when the modes are changed, so that the charges on the capacitors are combined to eliminate offset voltage.
10. The method of cycling for a cycled ADC for a CMOS image sensor of claim 9, wherein the plurality of said operating modes comprises: a first working mode, a second working mode, a third working mode and a fourth working mode; the capacitor includes: a first set of capacitors and a second set of capacitors;
in the first operating mode and the second operating mode, at least two capacitors in the first group of capacitors are respectively connected in series to the input end and the output end of a transconductance amplifier in the cyclic ADC; at least two capacitors are connected with the input end and the DAC output end of the digital-to-analog converter, and the polarity of the input end and the output end connected with the at least two capacitors in the first working mode is opposite to that of the input end and the output end connected with the at least two capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
in the third working mode, the positions of the first group of capacitors and the second group of capacitors in the first working mode are exchanged; in the fourth working mode, the positions of the first group of capacitors and the second group of capacitors in the second working mode are exchanged; to cancel the offset voltage by charge incorporation on the second set of capacitors.
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