CN114244359B - Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter - Google Patents
Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter Download PDFInfo
- Publication number
- CN114244359B CN114244359B CN202111582541.6A CN202111582541A CN114244359B CN 114244359 B CN114244359 B CN 114244359B CN 202111582541 A CN202111582541 A CN 202111582541A CN 114244359 B CN114244359 B CN 114244359B
- Authority
- CN
- China
- Prior art keywords
- calibration
- analog
- digital converter
- configuration
- comparison result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a calibration method, a calibration module and an analog-to-digital converter of the analog-to-digital converter, wherein the method comprises the following steps: acquiring a calibration configuration, wherein the calibration configuration is used for showing that a calibration mode adopted in the current calibration process is at least one of a plurality of calibration modes supported by an analog-to-digital converter; calibrating the analog-to-digital converter according to the calibration configuration to generate calibration parameters; determining a comparison of the calibration parameter to an expected parameter; judging whether to calibrate again according to the comparison result; and updating the parameters of the capacitor array of the analog-to-digital converter according to the current calibration parameters under the condition that the comparison result meets the condition of finishing calibration. Therefore, the calibration configuration can be set according to the actual scene, the analog-to-digital converter is calibrated according to the calibration configuration, and the calibration efficiency is improved on the premise of ensuring the calibration precision.
Description
Technical Field
The present invention relates to the field of digital signal processing, and in particular, to a calibration method and a calibration module for an analog-to-digital converter, and an analog-to-digital converter.
Background
The existing ADC (analog-to-digital converter) is limited by different process corners in the manufacturing process due to non-ideal characteristic factors such as parasitic capacitance, capacitance mismatch and the like, so that characteristic parameters are easy to appear. In order to eliminate errors due to capacitance mismatch, trimming techniques as well as calibration techniques may be employed. The conventional trimming technique is to test after the chip is manufactured and trim by laser according to the test result, but this method is expensive and cannot deal with the error caused by the aging of the device. Moreover, the current calibration technology cannot meet the requirement of high working efficiency under the condition of high precision when the adaptation error caused by the capacitance is eliminated.
Disclosure of Invention
In order to solve the above problems, embodiments of the present invention provide a calibration method, a calibration module and an analog-to-digital converter for an analog-to-digital converter.
According to a first aspect of the present invention, there is provided a method of self-calibration of an analog to digital converter, the method comprising: acquiring a calibration configuration, wherein the calibration configuration is used for showing that a calibration mode adopted in the current calibration process is at least one of a plurality of calibration modes supported by an analog-to-digital converter; calibrating the analog-to-digital converter according to the calibration configuration to generate calibration parameters; determining a comparison of the calibration parameter to an expected parameter; judging whether to calibrate again according to the comparison result; and updating the parameters of the capacitor array of the analog-to-digital converter according to the current calibration parameters under the condition that the comparison result meets the condition of finishing calibration.
According to an embodiment of the invention, the obtaining of the calibration configuration comprises one of: acquiring calibration configuration under the condition that the analog-to-digital converter is powered on and started; in the case where the analog-to-digital converter detects a distorted signal, a calibration configuration is obtained.
According to an embodiment of the present invention, the analog-to-digital converter detects the distortion signal by: collecting the current clock period of the analog-to-digital converter; determining an actual deviation of the current clock period from a reference clock period; and determining that the analog-to-digital converter detects a distortion signal when the actual deviation exceeds a preset deviation value.
According to an embodiment of the present invention, the obtaining the calibration configuration when the analog-to-digital converter detects a distortion signal includes: detecting a sampling frequency of the analog-to-digital converter in case the analog-to-digital converter detects a distorted signal; obtaining the calibration configuration generated by the analog-to-digital converter according to the sampling frequency.
According to an embodiment of the present invention, the determining whether to perform calibration again according to the comparison result includes: judging whether the comparison result meets a preset range or not; judging that the calibration is finished under the condition that the comparison result is within a preset range; and under the condition that the comparison result exceeds a preset range, calibrating the analog-to-digital converter again until the comparison result accords with the preset range, and judging to finish calibration.
According to an embodiment of the present invention, the determining whether to perform calibration again according to the comparison result includes: and judging to finish the calibration under the condition that the comparison result exceeds the preset range but the calibration times are more than the set cycle times.
According to an embodiment of the present invention, the analog-to-digital converter is a combination of a successive approximation register and a slope dual architecture; accordingly, the calibration mode includes at least one of: static comparator calibration, dynamic comparator calibration, and capacitance weight calibration.
According to a second aspect of the present invention, there is also provided a calibration module for calibrating an analog to digital converter, the calibration module comprising: the calibration trigger circuit is used for detecting a distortion signal of the analog-to-digital converter and sending a calibration trigger signal to the state machine in response to the distortion signal; a first register coupled to the state machine for sending the calibration configuration to the state machine; the state machine is connected with the first register and the calibration parameter acquisition circuit and used for acquiring calibration configuration from the state machine, calibrating the analog-to-digital converter according to the calibration configuration and obtaining calibration output; the state machine is also connected with the weight updating control circuit and is used for sending a control signal to the weight updating control circuit under the condition of finishing calibration, and the control signal is used for showing the end of calibration; the calibration parameter acquisition circuit is connected with the state machine and used for acquiring calibration output from the state machine and generating calibration parameters according to the calibration output; the second register is connected with the calibration parameter acquisition circuit and the weight updating control circuit and is used for registering the calibration parameters and sending the calibration parameters to the weight updating control circuit; and the weight updating control circuit is connected with the circuit needing to be updated of the mode converter and is used for updating the circuit needing to be updated according to the calibration parameters.
According to an embodiment of the present invention, the calibration module further comprises: and the frequency detection circuit is connected with the calibration trigger circuit and used for detecting the sampling frequency of the analog-to-digital converter and sending the sampling frequency to the first register through the calibration trigger circuit so that the first register determines the calibration configuration according to the sampling frequency.
According to a third aspect of the present invention, there is also provided an analog-to-digital converter comprising the above calibration module.
The calibration method, the calibration module and the analog-to-digital converter for calibrating the analog-to-digital converter can adjust the calibration mode used for calibrating the analog-to-digital converter according to different application scenes, and avoid the condition of low calibration efficiency caused by the fact that a plurality of calibration modes supported by the analog-to-digital converter are respectively used for calibrating the analog-to-digital converter in the conventional calibration process. Therefore, on the premise of ensuring the precision of the analog-to-digital converter, the calibration efficiency of the analog-to-digital converter is obviously improved.
It is to be understood that the teachings of the present invention need not achieve all of the above-described benefits, but that certain embodiments may achieve certain technical benefits and other embodiments of the invention may achieve benefits not mentioned above.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, like or corresponding reference characters designate like or corresponding parts.
Fig. 1 is a schematic diagram illustrating a specific application scenario of a calibration method for an analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an implementation flow of a calibration method for an analog-to-digital converter according to an embodiment of the present invention;
fig. 3 is a schematic diagram showing a detailed flow of a state machine of a calibration module of the calibration method for an analog-to-digital converter according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a configuration of a calibration module of a calibration method for an analog-to-digital converter according to an embodiment of the present invention.
Detailed Description
The principles and spirit of the present invention will be described with reference to several exemplary embodiments. It is understood that these embodiments are given only to enable those skilled in the art to better understand and to implement the present invention, and do not limit the scope of the present invention in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The technical solution of the present invention is further elaborated below with reference to the drawings and the specific embodiments.
First, an application scenario of the calibration method of the analog-to-digital converter according to the embodiment of the present invention is described, and the calibration method of the analog-to-digital converter according to the present invention can be applied to analog-to-digital converters having multiple calibration modes, such as a SAR ADC (successive approximation register analog-to-digital converter) and a SAR-PIPELINE ADC (time-interleaved ADC). Of course, the invention is also applicable to a combined structure analog-to-digital converter formed by combining the SAR structure with other structures. In the case of an analog-to-digital converter configured with multiple calibration modes, in the calibration process of the prior art, the analog-to-digital converter must be calibrated separately by using each of the multiple calibration modes. For example: when the calibration mode includes both comparator calibration and capacitance calibration, the conventional calibration process must complete the calibration of the comparator and capacitance. In practical applications, if the requirements of conversion speed and conversion accuracy of some analog-to-digital converters are low, only part of calibration modes need to be calibrated to meet the actual requirements of the analog-to-digital converters, and at this time, if the analog-to-digital converters are still calibrated in all the calibration modes, the calibration efficiency of the analog-to-digital converters will be seriously affected. Therefore, the method for calibrating the analog-to-digital converter by selecting the proper calibration mode according to the actual scene is designed for the analog-to-digital converter configured with multiple calibration modes, the accuracy of the analog-to-digital converter is guaranteed, meanwhile, the analog-to-digital converter is prevented from being unnecessarily calibrated, and therefore the calibration efficiency of the analog-to-digital converter is improved.
For example, referring to fig. 1, in the conventional calibration, the analog-to-digital converter based on the SAR and SLOPE architectures calibrates the dynamic comparator of the SAR part, the static comparator of the SLOPE part, and the capacitor array, but in the actual requirement of the digital-to-analog converter, only the calibration of the SAR part or the SLOPE part or the capacitor array may be needed to meet the requirement of the digital-to-analog converter. Since the conventional calibration process calibrates all error-generating parts, the analog-to-digital converter is unnecessarily calibrated, and the calibration efficiency of the analog-to-digital converter is reduced. Therefore, the calibration module is added in the analog-to-digital converter, and the calibration module is connected with both the SAR part and the SLOPE part of the analog-to-digital converter. When the analog-to-digital converter is calibrated, the analog-to-digital converter can only calibrate corresponding to the actual requirement of the analog-to-digital converter according to the calibration configuration only by setting the calibration configuration in the calibration module according to the actual requirement of the analog-to-digital converter. For example: the precision of the analog-to-digital converter shown in fig. 1 is 12 bits, and if the sampling frequency of the analog-to-digital converter is set to be a low frequency, an error generated in the working process of the analog-to-digital converter is small, and the precision does not change too much, so that the calibration of the capacitance weight with a long time is not needed, and the requirements of the analog-to-digital converter can be completely met only by selecting a dynamic comparator of the SAR part or a static comparator of the SLOPE part for calibration. However, in contrast, the present application may set the calibration configuration to enable the analog-to-digital converter to only perform calibration of the dynamic comparator of the SAR part or the static comparator of the SLOPE part or both the dynamic comparator and the static comparator. Therefore, the method and the device can avoid unnecessary calibration while ensuring the requirements of the analog-to-digital converter such as precision and the like, thereby improving the calibration efficiency of the analog-to-digital converter.
It should be noted that, the foregoing is only a simple description of the application scenario of the embodiment of the present invention for better describing the scheme, and is not intended to limit the application scenario of the embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a first implementation flow of a calibration method of an analog-to-digital converter according to an embodiment of the present invention.
Referring to fig. 2, a calibration method of an analog-to-digital converter according to an embodiment of the present invention at least includes the following operation flows: operation 201, acquiring a calibration configuration, where the calibration configuration is used to show that a calibration mode adopted in the current calibration process is at least one of multiple calibration modes supported by an analog-to-digital converter; operation 202, calibrating the analog-to-digital converter according to the calibration configuration to generate calibration parameters; an operation 203 of determining a comparison result of the calibration parameter and the expected parameter; operation 204, according to the comparison result, judging whether to perform calibration again; in operation 205, in a case that the comparison result satisfies the end calibration condition, the parameter of the capacitor array of the analog-to-digital converter is updated according to the current calibration parameter.
In operation 201, a calibration configuration is obtained, where the calibration configuration is used to show that the calibration mode adopted in the present calibration process is at least one of a plurality of calibration modes supported by the analog-to-digital converter.
Before calibration, a user sets the calibration configuration of the analog-to-digital converter through a software program of the analog-to-digital converter according to the actual requirement of the analog-to-digital converter at the time, for example: the conversion accuracy and the conversion speed of the analog-to-digital converter and the like.
Here, the calibration configuration may be binary coded and one binary code is provided for each calibration pattern or set of calibration patterns as a trigger condition. After the calibration is triggered by reaching the trigger condition of calibration, the calibration configuration is first obtained, and the calibration configuration shows what modes need to be calibrated in the current calibration.
Further, in this embodiment of the present invention, acquiring the calibration configuration includes: the analog-to-digital converter is powered on and started to obtain calibration configuration; and detecting a distortion signal in a normal working mode of the analog-to-digital converter to obtain a calibration configuration.
Specifically, calibration is automatically triggered when the analog-to-digital converter is powered on and started, and after the calibration is triggered, the analog-to-digital converter acquires a calibration configuration and performs self-calibration according to a calibration mode shown by the calibration configuration.
Further, the analog-to-digital converter is distorted due to interference, random noise, aging and the like during the operation process, and the analog-to-digital converter detects the distorted signal. Calibration is required after the analog-to-digital converter is distorted. Therefore, after the analog-to-digital converter detects the distortion signal, a calibration configuration is obtained, and calibration is performed according to the calibration configuration.
In this embodiment of the present invention, the analog-to-digital converter may detect the distorted signal by: collecting the current clock period; counting the actual deviation of the current time and a reference clock; and in the case that the actual deviation exceeds the preset deviation value, the distortion signal is considered to be detected.
Specifically, after the analog-to-digital converter operates for a period of time, the analog-to-digital converter is affected by various factors, and the clock period of the analog-to-digital converter changes, so that the clock period deviates from the reference value. Therefore, when the acquired current clock period has a deviation from the reference clock and the actual deviation exceeds the preset deviation range, the analog-to-digital converter is determined to be distorted and needs to be calibrated.
Further, the method for determining the deviation of the clock period from the reference clock may include a time interval error method, a period jitter, an adjacent period jitter, and the like.
Specifically, the time interval error method is as follows: and counting the deviation between the collected edge of the actual clock and the edge of the ideal clock. The cycle jitter is: the deviation between the actual collected clock period (rising edge to rising edge) and the ideal clock is counted. The adjacent cycle jitter is: and counting the deviation between the current period of the actual clock and the last period of the actual clock. It should be noted that the above method for detecting distortion is only one implementation of the present invention, and may also be used to detect an increase in error rate of calibration, distortion of input and output waveforms, and the like in an actual process.
Accordingly, in this embodiment of the present invention, the calibration configuration obtained in case of distortion of the analog-to-digital converter can be obtained by the following method: in case the analog-to-digital converter detects the distorted signal, the sampling frequency of the analog-to-digital converter is detected, and the calibration configuration is generated according to the sampling frequency.
Specifically, after the distortion signal is detected and calibration is triggered, selection of a calibration mode is entered, and at this time, besides setting a calibration configuration by a software program of the analog-to-digital converter before the analog-to-digital converter is initially powered on and started according to actual requirements of the analog-to-digital converter, different calibration configurations can be set for different sampling frequencies of the analog-to-digital converter.
For example, the frequency required by the analog-to-digital converter can be divided into a high frequency, an intermediate frequency and a low frequency, and the distortion time and the conversion accuracy of the analog-to-digital converter are correlated with the sampling frequency. Therefore, in the practical application process, the calibration modes needed to be used by different frequencies can be counted by using methods such as experiments according to the influence of the frequencies on the distortion time and the conversion precision. Thus, when a frequency is detected, the calibration configuration value at that time can be set to a value corresponding to the calibration mode trigger condition at that frequency according to the frequency. For example, when the current actual requirement of the analog-to-digital converter is a low frequency, it is counted according to a plurality of experiments that the analog-to-digital converter only performs calibration on the dynamic comparator with short calibration time and low calibration precision, so that the precision can be maintained and the higher calibration efficiency can be ensured, and thus, the calibration configuration when the frequency is detected can be set to the trigger condition value corresponding to the calibration mode as the dynamic comparator.
After the calibration configuration is obtained, the analog-to-digital converter is calibrated according to the calibration mode shown in the calibration configuration, and generates calibration parameters during the calibration process in operation 202.
Specifically, in the calibration mode, the digital-to-analog converter outputs a codeword, and a reference codeword exists for a corresponding output codeword, and an error codeword can be calculated by using the reference codeword, and then the error codeword is mapped to obtain the calibration parameters. It should be noted that, a specific process of obtaining an error codeword and a calibration parameter according to an output codeword is prior art and is not described herein again.
In operation 203, preset parameters are set in advance for calibration parameters generated in the calibration process, and in this process, a comparison result between the current calibration parameters and the preset parameters is further determined, and it is determined whether an error in the calibration mode meets the current actual requirement of the analog-to-digital converter according to the comparison result, so as to determine whether the analog-to-digital converter needs to be calibrated again.
Specifically, in this embodiment of the present invention, a preset range is set in advance, and after the analog-to-digital converter determines that the comparison result meets the preset range, it determines that the calibration is finished without performing the next calibration; and under the condition that the comparison result exceeds the preset range, the analog-to-digital converter can be calibrated again, and the calibration is judged to be finished until the analog-to-digital converter determines that the comparison result is in the preset range.
Further, in this embodiment of the present invention, a cycle calibration number is also preset, and when the comparison result does not satisfy the preset range, in order to avoid the adc performing calibration all the time, the calibration is forced to be ended when the cycle calibration number is reached.
In operations 204 to 205, if the comparison result obtained in step 203 is within a preset range, the calibration may be ended, and the related parameters of the capacitors capable of generating the mismatch factor in the analog-to-digital converter may be updated according to the calibration parameters at this time. It should be noted that the specific process of updating the related parameter of the capacitor according to the calibration parameter is owned by the prior art, and therefore, the detailed description is omitted.
In an embodiment of the present invention, the analog-to-digital converter used in the calibration method of the present invention may be a SAR-SLOPE ADC (a successive approximation register and SLOPE dual architecture combined analog-to-digital converter), and the corresponding calibration configuration may include CT-CMP calibration (static comparator calibration), D-CMP calibration (dynamic comparator calibration), and Cap Weight calibration (capacitance Weight calibration).
Specifically, the reason why the analog-to-digital converter needs to be calibrated by CT-CMP is that mismatch in manufacturing and fixed flip delay of CT-CMP affect the effective output value of the analog-to-digital converter Slope (Slope-Slope compensation) and thus cause Offset Error of the ADC (analog-to-digital converter). The specific calibration method for CT-CMP calibration of the analog-to-digital converter can be implemented by the following operations: considering the error caused by CT-CMP as fixed DC Offset, and recording the actual output result value B by taking the common mode level input of which the self output result of CT-CMP is A as reference; calculating DC Offset as B-A according to the actual output result B and the output result A; the DC Offset is subtracted from the actual output value in the final operation.
Further, the reason why the analog-to-digital converter needs to be calibrated by D-CMP is that the D-CMP has mismatch in manufacturing, which affects the comparison result of the dynamic comparator. The specific calibration procedure for D-CMP calibration of the analog-to-digital converter can be implemented as follows: and mounting a binary capacitor array constructed by small capacitors on the D-CMP, inputting the same voltage value into two input ends of the dynamic comparator D-CMP for comparison, removing a part of capacitors from one end with low voltage drop speed, and comparing eight times through self-contained SAR logic to finish calibration.
Further, the reason why the Cap Weight calibration is required is that the capacitance Weight may generate mismatch due to parasitic introduction in the layout and process deviation generated in actual manufacturing, so that the actual Weight of the capacitance changes, the analog-to-digital converter cannot correctly quantize the input value, a large error occurs in INL (integral nonlinearity) and DNL (differential nonlinearity) of the analog-to-digital converter, and meanwhile, ENOB (dynamic performance) may be reduced. The Cap Weight calibration for the analog-to-digital converter can be realized by the following operations: based on the fact that the mismatch generated by the low-order capacitor is small, the capacitors behind the third order are all regarded as ideal capacitors, and the low-order capacitors are used for calibrating and representing the first three orders. Taking the third position for calibration as an example, the states of the lower electrode plates of the capacitors at the two sides of the PN are kept consistent, and Vcm is input into the upper electrode plate; switching the lower polar plate of the third-bit capacitor on the P side from 0 to Vref to obtain the voltage difference value of the upper polar plates on the two sides of the PN; and calculating the voltage difference value by using subsequent ADC conversion logic, and representing the actual capacitance value of the calibrated capacitor by using subsequent capacitor weight and an output code according to the calculation result. And calibrating the capacitors on the N side by the same method, and obtaining the actual weight values of the capacitors on the three previous positions by analogy, wherein the P side and the N side represent two different groups of capacitor arrays of the analog-to-digital converter.
Specifically, for example, the implementation flow of the method in this embodiment of the present invention may include: triggering calibration and entering a calibration mode; acquiring calibration configuration, and calibrating according to the calibration configuration to obtain calibration parameters; ending the calibration when the calibration parameter reaches the desired calibration parameter; and sending the calibration parameters to a circuit needing to be updated to update the parameters of the capacitor.
Further, the calibration path shown by the calibration configuration and formed by combining the multiple calibration modes supported by the current calibration may include: CT-CMP calibration, D-CMP calibration, CT-CMP calibration plus D-CMP calibration, CT-CMP plus Cap Weight calibration, D-CMP calibration plus Cap Weight calibration, or CT-CMP calibration plus D-CMP calibration plus Cap Weight calibration, and the like.
Accordingly, referring to fig. 3, after obtaining the calibration configuration, the calibration configuration may show a group of binary code values, and the calibration path has different binary code values preset as the trigger condition. When the code value shown by the calibration configuration is the trigger condition code value corresponding to one of the calibration paths, the analog-to-digital converter can perform calibration of any one of the calibration paths according to the trigger condition code value of the calibration path corresponding to the binary code value shown by the calibration configuration.
Similarly, based on the calibration method based on the analog-to-digital converter described above, an embodiment of the present invention further provides a calibration module 40, configured to execute the calibration method described above, and referring to fig. 4, the calibration module includes: a calibration trigger circuit 41 for detecting a distortion signal of the analog-to-digital converter and sending a calibration trigger signal to the state machine in response to the distortion signal; a first register 42, connected to the state machine, for sending the calibration configuration to the state machine; a state machine 43 connected to the first register and the calibration parameter obtaining circuit, and configured to obtain a calibration configuration from the state machine, calibrate the analog-to-digital converter according to the calibration configuration, and obtain a calibration output; the state machine is also connected with the weight updating control circuit and is used for sending a control signal capable of representing the end of calibration to the weight updating control circuit under the condition of ending the calibration; a calibration parameter obtaining circuit 44, connected to the state machine, for obtaining a calibration output from the state machine and generating a calibration parameter according to the calibration output; the second register 45 is connected with the calibration parameter acquisition circuit and the weight update control circuit and is used for registering the calibration parameters and sending the calibration parameters to the weight update control circuit; and the weight updating control circuit 46 is connected with the circuit needing to be updated of the digital-to-analog converter and used for updating the circuit needing to be updated according to the calibration parameters.
Specifically, a user combines multiple calibration modes according to calibration modes supported by an actually used analog-to-digital converter to obtain multiple calibration paths, and configures the multiple calibration paths and conditional binary code values corresponding to the calibration paths in a state machine. Thus, the user can configure the binary values corresponding to various calibration path conditions in the first register 42 in advance. When the calibration trigger circuit 41 detects a distortion signal in the power-on start or normal operation mode of the analog-to-digital converter, the state machine 43 autonomously obtains the calibration configuration set in the first register in advance to complete the calibration. During the calibration process of the state machine, a plurality of output code words are generated, and these output code words are directly sent to the calibration parameter obtaining circuit 44 and are registered and buffered in the second register 45. Here, the calibration parameter obtaining circuit 44 is a combinational logic circuit, which has the logic of the error calculation formula therein, and each codeword output in the calibration process has an error codeword. The output code words generated during the calibration process of the state machine 43 and the error code words corresponding to the output codes enter the calibration parameter obtaining circuit 44, and are output as calibration parameters after passing through the combinational logic of the calibration parameter obtaining circuit and the logic corresponding to the error calculation formula. Accordingly, when the calibration of the analog-to-digital converter is completed and a control signal indicating the completion of the calibration is sent to the weight update control circuit 46, the calibration parameter obtaining circuit 44 synchronously sends the calibration parameters registered in the second register 45 to the weight update control circuit 46. Finally, the calibration weight control circuit 46 sends the calibration parameter to the circuit to be updated to update the capacitance parameter of the circuit.
Further, in order to enable the second register 45 to register the calibration parameters in different calibration modes, the second register 45 is set as a combination register.
In an embodiment of the present invention, the calibration module may further include a frequency detection circuit 47 connected to the calibration trigger circuit 41, for detecting the frequency of the analog-to-digital converter by being connected to the main circuit of the analog-to-digital converter, and transmitting the frequency to the first register 42 through the calibration trigger circuit 41 to adjust the calibration configuration in the first register 42.
Specifically, the relationship between the frequency of the analog-to-digital converter and the calibration mode may be set in the first register 42 in advance. When the calibration trigger circuit 41 detects the distortion signal, the frequency value at this time is obtained from the frequency detection circuit 37, and the frequency value at this time is transmitted to the first register 42. At this time, the first register 42 sets the calibration configuration to a specific code value corresponding to the calibration mode according to the preset relationship and the frequency value at this time, so that the state machine can obtain the calibration configuration and perform calibration according to the calibration mode corresponding to the calibration configuration.
For example, after determining all the supported calibration patterns of the analog-to-digital converter at this time, a plurality of calibration patterns may be combined to generate a plurality of calibration paths, and a trigger condition may be set for each calibration path. Further, the frequency of the adc can be divided into three types, i.e. high frequency, middle frequency and low frequency, and if the low frequency is detected at this time, corresponding to the first calibration path, the first register 42 will autonomously adjust the calibration configuration to the trigger condition code value corresponding to the first calibration path. It should be noted that the division of the frequency is only an exemplary description, and in practical applications, the frequency may be divided by different range intervals, so that the first register 42 adjusts the code value of the calibration configuration according to the different range intervals.
Here, it should be noted that: the description of the embodiment of the calibration module 40 in fig. 4 is similar to the description of the embodiment of the method shown in fig. 1, and has similar beneficial effects to the embodiment of the method shown in fig. 1, and therefore, the description thereof is omitted. For technical details that are not disclosed in the embodiment of the calibration module of the present invention, please refer to the description of the method embodiment shown in fig. 1 for understanding, and therefore, for brevity, will not be described again.
In a similar way, based on the calibration method based on the analog-to-digital converter, an embodiment of the present invention further provides an analog-to-digital converter, which includes the calibration module and is configured to execute the calibration method.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or in other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.
Alternatively, the integrated unit of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention or portions thereof contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A method of calibrating an analog-to-digital converter, the method comprising:
acquiring a calibration configuration, wherein the calibration configuration is used for showing that a calibration mode adopted in the current calibration process is at least one of a plurality of calibration modes supported by an analog-to-digital converter;
calibrating the analog-to-digital converter according to the calibration configuration to generate calibration parameters;
determining a comparison result of the calibration parameter and an expected parameter;
judging whether to calibrate again according to the comparison result;
updating the parameters of the capacitor array of the analog-to-digital converter according to the current calibration parameters under the condition that the comparison result meets the condition of finishing calibration;
the analog-to-digital converter is an analog-to-digital converter combining a successive approximation register and a slope dual architecture; accordingly, the method can be used for solving the problems that,
the calibration mode includes at least one of: static comparator calibration, dynamic comparator calibration, and capacitance weight calibration.
2. The method of claim 1, the obtaining a calibration configuration, comprising one of:
acquiring calibration configuration under the condition that the analog-to-digital converter is powered on and started;
in the case where the analog-to-digital converter detects a distorted signal, a calibration configuration is obtained.
3. The method of claim 2, wherein the analog-to-digital converter detects a distorted signal by:
collecting the current clock period of the analog-to-digital converter;
determining an actual deviation of the current clock period from a reference clock period;
and determining that the analog-to-digital converter detects a distortion signal when the actual deviation exceeds a preset deviation value.
4. The method of claim 3, wherein obtaining a calibration configuration in the event that the analog-to-digital converter detects a distorted signal comprises:
detecting a sampling frequency of the analog-to-digital converter in case the analog-to-digital converter detects a distorted signal;
obtaining the calibration configuration generated by the analog-to-digital converter according to the sampling frequency.
5. The method according to claim 1, wherein said determining whether to perform calibration again according to the comparison result comprises:
judging whether the comparison result meets a preset range or not;
judging that the calibration is finished under the condition that the comparison result is within a preset range;
and under the condition that the comparison result exceeds a preset range, calibrating the analog-to-digital converter again until the comparison result accords with the preset range, and judging to finish calibration.
6. The method according to claim 5, wherein said determining whether to perform calibration again according to the comparison result comprises:
and judging to finish the calibration under the condition that the comparison result exceeds the preset range but the calibration times are more than the set cycle times.
7. A calibration module for calibrating an analog-to-digital converter, the calibration module comprising:
the calibration trigger circuit is used for detecting a distortion signal of the analog-to-digital converter and sending a calibration trigger signal to the state machine in response to the distortion signal;
a first register coupled to the state machine for sending the calibration configuration to the state machine;
the state machine is connected with the first register and the calibration parameter acquisition circuit and is used for acquiring calibration configuration from the state machine, calibrating the analog-to-digital converter according to the calibration configuration and obtaining calibration output; the state machine is also connected with the weight updating control circuit and used for sending a control signal to the weight updating control circuit under the condition of finishing calibration, wherein the control signal is used for showing the end of calibration;
the calibration parameter acquisition circuit is connected with the state machine and used for acquiring calibration output from the state machine and generating calibration parameters according to the calibration output;
the second register is connected with the calibration parameter acquisition circuit and the weight updating control circuit and is used for registering the calibration parameters and sending the calibration parameters to the weight updating control circuit;
the weight updating control circuit is connected with the circuit needing to be updated of the analog-to-digital converter and used for updating the circuit needing to be updated according to the calibration parameters;
the calibration configuration is used to show that a calibration mode adopted in the calibration process is at least one of a plurality of calibration modes supported by the analog-to-digital converter, and the calibration mode includes at least one of the following: static comparator calibration, dynamic comparator calibration, and capacitance weight calibration.
8. The calibration module of claim 7, further comprising:
and the frequency detection circuit is connected with the calibration trigger circuit and used for detecting the sampling frequency of the analog-to-digital converter and sending the sampling frequency to the first register through the calibration trigger circuit so that the first register determines the calibration configuration according to the sampling frequency.
9. An analog-to-digital converter, characterized in that it comprises a calibration module for calibrating an analog-to-digital converter according to claim 7 or 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111582541.6A CN114244359B (en) | 2021-12-22 | 2021-12-22 | Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111582541.6A CN114244359B (en) | 2021-12-22 | 2021-12-22 | Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114244359A CN114244359A (en) | 2022-03-25 |
| CN114244359B true CN114244359B (en) | 2023-01-10 |
Family
ID=80761464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111582541.6A Active CN114244359B (en) | 2021-12-22 | 2021-12-22 | Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114244359B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054527A (en) * | 1983-09-05 | 1985-03-29 | Omron Tateisi Electronics Co | A/d converting device |
| CN103888141A (en) * | 2014-04-09 | 2014-06-25 | 华为技术有限公司 | Assembly line successive approximation type analog-digital converter self-calibration method and device |
| CN104702280A (en) * | 2015-02-02 | 2015-06-10 | 苏州迅芯微电子有限公司 | Foreground automatic calibration system for time interleaving ADC (analog to digital converter) |
| US10454492B1 (en) * | 2018-06-19 | 2019-10-22 | Analog Devices, Inc. | Analog-to-digital converter speed calibration techniques |
| CN110768671A (en) * | 2019-10-17 | 2020-02-07 | 西安交通大学 | Off-chip calibration method and system for successive approximation type analog-to-digital converter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110768670B (en) * | 2019-09-26 | 2021-05-28 | 西安交通大学 | Digital piecewise linear calibration method for successive approximation type analog-to-digital converter |
-
2021
- 2021-12-22 CN CN202111582541.6A patent/CN114244359B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054527A (en) * | 1983-09-05 | 1985-03-29 | Omron Tateisi Electronics Co | A/d converting device |
| CN103888141A (en) * | 2014-04-09 | 2014-06-25 | 华为技术有限公司 | Assembly line successive approximation type analog-digital converter self-calibration method and device |
| CN104702280A (en) * | 2015-02-02 | 2015-06-10 | 苏州迅芯微电子有限公司 | Foreground automatic calibration system for time interleaving ADC (analog to digital converter) |
| US10454492B1 (en) * | 2018-06-19 | 2019-10-22 | Analog Devices, Inc. | Analog-to-digital converter speed calibration techniques |
| CN110768671A (en) * | 2019-10-17 | 2020-02-07 | 西安交通大学 | Off-chip calibration method and system for successive approximation type analog-to-digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114244359A (en) | 2022-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8111178B2 (en) | Calibration method and related calibration apparatus for capacitor array | |
| US9106246B2 (en) | Successive approximation register analog-to-digital converter and associated control method | |
| US8665125B2 (en) | Electronic device and method for measuring differential non-linearity (DNL) of an SAR ADC | |
| US7924209B2 (en) | Self-calibration circuit and method for capacitors | |
| US7675452B2 (en) | Successive approximation register analog to digital converter with improved immunity to time varying noise | |
| KR20180028891A (en) | System and method of calibrating | |
| US7443323B2 (en) | Calibrating a digital-to-analog converter | |
| US10862498B1 (en) | Calibration circuit and calibration method for ADC | |
| US10069506B2 (en) | Calibration circuit and calibration method for DAC | |
| KR101293057B1 (en) | Comparator, analog digital converter, ramp signal slope calibration circuit, cmos image sensor using the same and ramp signal slope calibration method | |
| TWI572144B (en) | Method and digital correction circuit for adaptive regulating coding mode | |
| CN106253901B (en) | Analog-digital conversion device and related calibration method and calibration module | |
| US9124288B2 (en) | Semiconductor device | |
| US20150295586A1 (en) | Analog-digital converter | |
| JP6509041B2 (en) | Method and circuit for bandwidth mismatch estimation in A / D converter | |
| CN114244359B (en) | Calibration method and calibration module of analog-to-digital converter and analog-to-digital converter | |
| US10700694B2 (en) | Calibration method and related calibration system | |
| CN105245227A (en) | Digital calibration method for image sensor column-level cycle ADC (Analog to Digital Converter) | |
| US20160042203A1 (en) | Charge measurement | |
| CN116155285A (en) | Digital-to-analog converter calibration method based on digital domain coding remapping | |
| US8264389B2 (en) | Successive approximation analog-to-digital converter | |
| US11239850B2 (en) | Leakage compensation for a successive approximation analog-to-digital converter | |
| US12028086B2 (en) | Self calibrating digital-to-analog converter | |
| WO2024139135A1 (en) | Calibration method and apparatus for channel gain mismatch of analog-to-digital converter (adc), and circuit | |
| WO2021120037A1 (en) | Successive approximation register analog-to-digital converter and mismatch voltage detection method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |