CN114242881A - Cascade type plane thermoelectric thin film structure for cooling chip hot spots - Google Patents
Cascade type plane thermoelectric thin film structure for cooling chip hot spots Download PDFInfo
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- H10N19/00—Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
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- H01L23/38—Cooling arrangements using the Peltier effect
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Abstract
The invention discloses a cascade plane thermoelectric film structure for cooling chip hot spots, which is a plane and comprises: the thermoelectric module comprises a substrate, a bottom electrode and a cascade thermocouple layer, wherein round holes are formed in the centers of the substrate, the bottom electrode and the cascade thermocouple layer, the cascade thermocouple layer further comprises a plurality of stages of thermocouple pairs and a plurality of cascade heat conducting rings, the multistage thermocouple pairs are sequentially arranged from the center of a circle along the radial direction according to the heat transfer direction, and the cascade heat conducting rings are connected with the thermocouple pairs at all stages. The invention provides a cascade type plane thermoelectric thin film structure for cooling chip hot spots, which is characterized in that a plurality of cascade thermoelectric couple pairs are sequentially arranged according to the heat transfer direction of the chip hot spots, the refrigerating capacity of a plane thermoelectric thin film is improved by reasonably arranging a heat dissipation path of the thermoelectric thin film structure, and the whole structure can adopt a mature micro-processing technology without increasing the manufacturing difficulty of the structure.
Description
Technical Field
The invention belongs to the technical field of electronic device heat management, and particularly relates to a cascade type plane thermoelectric thin film structure for cooling a chip hot spot.
Background
With the continuous improvement of the performance and the integration of electronic chips and the continuous increase of the power density of chips, the local heat dissipation density of chips is also increased, that is, chip hot spots are generated, and the safe operation and the service life of the chips are seriously affected by the hot spots, so that the heat dissipation and cooling of the chip hot spots are necessary. Thermoelectric refrigerating devices (TEC) are attractive chip solid-state refrigerating devices, local heat dissipation is carried out on the refrigerated devices by mainly utilizing the Peltier effect, the current miniaturization design is an important direction of the thermoelectric refrigerating devices, and thermoelectric thin films are typical miniaturized devices of the thermoelectric refrigerating devices.
The thermoelectric film is similar to a macroscopic thermoelectric refrigeration device, is mainly integrated by a single micro-scale thermoelectric couple pair, the refrigeration performance of the thermoelectric film depends on the performance of a thermoelectric material, a cold-hot end contact resistance (thermal) and a film structure, and the thermoelectric film has wide application prospects in the fields of micro power supplies, local cooling, high-precision temperature control and the like.
Thermoelectric films can be classified into cross-plane (vertical type) structures and in-plane (planar type) structures according to the relationship between the direction of the temperature gradient and the plane of the substrate. The vertical thermoelectric film structure has a complex process, the establishment of temperature difference depends heavily on the thickness of the thermoelectric unit, and when the vertical thermoelectric film structure is applied to chip hot spot cooling, the unit refrigeration density is not high, so that effective local cooling cannot be formed, and cold energy waste is easily caused; the planar thermoelectric thin film structure can be completed by using the traditional silicon planar processing technology, but has two significant disadvantages: firstly, the temperature gradient direction is parallel to the substrate, the thermoelectric cooling efficiency is inevitably reduced by heat conduction along the substrate, secondly, the integration level of the plane type thin film structure is not high, higher cooling temperature difference is difficult to obtain, and the application range of the plane type thermoelectric thin film is greatly limited, although some mechanisms also carry out related research on the plane type thermoelectric thin film structure at present, for example, the national seoul university reports a plane radial thermoelectric thin film structure, but the maximum cooling temperature difference of less than 3 ℃ can be realized; the hong Kong scientific and technical university reports a SiGe cross-shaped plane thermoelectric film structure, the maximum refrigerating temperature difference of a single-stage thermoelectric film reaches 10.3 ℃, and the maximum refrigerating temperature difference can reach 11.2 ℃ in a mode of cascading two-stage thermoelectric films; the invention provides a plane thermoelectric film structure, which is verified by Wuhan theory of technology university through a finite element simulation method, the maximum refrigeration temperature difference reaches 8.2 ℃, but the existing thermoelectric film structure has the defects of low refrigeration temperature difference and poor refrigeration effect, can not meet the requirement of future chip hot spot cooling, and the structure and process complexity of the existing cascade thermoelectric film is usually high, so that a good heat transfer path is not formed, the heat at the hot end is not easy to dissipate, and larger refrigeration temperature difference and lower refrigeration temperature can not be obtained.
Disclosure of Invention
In view of the above, the present invention provides a cascaded planar thermoelectric thin film structure for cooling a chip hot spot, which can greatly reduce the temperature of the chip hot spot and make the temperature distribution of the chip more uniform.
In order to achieve the purpose, the invention adopts the following technical scheme: a cascaded, planar thermoelectric thin film structure for chip hot spot cooling, the thermoelectric thin film structure being planar, comprising: the device comprises a substrate, a bottom electrode and a cascade thermocouple layer, wherein round holes are formed in the centers of the substrate, the bottom electrode and the cascade thermocouple layer;
the substrate is an electric insulating substrate, and the thermal conductivity is less than 1.5W/(m.K);
the bottom electrode is positioned above the substrate;
the cascade thermocouple layer is located on the upper layer of the bottom electrode and comprises: the thermoelectric module comprises a plurality of stages of thermocouple pairs and a plurality of cascade heat-conducting rings, wherein the multistage thermocouple pairs are sequentially arranged along the radial direction from the circle center; each stage of the cascade thermocouple layer comprises a plurality of pairs of thermocouple pairs, and the hot ends of the thermocouple pairs of the previous stage and the cold ends of the thermocouple pairs of the next stage correspond one to one in the two adjacent thermocouple pairs;
each stage of thermocouple pair is composed of N-type fan-shaped thermocouples or P-type fan-shaped thermocouples alternately, and two adjacent stages of thermocouple pairs are arranged, wherein the N-type fan-shaped thermocouple of the previous stage corresponds to the P-type fan-shaped thermocouple of the next stage, and the P-type fan-shaped thermocouple of the previous stage corresponds to the N-type fan-shaped thermocouple of the next stage;
the cascade heat conduction ring is connected with the hot ends of all thermocouple pairs at the upper stage and the cold ends of all thermocouple pairs at the lower stage.
Preferably, the cascade thermally conductive ring is electrically insulating and has a thermal conductivity greater than 25W/(m · K).
Preferably, the cascade heat conduction ring is made of the following materials: any one of aluminum nitride, boron nitride, beryllium nitride, silicon nitride, aluminum oxide, gallium oxide, zinc selenide, tin oxide, tungsten oxide, chromium silicide, nickel oxide, indium gallium zinc oxide, tin antimony oxide, tin sulfide, boron carbide, germanium sulfide, magnesium oxide, cadmium selenide, zinc sulfide, titanium dioxide, titanium nitride, scandium oxide, lead zirconate titanate, lithium nickelate, manganese zinc, lithium iron phosphate, indium oxide, scandium aluminum nitride, molybdenum disulfide, germanium antimony tellurium, erbium oxide, and yttrium oxide.
Preferably, the thermal conductivity of the bottom electrode is more than 90W/(m.K), and the material is any one of copper, aluminum, gold, silver, chromium and alloy.
Preferably, the substrate material is any one of polyimide, quartz and glass.
Preferably, the N typeThe materials of the fan-shaped thermocouple and the P-type fan-shaped thermocouple are Bi2Te3Base thermoelectric material, Sb2Te3Any one or more of a base thermoelectric material, a SiGe alloy material, a semi-Hales compound thermoelectric material, a PbTe-based thermoelectric material, a skutterudite or a filled skutterudite thermoelectric material.
The invention has the beneficial effects that: the invention provides a cascade type plane thermoelectric thin film structure for cooling chip hot spots, which improves the refrigerating capacity of the plane thermoelectric thin film through a heat dissipation path of a radial plus cascade type thermoelectric thin film structure, can improve the heat absorption area ratio through a radially designed heat dissipation structure, namely the ratio of the outer diameter to the inner diameter of a thin film unit, and guides the heat of the hot spot of a middle chip outwards to the maximum extent; the multi-couple cascade structure can reduce the resistance of the thermoelectric unit on one hand, and can more effectively transfer heat outwards and increase refrigeration temperature difference by generating multi-stage pumping suction (Peltier effect) on the other hand.
Drawings
FIG. 1 is a schematic structural diagram of a cascaded planar thermoelectric film for hot spot cooling of a chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the temperature distribution on the thermoelectric film when the cascaded planar thermoelectric film structure for cooling the hot spot of the chip is not turned on according to the embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a temperature distribution across a thermoelectric film after a cascaded planar thermoelectric film structure for cooling a hot spot of a chip according to an embodiment of the present invention is turned on;
FIG. 4 is a hot spot cooling performance calculation result of a cascaded planar thermoelectric thin film structure for hot spot cooling of a chip according to an embodiment of the present invention;
in the figure: 1. the substrate 2, the bottom electrode 3, the cascade thermocouple layer 4, the chip hot spot 31, the N-type fan-shaped thermocouple 32, the P-type fan-shaped thermocouple 33 and the cascade heat-conducting ring.
Detailed Description
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
The invention is described in detail below with reference to the figures and specific embodiments.
As an embodiment, a cascaded planar thermoelectric thin film structure for chip hot spot cooling as shown in fig. 1, the thermoelectric thin film structure being planar, includes: the substrate 1, the bottom electrode 2 and the cascade thermocouple layer 3 are provided with round holes in the centers, and when chip hot spots are cooled, the round holes are aligned to the chip hot spots.
The substrate 1 is used as a support structure for the growth of the thermoelectric thin film, has electrical insulation and low thermal conductivity to prevent heat from flowing back from the hot end to the cold end so as to reduce the refrigeration efficiency of the thermoelectric thin film, and is generally made of materials with the thermal conductivity less than 1.5W/(m.K), such as polyimide, quartz, glass and the like;
the bottom electrode 2 is positioned above the substrate, is used for connecting all thermocouple pairs, is made of metal with higher thermal conductivity, the thermal conductivity of the bottom electrode 2 is more than 90W/(m.K), the metal material with high thermal conductivity can be copper, aluminum, gold, silver, chromium or alloy material, and the resistance of the thermoelectric film can be obviously reduced by adopting the metal for the bottom electrode 2;
the cascade thermocouple layer 3 is located on the upper layer of the bottom electrode 2, and includes: a plurality of stages of thermocouple pairs arranged in order in a radial direction from a center of the circle and a plurality of cascade heat-conducting rings 33 connecting the thermocouple pairs at each stage; each stage of the cascade thermocouple layer comprises a plurality of pairs of thermocouple pairs, the thermocouple pairs of two adjacent stages are arranged, the hot end of the thermocouple pair of the previous stage corresponds to the cold end of the thermocouple pair of the next stage one by one, and therefore the heat of the hot spot of the chip can be transferred from the hot spot of the chip to the outside in the radial direction through pumping. Each stage of thermocouple pairs consists of N-type sector thermocouples 31 or P-type sector thermocouples 32 alternately, and in the two adjacent stages of thermocouple pairs, the N-type sector thermocouple of the previous stage corresponds to the P-type sector thermocouple of the next stage, and the P-type sector thermocouple of the previous stage corresponds to the N-type sector thermocouple of the next stage;
the materials of the N-type fan-shaped thermocouple and the P-type fan-shaped thermocouple are Bi2Te3Base thermoelectric material, Sb2Te3Any one or more of a base thermoelectric material, a SiGe alloy material, a half-Halles compound thermoelectric material, a PbTe thermoelectric material, a skutterudite or filled skutterudite thermoelectric material
The cascade heat-conducting ring 33 is used for connecting the hot ends of all thermocouple pairs at the upper stage and the cold ends of all thermocouple pairs at the lower stage, has the properties of electric insulation and high heat conductivity, and is made of any one of the following materials: aluminum nitride, boron nitride, beryllium nitride, silicon nitride, aluminum oxide, gallium oxide, zinc selenide, tin oxide, tungsten oxide, chromium silicide, nickel oxide, indium gallium zinc oxide, tin antimony oxide, tin sulfide, boron carbide, germanium sulfide, magnesium oxide, cadmium selenide, zinc sulfide, titanium dioxide, titanium nitride, scandium oxide, lead zirconate titanate, lithium nickelate, manganese zinc, lithium iron phosphate, indium oxide, scandium aluminum nitride, molybdenum disulfide, germanium antimony tellurium, erbium oxide, and yttrium oxide.
The thermoelectric thin film structure in the embodiment is utilized to carry out chip hot spot refrigeration simulation calculation, the center of the thermoelectric thin film structure is aligned to a chip hot spot 4, and a thermocouple material is set to be Bi2Te3The thermoelectric material is based, the cascade heat-conducting ring material is aluminum nitride, the substrate material is polyimide, and the hot spot heat flow density of the chip is set to be 2.2W/cm2The surface heat convection coefficient of the thermoelectric film is set to be 10W/(m)2C.g. to be prepared into a preparation. When the thermoelectric thin film is not opened, the temperature of the chip hot spot is the highest, which is about 91 ℃, at this time, heat is transferred radially outward from the chip hot spot, but due to poor heat dissipation performance, the heat is still concentrated in an area near the chip hot spot, so that the temperature of the area is higher, and the local temperature gradient is larger, and fig. 2 is a calculation result of the temperature distribution of the thermoelectric thin film when the thermoelectric thin film is not opened in the embodiment of the present invention. When the thermoelectric film is turned onThe temperature distribution result is shown in fig. 3, and it can be seen from the graph that when the temperature of the hot spot of the chip is about 57 ℃ after the thermoelectric film is turned on, the reduction range reaches 34 ℃, and the temperature distribution of the area near the hot spot of the chip is more uniform.
FIG. 4 shows the calculation results of the hot spot cooling performance of the thermoelectric film, and it can be seen from the figure that, under different input current conditions, the thermoelectric film has an optimal performance working point, and when the heat flow density of the hot spot of the chip is 1.1W/cm2When the thermoelectric film is not started, the cooling amplitude of a hot spot of the chip exceeds 22 ℃; when the heat flow density of the hot spot of the chip is 2.2W/cm2In the process, the optimal working current of the thermoelectric film is 25mA, and compared with the situation that the thermoelectric film is not opened, the cooling amplitude of a hot spot of the chip exceeds 34 ℃. Therefore, the cascade plane radial thermoelectric thin film structure provided by the invention can greatly reduce the hot spot temperature of the chip and enable the temperature distribution of the chip to be more uniform.
Claims (6)
1. A cascaded planar thermoelectric thin film structure for hot spot cooling of a chip, the thermoelectric thin film structure being planar, comprising: the device comprises a substrate, a bottom electrode and a cascade thermocouple layer, wherein round holes are formed in the centers of the substrate, the bottom electrode and the cascade thermocouple layer;
the substrate is an electric insulating substrate, and the thermal conductivity is less than 1.5W/(m.K);
the bottom electrode is positioned above the substrate;
the cascade thermocouple layer is located on the upper layer of the bottom electrode and comprises: the multistage thermocouple pairs and the cascade heat-conducting rings are sequentially arranged along the radial direction from the circle center according to the heat transfer direction; each stage of the cascade thermocouple layer comprises a plurality of pairs of thermocouple pairs, and the hot ends of the thermocouple pairs of the previous stage correspond to the cold ends of the thermocouple pairs of the next stage one by one in the two adjacent stages of thermocouple pairs;
each stage of thermocouple pair is composed of N-type fan-shaped thermocouples or P-type fan-shaped thermocouples alternately, and two adjacent stages of thermocouple pairs are arranged, wherein the N-type fan-shaped thermocouple of the previous stage corresponds to the P-type fan-shaped thermocouple of the next stage, and the P-type fan-shaped thermocouple of the previous stage corresponds to the N-type fan-shaped thermocouple of the next stage;
the cascade heat conduction ring is connected with the hot ends of all thermocouple pairs at the upper stage and the cold ends of all thermocouple pairs at the lower stage.
2. The cascaded planar thermoelectric thin film structure for chip hot spot cooling of claim 1, wherein the cascaded thermally conductive rings are electrically insulating and have a thermal conductivity greater than 25W/(m-K).
3. The cascaded planar thermoelectric thin film structure for chip hot spot cooling of claim 4, wherein the cascaded thermally conductive rings are made of: any one of aluminum nitride, boron nitride, beryllium nitride, silicon nitride, aluminum oxide, gallium oxide, zinc selenide, tin oxide, tungsten oxide, chromium silicide, nickel oxide, indium gallium zinc oxide, tin antimony oxide, tin sulfide, boron carbide, germanium sulfide, magnesium oxide, cadmium selenide, zinc sulfide, titanium dioxide, titanium nitride, scandium oxide, lead zirconate titanate, lithium nickelate, manganese zinc, lithium iron phosphate, indium oxide, scandium aluminum nitride, molybdenum disulfide, germanium antimony tellurium, erbium oxide, and yttrium oxide.
4. The structure of claim 1, wherein the bottom electrode has a thermal conductivity greater than 90W/(m-K) and is made of any one of Cu, Al, Au, Ag, Cr and alloy.
5. The structure of claim 1, wherein the substrate material is any one of polyimide, quartz and glass.
6. The cascaded planar thermoelectric thin film structure for chip hot spot cooling of claim 3, wherein the N-type fan-shaped thermocouple and the P-type fan-shaped thermocouple are both Bi2Te3Base thermoelectric material, Sb2Te3Any one or more of a base thermoelectric material, a SiGe alloy material, a semi-Hales compound thermoelectric material, a PbTe-based thermoelectric material, a skutterudite or a filled skutterudite thermoelectric material.
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