CN114242826A - Single photon avalanche diode and forming method thereof - Google Patents
Single photon avalanche diode and forming method thereof Download PDFInfo
- Publication number
- CN114242826A CN114242826A CN202111476922.6A CN202111476922A CN114242826A CN 114242826 A CN114242826 A CN 114242826A CN 202111476922 A CN202111476922 A CN 202111476922A CN 114242826 A CN114242826 A CN 114242826A
- Authority
- CN
- China
- Prior art keywords
- region
- substrate
- well region
- ion implantation
- single photon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 153
- 150000002500 ions Chemical class 0.000 claims abstract description 22
- 238000002513 implantation Methods 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims description 92
- 238000002955 isolation Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 2
- 239000000969 carrier Substances 0.000 abstract description 12
- 238000001514 detection method Methods 0.000 abstract description 11
- 230000001965 increasing effect Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000002596 correlated effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Light Receiving Elements (AREA)
Abstract
The invention relates to a single photon avalanche diode and a forming method thereof. In the single photon avalanche diode, the first well region and the surrounding substrate region constitute a diode structure, and, a depletion thickness adjusting region isolated from the first well region is also formed in the substrate, the depletion thickness adjusting region having the same doping type as the first well region, and the depth in the substrate is greater than the maximum implantation depth of the doped ions of the first well region in the substrate, when the single photon avalanche diode works, the diode structure is reversely biased, the minority carriers on one side of the first well region drift downwards, the majority carriers in the depletion thickness adjusting region drift towards the first well region along with the drift motion of the minority carriers below the first well region, the thickness of the depletion layer is increased, the photon detection efficiency of the device is enhanced, and the influence on the electrical performance of the single photon avalanche diode is small.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a single photon avalanche diode and a forming method thereof.
Background
A single Photon Avalanche diode, abbreviated as spad (single Photon Avalanche diode), is a solid-state photodetector that achieves photodetection based on a breakdown region where a reverse bias voltage exceeds a pn junction. In a single photon avalanche diode, the pn junction is reverse biased at a voltage above the breakdown voltage, and an avalanche current is generated by the internal photoelectric effect (the emission of electrons or another carrier when a material is struck by a photon). Very low signal intensities, e.g. down to single photon levels, can be detected with single photon avalanche diodes. The single photon detector based on the single photon avalanche diode can be used in a highly sensitive photon capturing environment, and has wide application in the fields of fluorescence lifetime imaging, 3D imaging and the like.
Photon detection efficiency is an important parameter for judging the performance of the single photon avalanche diode device, and the higher the photon detection efficiency is, the better the performance of the device is. Photon detection efficiency and outside quantum efficiency are relevant with avalanche emergence probability, under certain operating condition (reverse bias voltage, temperature etc.), photon detection efficiency is positively correlated with outside quantum efficiency, and outside quantum efficiency is positively correlated with the diffusion length of minority carrier (be minority carrier), and the diffusion length of minority carrier is the thickness of depletion layer, therefore, through the thickness that increases the depletion layer, the probability that the photon is absorbed at the depletion layer increases, can improve single photon avalanche diode's photon detection efficiency effectively, thereby promote the device performance.
Currently, a single photon avalanche diode generally adopts an N Well (NW) formed in a p-type semiconductor substrate to construct a doped region of a diode structure, a depletion layer of the diode structure can be increased in thickness by reducing ion implantation concentration in the N well or the substrate, but the electric performance of the single photon avalanche diode is affected (for example, breakdown voltage is increased) by reducing the ion implantation concentration in the N well or the substrate.
Therefore, it is desirable to provide a more efficient method for increasing the thickness of the depletion layer to improve the device performance of the single photon avalanche diode.
Disclosure of Invention
The invention provides a single photon avalanche diode, which can obtain larger depletion layer thickness under the condition of not changing the ion doping concentration of a diode structure, so that the photon detection efficiency of a device is higher. The invention further provides a forming method of the single photon avalanche diode.
In one aspect, the present invention provides a single photon avalanche diode comprising:
the diode structure comprises a substrate and a first well region extending from the upper surface of the substrate to the inside of the substrate, wherein the upper surface and the lower surface of the substrate are opposite surfaces, the doping type of the substrate is opposite to that of the first well region, and the first well region and the surrounding substrate region form a diode structure; and the number of the first and second groups,
and the depletion thickness adjusting region is formed in the substrate and has a depth in the substrate greater than the maximum implantation depth of the doped ions of the first well region in the substrate, and the depletion thickness adjusting region has the same doping type as the first well region and is isolated from the first well region by the substrate.
Optionally, an orthographic projection of the depletion thickness adjusting region on the upper surface of the substrate has an outer contour and an inner contour, an orthographic projection of a doped region of the depletion thickness adjusting region on the upper surface of the substrate is between the outer contour and the inner contour of the orthographic projection of the depletion thickness adjusting region on the upper surface of the substrate, and an orthographic projection outer contour of the first well region on the upper surface of the substrate is between the orthographic projection outer contour and the inner contour of the depletion thickness adjusting region; the minimum lateral dimension of the orthographic projection inner contour of the depletion thickness adjusting region is larger than the diffusion distance of the doping ions in the depletion thickness adjusting region.
Optionally, the single photon avalanche diode further includes a second well region, the second well region and the substrate have the same doping type, and the second well region and the first well region are adjacent to each other on a side of the first well region away from the upper surface of the substrate to form a diode structure, an orthographic projection of the first well region on the upper surface of the substrate covers an orthographic projection of the second well region on the upper surface of the substrate, and the depletion thickness adjusting region and the second well region are isolated by the substrate.
Optionally, an orthographic projection outer contour of the second well region on the upper surface of the substrate is located in an orthographic projection inner contour of the depletion thickness adjusting region on the upper surface of the substrate.
Optionally, the orthographic projection outer contour and the orthographic projection inner contour of the depletion thickness adjusting region on the upper surface of the substrate are both circular or polygonal.
Optionally, a longitudinal vertical distance between the depletion thickness adjusting region and the lower surface of the first well region is 0.5 μm to 3 μm.
Optionally, the multi-sub doping concentration of the depletion thickness adjusting region is smaller than that of the first well region.
Optionally, the substrate is doped p-type, and the first well region is doped n-type.
In one aspect, the present invention provides a method for forming a single photon avalanche diode, which is used for forming the single photon avalanche diode described above, and the method includes:
providing a substrate, wherein an isolation structure and an active region defined by the isolation structure are formed in the substrate, and the active region has a first doping type;
performing ion implantation of a second doping type, and forming a first ion implantation area in a set depth range of the active area, wherein the second doping type is opposite to the first doping type;
performing ion implantation of a second doping type again, and forming a second ion implantation region in the active region, wherein the second ion implantation region is shallower than the first ion implantation region and is isolated from the first ion implantation region by the substrate, and the second ion implantation region extends from the inside of the active region to the upper surface of the substrate; and the number of the first and second groups,
and performing thermal annealing to activate and stabilize ions of the first ion implantation area and the second ion implantation area, wherein the depletion thickness adjusting area is obtained from the first ion implantation area, and the first well area is obtained from the second ion implantation area.
Optionally, after forming the first ion implantation region and before forming the second ion implantation region, the method for forming the single photon avalanche diode further includes: and performing ion implantation of a first doping type, forming a third ion implantation area in the active area, wherein the third ion implantation area is shallower than the first ion implantation area, the maximum implantation depth of the third ion implantation area is greater than that of the second ion implantation area, the third ion implantation area is used for obtaining a second well region after the thermal annealing is performed, the second well region is positioned on one side of the first well region, which is far away from the upper surface of the substrate, and the second well region is adjacent to the first well region to form a diode structure.
In the single photon avalanche diode provided by the invention, a first well region and a surrounding substrate region form a diode structure, a depletion thickness adjusting region isolated from the first well region is further formed in the substrate, the doping type of the depletion thickness adjusting region is the same as that of the first well region, the depth in the substrate is larger than the maximum injection depth of doping ions of the first well region in the substrate, when the single photon avalanche diode works, the diode structure is reversely biased, the built-in electric field of a depletion layer is enhanced, namely the minority carrier drift motion is enhanced, minority carriers (such as holes) of the depletion layer on one side of the first well region drift downwards, minority carriers (such as electrons) of the depletion layer on the other side drift towards the first well region, and the majority carriers in the depletion thickness adjusting region drift towards the first well region along with the drift motion of the minority carriers below the first well region under the reverse bias action, until the strength of the external electric field is equal to that of the built-in electric field, compared with the condition that the depletion thickness adjusting region is not arranged, the arrangement of the depletion thickness adjusting region increases the charge quantity for constructing the built-in electric field, so that when the strength of the external electric field is equal to that of the built-in electric field, the thickness of a depletion layer is increased, the photon detection efficiency of the device is enhanced, and the single photon avalanche diode does not need to adjust the ion doping concentration of the first well region and the whole substrate, and has small influence on the electrical performance of the single photon avalanche diode, such as breakdown voltage. The method for forming the single-photon avalanche diode can be used for manufacturing the single-photon avalanche diode.
Drawings
Figure 1 is a schematic cross-sectional view of a single photon avalanche diode in accordance with one embodiment of the present invention.
Figure 2 is a schematic cross-sectional view of a single photon avalanche diode in accordance with another embodiment of the present invention.
Figure 3 is a schematic plan view of the single photon avalanche diode shown in figure 2.
Fig. 4 is a simulation result of a depletion layer of the diode structure shown in fig. 2 when the depletion thickness adjusting region is not provided and when the depletion thickness adjusting region is provided.
Figure 5 is a flow chart illustrating a method of forming a single photon avalanche diode according to an embodiment of the invention.
Description of reference numerals:
10. 20-single photon avalanche diode; 100-a substrate; 101-an isolation structure; 110-a first well region; 120-depletion thickness adjustment zone; 130-second well region.
Detailed Description
The single photon avalanche diode and the forming method thereof of the present invention are further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be understood that the drawings in the specification are in simplified form and are not to be taken in a precise scale, for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
It is noted that the terms "first," "second," and the like, hereinafter are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if a method described herein comprises a series of steps, and the order in which these steps are presented herein is not necessarily the only order in which these steps are performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "at … …" can also include "at … …" and other orientational relationships. Unless otherwise specified, identical functional structures are provided with the same reference numerals.
Under certain operating conditions (reverse bias voltage, temperature, etc.), the relationship between the external quantum efficiency (expressed as η (λ)) of the single photon avalanche diode device and the thickness of the depletion layer can be expressed by the following relation:
η(λ)＝1-e-α(λ)Wwhere W is the depletion layer thickness, α (λ) is the absorption coefficient of the substrate material (e.g., silicon), and λ is the wavelength of the incident light.
As can be seen from this relation, the external quantum efficiency η (λ) of the single photon avalanche diode device is positively correlated with the depletion layer thickness W, that is, the larger the depletion layer thickness W, the higher the external quantum efficiency η (λ) is. In addition, since the photon detection efficiency of the single photon avalanche diode device is positively correlated with the external quantum efficiency η (λ), the larger the depletion layer thickness W is, the higher the photon detection efficiency is, which indicates that increasing the depletion layer thickness on the basis of not affecting the electrical performance is helpful to improve the device performance of the single photon avalanche diode.
Figure 1 is a schematic cross-sectional view of a single photon avalanche diode in accordance with one embodiment of the present invention. Referring to fig. 1, an embodiment of the invention relates to a single photon avalanche diode 10, the single photon avalanche diode 10 comprising a substrate 100 and a first well region 110 and a depletion thickness adjusting region 120 formed in the substrate 100. The first well region 110 extends from the upper surface of the substrate 100 to the inside of the substrate 100 (the side surface of the first well region 110 extending from the surface of the substrate 100 to the inside of the substrate 100 is the upper surface of the substrate 100), and the upper surface and the lower surface of the substrate 100 are opposite surfaces. The doping type of the substrate 100 is opposite to that of the first well region 110, and the first well region 110 and the surrounding substrate region form a diode structure. The depletion thickness adjusting region 120 is formed in the substrate 100, and the depth in the substrate 100 (which can be understood as the depth of the substrate 100 of the side surface of the depletion thickness adjusting region 120 facing the upper surface of the substrate 100) is greater than the maximum implantation depth of the doped ions of the first well region 110 in the substrate 100, and the depletion thickness adjusting region 120 is the same as the doping type of the first well region 110 and is isolated by the substrate 100, so that the depletion thickness adjusting region 120 is entirely located in the substrate region below the first well region 110.
In particular, the doping type of the substrate 100 and the first well region 110 may be selected from p-type and n-type, and the substrate 100 is, for example, p-type (for example, doped with boron B or boron difluoride BF)2) The first well 110 is, on the contrary, n-type (e.g., doped with phosphorus P or arsenic As). Therefore, in the diode structure formed by the first well region 110 and the surrounding substrate region, the first well region 110 is an n-type doped region of the diode structure, and the p-type substrate region located around the first well region 110 is a p-type doped region of the diode structure. However, the diode structure may also have the first well region as a p-type doped region and the n-type substrate region around the first well region as an n-type doped region. In the latter case, the conductivity type needs to be reversed and the bias on the diode structure adjusted appropriately for operation.
In this embodiment, the substrate 100 may include a silicon substrate and an epitaxial layer disposed on the silicon substrate. When the silicon substrate is doped p-type, the epitaxial layer has, for example, p-type doping (p-representation), and the doping concentration of p-type ions of the epitaxial layer is, for example, 5 × 1016/cm3Above to 5X 1018/cm3The following. The doping concentration of p-type ions in the epitaxial layer is lower than that of the underlying silicon substrate, for example. The first well region 110 extends, for example, from the upper surface of the substrate 100 to a certain depth within the substrate 100 (specifically, within the epitaxial layer), and both the lateral and lower surfaces of the first well region 110 are surrounded by the p-type doped substrate region.
The embodiments of the present invention mainly describe a single photon avalanche diode, and it can be understood that more than one single photon avalanche diode can be integrated on the same substrate 100, and other devices can also be formed. In order to isolate different devices integrated on the same substrate 100, as shown in fig. 1, an active region where a single photon avalanche diode is disposed may be defined by disposing an isolation structure 101 in the substrate 100, and a single photon avalanche diode may be formed in one active region defined by the isolation structure 101. The isolation structure 101 may be a Shallow Trench Isolation (STI) or a Deep Trench Isolation (DTI), preferably a deep trench isolation. The embodiments of the present invention are mainly described by taking each active region as p-type doping.
Figure 2 is a schematic cross-sectional view of a single photon avalanche diode in accordance with another embodiment of the present invention. Referring to fig. 2, a single photon avalanche diode 20 in another embodiment is different from the single photon avalanche diode 10 shown in fig. 1 in that a second well region 130 is additionally disposed in the substrate 100, the second well region 130 has the same doping type (denoted as PW) as the substrate 100, and the second well region 130 is adjacent to the first well region 110 on the side of the first well region 110 away from the upper surface of the substrate 100 to form a diode structure. In this embodiment, the orthographic projection of the first well region 110 on the upper surface of the substrate 100 covers the orthographic projection of the second well region 130 on the upper surface of the substrate 100, and the depletion thickness adjusting region 120 is isolated from the second well region 130 by the substrate 100. For example, the substrate 100 is doped p-type, the second well 130 is also doped p-type, and the doping concentration of the p-type ions in the second well 130 may be higher than that of the substrate 100. It can be seen that the second well region 130 is located within a p-doped region in the diode structure formed by the first well region 110 and the surrounding substrate region. As shown in fig. 2, a portion of the lower surface of the first well region 110, which is connected to the side edges, is not covered by the second well region 130, i.e., the second well region 130 exposes the lower corner of the first well region 110, which is arranged so that the depletion region of the diode structure diverges at the corner of the first well region 110 at the boundary of the p-type doped region, and in a direction away from the first well region 110, compared with the diode structure shown in fig. 1, the diode structure shown in fig. 2 can further define the location of reverse breakdown by the arrangement of the second well region 130. The shortest lateral vertical distance between the sides of the second well 130 and the first well 110 is about 0.1 μm to about 0.3 μm. Here, "laterally shortest vertical distance" refers to the vertical spacing, in a plane parallel to the upper surface of the substrate 100, of the rightmost side of the second well region 130 from the rightmost side of the first well region 110 in fig. 2.
In this embodiment, the depletion thickness adjusting region 120 is used to adjust the thickness of the depletion layer of the diode structure formed by the first well region 110 and the surrounding substrate region, and more specifically, the thickness of the depletion layer is increased by the single photon avalanche diode 10 or the single photon avalanche diode 20 under the same reverse bias voltage compared to the situation without the depletion thickness adjusting region 120. The depletion thickness adjusting region 120 is not an extension of the first well region 110, but is isolated from the first well region 110, as shown in fig. 1 or fig. 2, a p-type substrate region not only surrounds the first well region 110, but also surrounds the depletion thickness adjusting region 120, that is, the first well region 110 and the depletion thickness adjusting region 120 are isolated by the substrate. In the diode structure, the depletion thickness adjusting region 120 is disposed in an oppositely doped region (i.e., a p-type doped substrate region) of the first well region 110, so that when the diode structure is reverse biased, the depletion thickness adjusting region 120 is affected by the oppositely doped region to form charge drift, and more specifically, when the single photon avalanche diode is reverse biased, a majority charge in the depletion thickness adjusting region 120 drifts toward the first well region 110 along with drift motion of a minority charge under the first well region 110.
In order to facilitate multiphoton drift within the depletion thickness modulation region 120 when the single photon avalanche diode is reverse biased, it is preferable to locate the depletion thickness modulation region 120 at or near a depletion layer formed under reverse bias of the diode structure when the depletion thickness modulation region 120 is not located. For example, the vertical distance between the upper surface of the depletion thickness adjusting region 120 and the lower surface of the first well region 110 may be set to be in the range of 0.5 μm to 3 μm. For a single photon avalanche diode 20 (see fig. 2) provided with the second well region 130, the vertical distance between the upper surface of the depletion thickness adjusting region 120 and the lower surface of the second well region 130 is in the range of 0.5 μm to 2.5 μm. Here, the "longitudinal vertical distance" refers to a vertical distance between an upper surface of the depletion thickness adjusting region 120 and a lower surface of the second well region 130 in a thickness direction of the substrate 100.
In the embodiment where the second well region 130 is disposed, the depletion thickness adjusting region 120 is further isolated from the second well region 130 (by the substrate 100) to prevent multiple photons (e.g., holes) in the second well region 130 from diffusing into the depletion thickness adjusting region 120 to neutralize multiple photons (e.g., electrons) in the depletion thickness adjusting region 120, which may cause the doping concentration of the multiple photons of the depletion thickness adjusting region 120 to decrease and affect the thickness adjusting performance of the depletion layer. In addition, by isolating the depletion thickness adjusting region 120 from the second well region 130, the depletion thickness adjusting region 120, the second well region 130 and the first well region 110 can be prevented from forming a triode structure, which affects the effect of adjusting the depletion layer thickness. To this end, further, the depletion thickness adjusting region 120 is preferably disposed below the second well region 130 and near the side of the first well region 130 as viewed in the lateral direction, as shown in fig. 1 and 2.
Figure 3 is a schematic plan view of the single photon avalanche diode shown in figure 2. Referring to fig. 3 (the second well region 130 is not shown), an orthographic projection of the depletion thickness adjusting region 120 on the upper surface of the substrate 100 may overlap with an orthographic projection of the first well region 110 on the upper surface of the substrate 100 near the sides of the first well region 110. The doped ions in the depletion thickness adjusting region 120 preferably do not diffuse to the lower portion of the central region of the first well region 110, so as to avoid affecting the effect of adjusting the depletion thickness. As shown in fig. 2 and 3, the depletion thickness adjusting region 120 may extend along a circle near the side of the first well region 110, i.e., the depletion thickness adjusting region 120 surrounds a portion of the p-type region of the substrate 100. The annular depletion thickness adjusting region 120 preferably has a uniform width, which helps to make the depletion layer of the single photon avalanche diode uniform in thickness near the sides of the first well region 110.
In one embodiment, an orthographic projection of the depletion thickness adjusting region 120 on the upper surface of the substrate 100 has an outer contour and an inner contour, and an orthographic projection of a doped region of the depletion thickness adjusting region 120 on the upper surface of the substrate 100 is between the outer contour and the inner contour of the orthographic projection of the depletion thickness adjusting region 120 on the upper surface of the substrate 100. The orthographic projection outline of the first well region 110 on the upper surface of the substrate 100 (referred to as the orthographic projection outline of the first well region 110) is at least located within the orthographic projection outline of the depletion thickness adjusting region 120, and preferably, the orthographic projection outline of the first well region 110 on the upper surface of the substrate 100 is located between the orthographic projection outline and the inner outline of the depletion thickness adjusting region 120. The minimum lateral dimension of the orthographic inner contour of the depletion thickness accommodating region 120 is greater than the diffusion distance of the dopant ions in the depletion thickness accommodating region. Here, the "minimum lateral dimension of the orthographic projected inner contour of the depletion thickness modulation region 120" refers to a width at which the orthographic projected inner contour of the depletion thickness modulation region 120 is narrowest. An orthographic outer contour of the second well region 130 on the upper surface of the substrate 100 may be located within an orthographic inner contour of the depletion thickness adjusting region 120 on the upper surface of the substrate 100. Although the orthographic projection outer contour of the first well region 110 and the orthographic projection outer contour and inner contour of the depletion thickness adjusting region 120 are shown as being rectangular in fig. 3, in other embodiments, the orthographic projection outer contour of the first well region 110 and the orthographic projection outer contour and inner contour of the depletion thickness adjusting region 120 may take other shapes, such as a circle or other polygons. The orthographic projection outer contour and the orthographic projection inner contour of the depletion thickness adjusting region 120 on the upper surface of the substrate 100 can be circular or polygonal, and when the orthographic projection outer contour and the orthographic projection inner contour of the depletion thickness adjusting region 120 on the upper surface of the substrate 100 are both circular, the depletion thickness adjusting region 120 is annular.
In the single photon avalanche diode according to the embodiment of the present invention, one or more depletion thickness adjusting regions 120 as described above may be disposed according to the requirement of adjusting the depletion thickness, wherein different depletion thickness adjusting regions 120 are all located in the substrate region around the first well region 110, and the different depletion thickness adjusting regions 120 are isolated by the substrate 100 and the isolation structure 101 in the substrate 100.
Fig. 4 is a simulation result of the depletion layer of the diode structure shown in fig. 2 when the depletion thickness adjustment region is not provided and when the depletion thickness adjustment region is provided, wherein the left diagram is the case when the depletion thickness adjustment region is not provided, the right diagram is the case when the depletion thickness adjustment region is provided, the white line indicated by the arrow is the boundary of the depletion layer of the diode structure, the upper part of the embodiment is the boundary of the n-type doped region, the lower part of the embodiment is the boundary of the p-type doped region, and the dotted line crossing the left diagram and the right diagram is used for comparing the positions of the depletion layers. The results shown in fig. 4 indicate that, for the single photon avalanche diode 20 provided with the depletion thickness adjusting region 120, the thickness of the depletion layer increases in the reverse bias state, and particularly in the edge region of the first well region 110 provided with the depletion thickness adjusting region 120, the lower boundary of the depletion layer is pulled down greatly, so that the depletion thickness increases.
In the single photon avalanche diode provided by the invention, the first well region 110 formed in the substrate 100 and the surrounding substrate region form a diode structure, and a depletion thickness adjusting region 120 isolated from the first well region 110 is further formed in the substrate 100, the doping type of the depletion thickness adjusting region 120 is the same as that of the first well region 110, and the depth in the substrate 100 is greater than the maximum implantation depth of the doping ions of the first well region 110 in the substrate 100. When the single photon avalanche diode works, the diode structure is reversely biased, the built-in electric field of a depletion layer is enhanced, namely the drift motion of minority carriers is enhanced, minority carriers (such as holes) of the depletion layer on one side of the first well region 110 drift downwards, minority carriers (such as electrons) of the depletion layer on the other side of the depletion layer drift towards the first well region 110, and under the reverse bias action, the majority carriers in the depletion thickness adjusting region 120 also drift towards the first well region 110 along with the drift motion of the minority carriers below the first well region 110 until the external electric field and the strength of the built-in electric field are equal, compared with the situation that the depletion thickness adjusting region 120 is not arranged, the arrangement of the depletion thickness adjusting region 120 increases the built-in electric field, so that when the external electric field and the strength of the built-in electric field are equal, the thickness of the depletion layer is increased, which is beneficial to enhancing the photon detection efficiency of the device, in addition, the single photon avalanche diode does not need to adjust the ion doping concentration of the first well region and the whole substrate, and the influence on the electrical performance of the single photon avalanche diode, such as breakdown voltage, is small.
Embodiments of the present invention also relate to a method for forming a single photon avalanche diode, which can be used to form the single photon avalanche diode described in the above embodiments. It should be understood that the fabrication of the single photon avalanche diode described in the above embodiments is not limited to the method described below.
Figure 5 is a flow chart illustrating a method of forming a single photon avalanche diode according to an embodiment of the invention. Referring to fig. 1 to 5, in an embodiment of the present invention, a method for forming a single photon avalanche diode includes the following steps:
first step S1: providing a substrate 100, wherein an isolation structure 101 and an active region defined by the isolation structure 101 are formed in the substrate 100, and the active region has a first doping type;
second step S2: performing ion implantation of a second doping type, and forming a first ion implantation area in a set depth range of the active area, wherein the second doping type is opposite to the first doping type;
third step S3: performing ion implantation of a second doping type again, and forming a second ion implantation region in the active region, wherein the second ion implantation region is shallower than the first ion implantation region and is isolated from the first ion implantation region by the substrate 100, and the second ion implantation region extends from the inside of the active region to the upper surface of the substrate 100;
fourth step S4: and performing thermal annealing to activate and stabilize ions in the first ion implantation region and the second ion implantation region, so as to obtain the depletion thickness adjusting region 120 from the first ion implantation region and obtain the first well region 110 from the second ion implantation region.
In the first step S1, the isolation structures formed in the substrate 100 are, for example, Deep Trench Isolations (DTIs) to minimize cross-talk between single photon avalanche diodes formed in adjacent active regions. The substrate 100 has, for example, a p-type doping, i.e., the first doping type is p-type, the second doping type is n-type, and each active region is p-type doped. In other embodiments, however, the first doping type may also be n-type, so that the second doping type is p-type.
The present embodiment sequentially performs ion implantation in order from deep to shallow, and specifically forms a first ion implantation region and a second ion implantation region in the substrate 100 using the second step S2 and the third step S3, respectively. The implantation type of the first ion implantation area and the implantation type of the second ion implantation area are both a second doping type opposite to the first doping type. In the ion implantation in the second step S2 and the third step S3, a photoresist layer may be coated on the surface of the substrate 100, then the region where the second doping type is to be implanted may be defined by exposure and development, then the ion implantation process may be performed according to the depth to be implanted, and finally the photoresist layer may be removed. As an example, the first ion implantation region is a ring-shaped implantation region located in the substrate 100, and an implantation width of the ring-shaped implantation region is, for example, in a range of 0.5 μm to 1 μm. The first ion implantation region may be formed inside the substrate 100 using high-energy ion implantation. The concentration of the second doping type ions of the first ion implantation region may be less than that of the second doping type ions of the second ion implantation region, so that the n-type doping concentration of the subsequently formed depletion thickness adjusting region 120 is less than that of the first well region 110, and when the single photon avalanche diode operates, the depletion thickness adjusting region 120 has less influence on the forward electric field of the diode structure at the first well region 110.
In the fourth step S4, the ions of the first ion implantation region formed in the second step S2 and the second ion implantation region formed in the third step S3 are simultaneously activated (activated) and stabilized by thermal annealing, so that the depletion thickness adjusting region 120 is obtained from the first ion implantation region, and the first well region 110 is obtained from the second ion implantation region, so that the single photon avalanche diode 10 shown in fig. 1 can be obtained.
In one embodiment, to fabricate the single photon avalanche diode 20 shown in fig. 2, on the basis of the above steps, after the second step S2 is performed to form the first ion implantation region and before the third step S3 is performed to form the second ion implantation region, an ion implantation process of the first doping type is inserted to form a third ion implantation region in the same active region, wherein the third ion implantation region is used to form the second well region 130 after the thermal annealing of the fourth step S4. After the third ion implantation region is formed, the third step S3 is performed to form the second ion implantation region, wherein the maximum implantation depth of the third ion implantation region is greater than the maximum implantation depth of the second ion implantation region, and thus the lower surface of the third ion implantation region is lower than the lower surface of the second ion implantation region. The implantation surface of the second ion implantation region on the upper surface of the substrate 100 may cover and be larger than the implantation surface of the third ion implantation region, that is, the orthographic projection of the second ion implantation region on the upper surface of the substrate 100 covers the orthographic projection of the third ion implantation region on the upper surface of the substrate 100, so that the lower corner of the second ion implantation region is not covered by the third ion implantation region. After the fourth step S4 is completed, the second well 130 is obtained from the third ion implantation region, and the first well 110 is located above the second well 130. In addition, the implantation depth of the first ion implantation region is preferably greater than that of the third ion implantation region by more than 0.5 μm, so as to avoid the contact between the subsequently formed depletion thickness adjusting region 120 and the second well region 130.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the structure disclosed by the embodiment, and the relevant points can be referred to the structural part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A single photon avalanche diode comprising:
the diode structure comprises a substrate and a first well region extending from the upper surface of the substrate to the inside of the substrate, wherein the upper surface and the lower surface of the substrate are opposite surfaces, the doping type of the substrate is opposite to that of the first well region, and the first well region and the surrounding substrate region form a diode structure; and the number of the first and second groups,
and the depletion thickness adjusting region is formed in the substrate and has a depth in the substrate greater than the maximum implantation depth of the doped ions of the first well region in the substrate, and the depletion thickness adjusting region has the same doping type as the first well region and is isolated from the first well region by the substrate.
2. The single photon avalanche diode according to claim 1 wherein an orthographic projection of said depletion thickness accommodating region on said substrate upper surface has an outer profile and an inner profile, said depletion thickness accommodating region being between said orthographic projection of said substrate upper surface and said inner profile an orthographic projection of said depletion thickness accommodating region doped region on said substrate upper surface, said orthographic projection of said first well region on said substrate upper surface having an outer profile between said orthographic projection of said depletion thickness accommodating region and said inner profile; the minimum lateral dimension of the orthographic projection inner contour of the depletion thickness adjusting region is larger than the diffusion distance of the doping ions in the depletion thickness adjusting region.
3. The single photon avalanche diode according to claim 2 further comprising:
the doping type of the second well region is the same as that of the substrate, the second well region is adjacent to the first well region on one side, away from the upper surface of the substrate, of the first well region to form a diode structure, the orthographic projection of the first well region on the upper surface of the substrate covers the orthographic projection of the second well region on the upper surface of the substrate, and the depletion thickness adjusting region is isolated from the second well region by the substrate.
4. The single photon avalanche diode of claim 3 wherein the orthographic outer profile of said second well region over said substrate upper surface lies within the orthographic inner profile of said depletion thickness accommodating region over said substrate upper surface.
5. The single photon avalanche diode according to claim 2 wherein said depletion thickness accommodating region has an orthogonal outer profile and an orthogonal inner profile both of circular or polygonal shape on said substrate upper surface.
6. The single photon avalanche diode of claim 1 wherein said depletion thickness accommodating region is at a longitudinal vertical distance of from 0.5 μm to 3 μm from a lower surface of said first well region.
7. The single photon avalanche diode according to claim 1 wherein said depletion thickness adjusting region has a lower concentration of majority dopants than said first well region.
8. The single photon avalanche diode according to any one of the claims 1 to 7 wherein said substrate is p-type doped and said first well region is n-type doped.
9. A method of forming a single photon avalanche diode according to any one of claims 1 to 8, the method comprising:
providing a substrate, wherein an isolation structure and an active region defined by the isolation structure are formed in the substrate, and the active region has a first doping type;
performing ion implantation of a second doping type, and forming a first ion implantation area in a set depth range of the active area, wherein the second doping type is opposite to the first doping type;
performing ion implantation of a second doping type again, and forming a second ion implantation region in the active region, wherein the second ion implantation region is shallower than the first ion implantation region and is isolated from the first ion implantation region by the substrate, and the second ion implantation region extends from the inside of the active region to the upper surface of the substrate; and the number of the first and second groups,
and performing thermal annealing to activate and stabilize ions of the first ion implantation area and the second ion implantation area, wherein the depletion thickness adjusting area is obtained from the first ion implantation area, and the first well area is obtained from the second ion implantation area.
10. The method of forming of claim 9, further comprising, after forming the first ion implantation region and before forming the second ion implantation region:
and performing ion implantation of a first doping type, forming a third ion implantation area in the active area, wherein the third ion implantation area is shallower than the first ion implantation area, the maximum implantation depth of the third ion implantation area is greater than that of the second ion implantation area, the third ion implantation area is used for obtaining a second well region after the thermal annealing is performed, the second well region is positioned on one side of the first well region, which is far away from the upper surface of the substrate, and the second well region is adjacent to the first well region to form a diode structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111476922.6A CN114242826B (en) | 2021-12-02 | 2021-12-02 | Single photon avalanche diode and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111476922.6A CN114242826B (en) | 2021-12-02 | 2021-12-02 | Single photon avalanche diode and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114242826A true CN114242826A (en) | 2022-03-25 |
| CN114242826B CN114242826B (en) | 2023-12-22 |
Family
ID=80753301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111476922.6A Active CN114242826B (en) | 2021-12-02 | 2021-12-02 | Single photon avalanche diode and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114242826B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115621352A (en) * | 2022-10-31 | 2023-01-17 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN116845121A (en) * | 2023-07-20 | 2023-10-03 | 深圳阜时科技有限公司 | Photoelectric conversion device, and method for manufacturing the same |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000003345A (en) * | 1998-06-27 | 2000-01-15 | 김영환 | Pinned photo diode of image sensor and production method thereof |
| US6228674B1 (en) * | 1998-12-08 | 2001-05-08 | United Microelectronics Corp. | CMOS sensor and method of manufacture |
| US20020024067A1 (en) * | 2000-08-31 | 2002-02-28 | Jin-Su Han | Image sensor capable of decreasing leakage current between diodes and method for fabricating the same |
| US20030085399A1 (en) * | 2001-08-22 | 2003-05-08 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for manufacturing the same |
| CN1553508A (en) * | 1999-09-06 | 2004-12-08 | ���չ�˾ | Light sensitive element and light sensitive element having internal circuitry |
| US20050156253A1 (en) * | 2004-01-21 | 2005-07-21 | Chui King J. | Structure and method to form source and drain regions over doped depletion regions |
| CN104952893A (en) * | 2014-03-25 | 2015-09-30 | 精工电子有限公司 | Image sensor |
| JP2017005276A (en) * | 2016-09-30 | 2017-01-05 | 株式会社豊田中央研究所 | Single-photon avalanche diode |
| CN106531837A (en) * | 2016-12-29 | 2017-03-22 | 杭州电子科技大学 | Double-junction single-photon avalanche diode and production method thereof |
| CN107946389A (en) * | 2017-11-14 | 2018-04-20 | 重庆邮电大学 | A kind of CMOS single-photon avalanche diodes for long-wave band faint light |
| CN108110021A (en) * | 2017-11-14 | 2018-06-01 | 上海集成电路研发中心有限公司 | A kind of photoelectric diode structure for improving cmos image sensor quantum efficiency |
| CN110246903A (en) * | 2019-06-28 | 2019-09-17 | 湖南师范大学 | The single-photon avalanche photodiode and preparation method thereof of low noise wide spectrum response |
| CN110993710A (en) * | 2019-12-30 | 2020-04-10 | 上海集成电路研发中心有限公司 | Single-photon avalanche diode and preparation method thereof |
-
2021
- 2021-12-02 CN CN202111476922.6A patent/CN114242826B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000003345A (en) * | 1998-06-27 | 2000-01-15 | 김영환 | Pinned photo diode of image sensor and production method thereof |
| US6228674B1 (en) * | 1998-12-08 | 2001-05-08 | United Microelectronics Corp. | CMOS sensor and method of manufacture |
| CN1553508A (en) * | 1999-09-06 | 2004-12-08 | ���չ�˾ | Light sensitive element and light sensitive element having internal circuitry |
| US20020024067A1 (en) * | 2000-08-31 | 2002-02-28 | Jin-Su Han | Image sensor capable of decreasing leakage current between diodes and method for fabricating the same |
| US20030085399A1 (en) * | 2001-08-22 | 2003-05-08 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for manufacturing the same |
| US20050156253A1 (en) * | 2004-01-21 | 2005-07-21 | Chui King J. | Structure and method to form source and drain regions over doped depletion regions |
| CN104952893A (en) * | 2014-03-25 | 2015-09-30 | 精工电子有限公司 | Image sensor |
| JP2017005276A (en) * | 2016-09-30 | 2017-01-05 | 株式会社豊田中央研究所 | Single-photon avalanche diode |
| CN106531837A (en) * | 2016-12-29 | 2017-03-22 | 杭州电子科技大学 | Double-junction single-photon avalanche diode and production method thereof |
| CN107946389A (en) * | 2017-11-14 | 2018-04-20 | 重庆邮电大学 | A kind of CMOS single-photon avalanche diodes for long-wave band faint light |
| CN108110021A (en) * | 2017-11-14 | 2018-06-01 | 上海集成电路研发中心有限公司 | A kind of photoelectric diode structure for improving cmos image sensor quantum efficiency |
| CN110246903A (en) * | 2019-06-28 | 2019-09-17 | 湖南师范大学 | The single-photon avalanche photodiode and preparation method thereof of low noise wide spectrum response |
| CN110993710A (en) * | 2019-12-30 | 2020-04-10 | 上海集成电路研发中心有限公司 | Single-photon avalanche diode and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115621352A (en) * | 2022-10-31 | 2023-01-17 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| WO2024092961A1 (en) * | 2022-10-31 | 2024-05-10 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method therefor |
| CN116845121A (en) * | 2023-07-20 | 2023-10-03 | 深圳阜时科技有限公司 | Photoelectric conversion device, and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114242826B (en) | 2023-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10872995B2 (en) | Avalanche diode along with vertical PN junction and method for manufacturing the same field | |
| JP2015041746A (en) | Single-photon avalanche diode | |
| EP1679749A1 (en) | Semiconductor photodiode and method of making | |
| US9935231B2 (en) | Semiconductor element with a single photon avalanche diode and method for manufacturing such semiconductor element | |
| JP2017005276A (en) | Single-photon avalanche diode | |
| US9515176B2 (en) | Silicon carbide bipolar junction transistor including shielding regions | |
| CN114242826B (en) | Single photon avalanche diode and forming method thereof | |
| TWI647858B (en) | Apparatus and method for single-photon avalanche-photodiode detectors with reduced dark count rate | |
| CN113690337B (en) | Single photon avalanche diode, manufacturing method thereof and single photon avalanche diode array | |
| CN111628034A (en) | Method for manufacturing photoelectric detection device | |
| KR100835113B1 (en) | Bipolar junction transistor and the fabrication method, CMOS image sensor having it and the fabrication method thereof | |
| JP2016152377A (en) | Semiconductor device, manufacturing method for the same and imaging device | |
| CN116207179A (en) | Vertical single photon avalanche diode device and preparation method thereof | |
| CN113690336B (en) | Single photon avalanche diode and manufacturing method thereof | |
| JP2012174783A (en) | Photodiode and photodiode array | |
| WO2003003476A2 (en) | Microelectronic device and method of its manufacture | |
| JP6194524B2 (en) | Photodiode with suppressed noise current and method of forming the same | |
| KR101707896B1 (en) | Silicon photomultiplier | |
| KR101283534B1 (en) | Method for manufacturing silicon photomultiplier device | |
| KR101768704B1 (en) | photo multiplier and manufacturing method for the same | |
| CN117832315A (en) | CMOS APD device and preparation method thereof | |
| KR101707897B1 (en) | Silicon photomultiplier | |
| CN115621352A (en) | Semiconductor device and method for manufacturing the same | |
| CN117393634A (en) | Avalanche diode and preparation method thereof | |
| JP2016039265A (en) | Photodetector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |