CN114219058B - Radio frequency analog circuit and electronic tag - Google Patents
Radio frequency analog circuit and electronic tag Download PDFInfo
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- CN114219058B CN114219058B CN202111412913.0A CN202111412913A CN114219058B CN 114219058 B CN114219058 B CN 114219058B CN 202111412913 A CN202111412913 A CN 202111412913A CN 114219058 B CN114219058 B CN 114219058B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
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Abstract
The application provides a radio frequency analog circuit and an electronic tag, which are characterized in that an input resonance signal is rectified into a first signal through a rectification module, the first signal is limited within a preset amplitude through a clamping modulation module, the first signal is modulated according to a modulation signal, the first signal is used for outputting internal data, and the modulation signal is sent to the clamping modulation module through a control module. According to the application, the clamping of the amplitude of the resonance signal and the modulation of the high level and the low level of the resonance signal are integrated, so that the amplitude of the resonance signal and the amplitude of the modulation signal are limited within the voltage-resistant range of the device, and the working safety of the device is ensured.
Description
Technical Field
The application belongs to the technical field of radio frequency identification, and particularly relates to a radio frequency analog circuit and an electronic tag.
Background
Radio frequency identification (Radio Frequency Identification, RFID) is an automatic identification technology of non-contact two-way communication, and the radio frequency identification technology can be used for performing read-write operation on an electronic tag, so that various functions such as identification target and data exchange are realized. The application field of radio frequency identification is very wide, and the radio frequency identification has wide application in the aspects of animal tags, automobile burglar alarms, access control management, production line management, warehouse management and the like.
However, the radio frequency analog circuit in the traditional electronic tag generally adjusts the amplitude of the resonance signal by directly changing the impedance, so that the voltage in the radio frequency analog circuit may exceed the withstand voltage range of the internal device, the device is easy to burn out, and the safety is low.
Disclosure of Invention
The application aims to provide a radio frequency analog circuit and an electronic tag, and aims to solve the problem of low safety of the traditional radio frequency analog circuit.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides a radio frequency analog circuit, including a rectifying module, a clamping modulation module, and a control module;
the clamping modulation module is electrically connected with the rectifying module and the control module;
the rectification module is configured to rectify an input resonance signal into a first signal;
The clamping modulation module is configured to limit the first signal within a preset amplitude value, and modulate the first signal according to a modulation signal so as to output internal data;
The control module is configured to send a modulation signal to the clamp modulation module.
In a possible implementation manner of the first aspect, the radio frequency analog circuit further includes a voltage stabilizing module;
The voltage stabilizing module is electrically connected with the rectifying module;
The voltage stabilizing module is configured to stabilize the first signal into a second signal.
In another possible implementation manner of the first aspect, the clamping modulation module includes a modulation unit and a clamping unit;
the clamping unit and the modulation unit are electrically connected with the rectification module;
The clamping unit is configured to limit the first signal within a preset amplitude;
the modulation unit is configured to modulate the first signal according to a modulation signal.
In another possible implementation manner of the first aspect, the modulation unit includes a first PMOS transistor, a second PMOS transistor, a fourth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, a fifth NMOS transistor, a first triode, and a second triode;
The source electrode of the first PMOS tube is electrically connected with the emitter electrode of the first triode, the base electrode of the second triode and the clamping unit, the emitter electrode of the second triode is electrically connected with the drain electrode of the second PMOS tube, and the source electrode of the second PMOS tube is electrically connected with the rectifying module; the drain electrode of the first PMOS tube is electrically connected with the grid electrode of the first PMOS tube and the drain electrode of the first NMOS tube; the first modulation signal is electrically connected with the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube is electrically connected with the grid electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube and the source electrode of the seventh PMOS tube, and the source electrode of the fourth PMOS tube is electrically connected with the base electrode of the first triode;
The drain electrode of the seventh PMOS tube is electrically connected with the grid electrode of the seventh PMOS tube, the drain electrode of the fifth NMOS tube and the grid electrode of the fifth NMOS tube; the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the source electrode of the fifth NMOS tube, the collector electrode of the first triode and the collector electrode of the second triode are all grounded.
In another possible implementation manner of the first aspect, the clamping unit includes a third PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor;
The source electrode of the third PMOS tube is electrically connected with the rectifying module, the grid electrode of the third PMOS tube is electrically connected with the modulating module, the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube, the grid electrode of the sixth NMOS tube is electrically connected with the drain electrode of the seventh NMOS tube and the rectifying module, and the source electrodes of the sixth NMOS tube and the seventh NMOS tube are grounded.
In another possible implementation manner of the first aspect, the voltage stabilizing module includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a first capacitor;
The drain electrode of the eighth PMOS tube is electrically connected with the source electrode of the tenth PMOS tube and the rectifying module, the source electrode of the eighth PMOS tube is electrically connected with the source electrode of the eleventh PMOS tube, one end of the first capacitor and the drain electrode of the ninth PMOS tube, and the grid electrode of the ninth PMOS tube is electrically connected with the source electrode of the ninth PMOS tube; the grid electrode of the tenth PMOS tube is electrically connected with the drain electrode of the tenth PMOS tube, the drain electrode of the eighth NMOS tube, the grid electrode of the eleventh PMOS tube and the grid electrode of the ninth NMOS tube, the drain electrode of the eleventh PMOS tube is electrically connected with the grid electrode of the eighth PMOS tube and the drain electrode of the ninth NMOS tube, and the source electrode of the eighth NMOS tube is grounded with the source electrode of the ninth NMOS tube and the other end of the first capacitor.
In another possible implementation manner of the first aspect, the radio frequency analog circuit further includes a demodulation module;
the demodulation module is electrically connected with the rectification module and the control module;
The demodulation module is configured to form corresponding control level from the command information carried in the first signal and send the corresponding control level to the control module.
In another possible implementation manner of the first aspect, the radio frequency analog circuit further includes a clock module;
The clock module is electrically connected with the resonance signal, the rectifying module and the control module;
the clock module is configured to generate clock information according to the resonance signal and send the clock information to the control module.
In another possible implementation manner of the first aspect, the radio frequency analog circuit further includes a power-on reset module;
The power-on reset module is electrically connected with the rectifying module and the control module;
the power-on reset module is configured to output a low-level signal for a preset time to the control module according to the first signal.
In a second aspect, an embodiment of the present application provides an electronic tag, including the radio frequency analog circuit and the memory circuit;
the storage circuit is electrically connected with the radio frequency analog circuit;
The memory circuit is configured to store internal data.
Compared with the prior art, the embodiment of the application has the beneficial effects that: according to the radio frequency analog circuit, the input resonance signal is rectified into the first signal through the rectification module, the first signal is limited in the preset amplitude through the clamping modulation module, the first signal is modulated according to the modulation signal, the radio frequency analog circuit is used for outputting internal data, and the modulation signal is sent to the clamping modulation module through the control module. According to the application, the clamping of the amplitude of the resonance signal and the modulation of the high level and the low level of the resonance signal are integrated, so that the amplitude of the resonance signal and the amplitude of the modulation signal are limited within the voltage-resistant range of the device, and the working safety of the device is ensured.
Drawings
In order to more clearly illustrate the technical solutions in application, the following description will be briefly presented with reference to the drawings used in the embodiments or the description of the prior art, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings can be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a first structure of a radio frequency analog circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a second structure of a radio frequency analog circuit according to an embodiment of the present application;
fig. 3 is a circuit diagram of a clamp modulation module of a radio frequency analog circuit according to an embodiment of the present application;
FIG. 4 is a circuit diagram of a voltage stabilizing module of a radio frequency analog circuit according to an embodiment of the present application;
fig. 5 is a circuit diagram of a third structure of a radio frequency analog circuit according to an embodiment of the present application;
fig. 6 is a schematic diagram of an electronic tag according to an embodiment of the present application.
Reference numerals illustrate:
The device comprises a 1-rectifying module, a 2-clamping modulation module, a 21-modulating unit, a 22-clamping unit, a 3-control module, a 4-voltage stabilizing module, a 5-demodulation module, a 6-clock module and a 7-power-on reset module.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
At present, the conventional radio frequency analog circuit generally adjusts the amplitude of a resonance signal by directly changing the impedance of the resonance circuit, so as to achieve the purposes of modulating the resonance signal and outputting the internal data of the electronic tag. However, the modulation method may cause a problem that the voltage in the radio frequency analog circuit exceeds the withstand voltage range of the internal device, and the internal device is burned.
Therefore, the application provides the radio frequency analog circuit, and the amplitude of the resonance signal is always limited within the voltage-resistant range of the device by clamping the resonance signal while the modulation signal outputs internal data, so that the safety of the internal device is ensured.
The radio frequency analog circuit provided by the application is described in an exemplary manner by referring to the accompanying drawings: fig. 1 is a schematic diagram of a first structure of a radio frequency analog circuit according to an embodiment of the present application, as shown in fig. 1, for convenience of explanation, only a portion related to the embodiment is shown, and the following details are described below: illustratively, the radio frequency analog circuit comprises a rectifying module 1, a clamping modulation module 2 and a control module 3;
the clamping modulation module 2 is electrically connected with the rectification module 1 and the control module 3;
A rectifying module 1 configured to rectify an input resonance signal into a first signal;
A clamp modulation module 2 configured to limit the first signal within a preset amplitude and modulate the first signal according to a modulation signal for outputting internal data;
and a control module 3 configured to transmit the modulation signal to the clamp modulation module.
In application, firstly, an electromagnetic wave signal is sent through an antenna of a reader-writer, a resonance signal is generated through a resonance inductor and a resonance capacitor in an electronic tag, then the input resonance signal is rectified into a first signal (namely a positive voltage signal for supplying power to other modules in a radio frequency analog circuit) through a rectification module, the first signal is limited within a preset amplitude through a clamping modulation module, the internal electronic device is prevented from being burnt due to the excessive amplitude, the first signal is modulated according to a modulation signal for outputting internal data, and the internal data is sent to the reader-writer in a carrier mode, wherein the modulation signal is generated through a control module.
Fig. 2 is a schematic diagram of a second structure of a radio frequency analog circuit according to an embodiment of the present application, where, as shown in fig. 2, the radio frequency analog circuit further includes a voltage stabilizing module;
the voltage stabilizing module 4 is electrically connected with the rectifying module 1;
the voltage stabilizing module 4 is configured to stabilize the first signal into the second signal.
In application, the voltage stabilizing module is matched with the energy storage capacitor, so that the first signal can be stabilized, and a second signal power supply with better stability and smaller fluctuation is generated.
Fig. 3 is a circuit diagram of a clamp modulation module of a radio frequency analog circuit according to an embodiment of the present application, and as shown in fig. 3, an exemplary clamp modulation module 2 includes a modulation unit 21 and a clamp unit 22;
the clamping unit 21 and the modulation unit 22 are electrically connected with the rectification module 1;
A clamping unit 22 configured to limit the first signal to within a preset amplitude;
The modulation unit 21 is configured to modulate the first signal according to the modulation signal.
In application, the first signal is limited within a preset amplitude value through the clamping unit, so that the amplitude value of the resonance signal is prevented from exceeding the withstand voltage range of the internal device, and the internal device is prevented from being burnt; the first signal is modulated by the modulating unit according to the modulating signal, so that the first signal is modulated into a carrier signal corresponding to the internal data to be output, and the internal data is further output to the reader-writer.
As shown in fig. 3, the modulation unit 21 illustratively includes a first PMOS transistor P1, a second PMOS transistor P2, a fourth PMOS transistor P4, a seventh PMOS transistor P7, a first NMOS transistor N1, a second NMOS transistor N2, a fifth NMOS transistor N5, a first triode PNP1, and a second triode PNP2;
The source electrode of the first PMOS tube P1 is electrically connected with the emitter electrode of the first triode PNP1, the base electrode of the second triode PNP2 and the clamping unit 22, the emitter electrode of the second triode PNP2 is electrically connected with the drain electrode of the second PMOS tube P2, and the source electrode of the second PMOS tube P2 is electrically connected with the rectifying module 1; the drain electrode of the first PMOS tube P1 is electrically connected with the grid electrode of the first PMOS tube P1 and the drain electrode of the first NMOS tube N1; the first modulation signal CTRL1 is electrically connected with the grid electrode of the first NMOS tube N1 and the grid electrode of the second NMOS tube N2, the drain electrode of the second NMOS tube N2 is electrically connected with the grid electrode of the fourth PMOS tube P4, the drain electrode of the fourth PMOS tube P4 and the source electrode of the seventh PMOS tube P7, and the source electrode of the fourth PMOS tube P4 is electrically connected with the base electrode of the first triode PNP 1;
The drain electrode of the seventh PMOS tube P7 is electrically connected with the grid electrode of the seventh PMOS tube P7, the drain electrode of the fifth NMOS tube N5 and the grid electrode of the fifth NMOS tube N5; the source electrode of the first NMOS tube N1, the source electrode of the second NMOS tube N2, the source electrode of the fifth NMOS tube N5, the collector electrode of the first triode PNP1 and the collector electrode of the second triode PNP2 are all grounded.
In application, the modulation signal may include one or more, and when the modulation signal is one, the first signal is subjected to high-low level voltage modulation through the first PMOS transistor, the second PMOS transistor, the fourth PMOS transistor, the seventh PMOS transistor, the fifth NMOS transistor, the first triode and the second triode, and the first NMOS transistor and the second NMOS transistor are used as switches of voltage modulation depth for deepening or stopping deepening voltage modulation.
When the modulation signals are multiple, the modulation unit comprises a first PMOS tube, a second PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first triode and a second triode;
The source electrode of the first PMOS tube is electrically connected with the emitter electrode of the first triode, the base electrode of the second triode and the clamping unit, the emitter electrode of the second triode is electrically connected with the drain electrode of the second PMOS tube, and the source electrode of the second PMOS tube is electrically connected with the rectifying module; the drain electrode of the first PMOS tube is electrically connected with the grid electrode of the first PMOS tube and the drain electrode of the first NMOS tube; the first modulation signal CTRL1 is electrically connected with the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube is electrically connected with the grid electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube, and the source electrode of the fourth PMOS tube is electrically connected with the base electrode of the first triode;
The second modulation signal CTRL2 is electrically connected with the grid electrode of the third NMOS tube, and the drain electrode of the third NMOS tube is electrically connected with the grid electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube; the third modulation signal CTRL3 is electrically connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is electrically connected with the grid electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube, and the drain electrode of the seventh PMOS tube is electrically connected with the grid electrode of the seventh PMOS tube, the drain electrode of the fifth NMOS tube and the grid electrode of the fifth NMOS tube; the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube, the collector electrode of the first triode and the collector electrode of the second triode are all grounded.
In application, the first signal is subjected to high-low level voltage modulation through the first PMOS tube, the second PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the fifth NMOS tube, the first triode and the second triode, and the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are used as switches of voltage modulation depth and used for starting or stopping the voltage modulation, or different modulation depths are selected.
Specifically, the first modulation signal, the second modulation signal and the third modulation signal are interfaces of the clamp modulation unit and the control module, and when one or more of the clamp modulation units and the control module are electrically connected with the control module, different modulation depths can be generated. For example, only the first modulation signal is used to electrically connect with the control module; or the first modulation signal and the second modulation signal are electrically connected with the control module at the same time; or the first modulation signal, the second modulation signal and the third modulation signal are all electrically connected with the control module. Different modulation depths can be generated and 7 different modulation depths can be generated by different combinations. If only one modulation depth is needed, only one modulation signal is electrically connected with the control module, and the other modulation signals are additional selection interfaces and can be grounded.
As shown in fig. 3, the clamp unit 22 includes, illustratively, a third PMOS transistor P3, a sixth NMOS transistor N6, and a seventh NMOS transistor N7;
The source electrode of the third PMOS tube P3 is electrically connected with the rectifying module, the grid electrode of the third PMOSP3 tube is electrically connected with the modulating module, the drain electrode of the third PMOSP3 tube is electrically connected with the drain electrode of the sixth NMOS tube N6 and the grid electrode of the seventh NMOS tube N7, the grid electrode of the sixth NMOS tube N6 is electrically connected with the drain electrode of the seventh NMOS tube N7 and the rectifying module, and the source electrode of the sixth NMOS tube N6 and the source electrode of the seventh NMOS tube N7 are grounded.
In application, the third PMOS tube, the sixth NMOS tube and the seventh NMOS tube clamp the resonance signals, so that the amplitude of the first signal is limited within a preset amplitude range, and the damage to internal electronic devices caused by overhigh amplitude is prevented.
Fig. 4 is a circuit diagram of a voltage stabilizing module of a radio frequency analog circuit according to an embodiment of the present application, as shown in fig. 4, the voltage stabilizing module includes an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, an eighth NMOS transistor N8, a ninth NMOS transistor N9, and a first capacitor C1, for example;
The drain electrode of the eighth PMOS tube P8 is electrically connected with the source electrode of the tenth PMOS tube and the rectifying module, the source electrode of the eighth PMOS tube P8 is electrically connected with the source electrode of the eleventh PMOS tube P11, one end of the first capacitor C1 and the drain electrode of the ninth PMOS tube P9, and the grid electrode of the ninth PMOS tube P9 is electrically connected with the source electrode of the ninth PMOS tube P9; the grid electrode of the tenth PMOS tube P10 is electrically connected with the drain electrode of the tenth PMOS tube P10, the drain electrode of the eighth NMOS tube N8, the grid electrode of the eighth NMOS tube N8, the drain electrode of the eleventh PMOS tube P11 and the grid electrode of the ninth NMOS tube N9, the source electrode of the eleventh PMOS tube P11 is electrically connected with the grid electrode of the eighth PMOS tube P8 and the drain electrode of the ninth NMOS tube N9, and the source electrode of the eighth NMOS tube N8 is grounded with the source electrode of the ninth NMOS tube N9 and the other end of the first capacitor C1.
In application, when the voltage VX between the eighth PMOS transistor and the ninth PMOS transistor is higher, the first signal VDD1 is lower than VX. The gate voltage of the tenth PMOS tube is reduced, so that the gate voltages of the eighth NMOS tube and the ninth NMOS tube are reduced, and finally the gate voltage of the eighth PMOS tube is increased, so that the output voltage of the eighth PMOS tube is reduced, and the purpose of stabilizing voltage is achieved. Meanwhile, the purpose of mutual isolation between the second signal VDD2 and the first signal VDD1 is achieved through the ninth PMOS tube, so that the power supply of a subsequent circuit is more stable. If a different supply voltage is required, this can be achieved by dividing or stabilizing the voltage on the basis of the second signal VDD 2. Meanwhile, the eighth NMOS tube can be connected with the tenth NMOS tube N10 in series, and the ninth NMOS tube can be connected with the eleventh NMOS tube N11 in series, so that a better voltage stabilizing effect is achieved.
Fig. 5 is a circuit diagram of a third structure of a radio frequency analog circuit according to an embodiment of the present application, where, as shown in fig. 5, the radio frequency analog circuit exemplarily further includes a demodulation module;
The demodulation module is electrically connected with the rectification module and the control module;
the demodulation module is configured to form corresponding control level from command information carried in the first signal and send the corresponding control level to the control module.
In application, command information sent by the reader-writer is sent to the control module in a corresponding control level mode through the demodulation module, so that the control module in the electronic tag can perform corresponding operation according to the command information.
As shown in fig. 5, the radio frequency analog circuit further illustratively includes a clock module;
The clock module is electrically connected with the resonance signal, the rectifying module and the control module;
And the clock module is configured to generate clock information according to the resonance signal and send the clock information to the control module.
In application, the alternating resonance signal is shaped by the clock module to obtain a clock signal and sent to the control module for use.
As shown in fig. 5, the radio frequency analog circuit also illustratively includes a power-on reset module;
the power-on reset module is electrically connected with the rectifying module and the control module;
the power-on reset module is configured to output a low-level signal for a preset time to the control module according to the first signal.
In application, a low level signal is output for a period of time in the first few oscillation periods of the resonance signal, so that a power-on reset signal is provided for the control module, and digital logic confusion and errors caused by unstable power supply at the time of initial resonance are prevented.
Fig. 6 is a schematic diagram of an electronic tag according to an embodiment of the present application, as shown in fig. 6, and exemplary, this embodiment discloses an electronic tag 300 of a radio frequency analog circuit, including a radio frequency analog circuit 100 and a memory circuit 200;
the memory circuit 200 is electrically connected with the radio frequency analog circuit 100;
The memory circuit 200 is configured to store internal data.
In application, a radio frequency analog circuit is provided inside the electronic tag for receiving command signals of the reader/writer 400 and transmitting internal data to the reader/writer 400. Firstly, an electromagnetic wave signal is sent through an antenna of the reader-writer, a resonance signal is generated through a resonance inductor and a resonance capacitor in the electronic tag, and then a command signal sent by the reader-writer is demodulated through a radio frequency analog circuit, or internal data is sent to the reader-writer in a form of a modulation signal, so that data exchange between the electronic tag and the reader-writer is realized.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed ups parallel operation redundancy system and method may be implemented in other manners. For example, the ups parallel redundancy system embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (8)
1. The radio frequency analog circuit is characterized by comprising a rectifying module, a clamping modulation module and a control module;
the clamping modulation module is electrically connected with the rectifying module and the control module;
the rectification module is configured to rectify an input resonance signal into a first signal;
The clamping modulation module is configured to limit the first signal within a preset amplitude value, and modulate the first signal according to a modulation signal so as to output internal data;
the control module is configured to send a modulation signal to the clamp modulation module;
the clamping modulation module comprises a modulation unit and a clamping unit;
the clamping unit and the modulation unit are electrically connected with the rectification module;
The clamping unit is configured to limit the first signal within a preset amplitude;
The modulation unit is configured to modulate the first signal according to a modulation signal;
The modulation unit comprises a first PMOS tube, a second PMOS tube, a fourth PMOS tube, a seventh PMOS tube, a first NMOS tube, a second NMOS tube, a fifth NMOS tube, a first triode and a second triode;
The source electrode of the first PMOS tube is electrically connected with the emitter electrode of the first triode, the base electrode of the second triode and the clamping unit, the emitter electrode of the second triode is electrically connected with the drain electrode of the second PMOS tube, and the source electrode of the second PMOS tube is electrically connected with the rectifying module; the drain electrode of the first PMOS tube is electrically connected with the grid electrode of the first PMOS tube and the drain electrode of the first NMOS tube; the first modulation signal is electrically connected with the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube is electrically connected with the grid electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube and the source electrode of the seventh PMOS tube, and the source electrode of the fourth PMOS tube is electrically connected with the base electrode of the first triode;
The drain electrode of the seventh PMOS tube is electrically connected with the grid electrode of the seventh PMOS tube, the drain electrode of the fifth NMOS tube and the grid electrode of the fifth NMOS tube; the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the source electrode of the fifth NMOS tube, the collector electrode of the first triode and the collector electrode of the second triode are all grounded.
2. The radio frequency analog circuit of claim 1, wherein the radio frequency analog circuit further comprises a voltage regulation module;
The voltage stabilizing module is electrically connected with the rectifying module;
The voltage stabilizing module is configured to stabilize the first signal into a second signal.
3. The radio frequency analog circuit of claim 1, wherein the clamp unit comprises a third PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor;
The source electrode of the third PMOS tube is electrically connected with the rectifying module, the grid electrode of the third PMOS tube is electrically connected with the modulating module, the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube, the grid electrode of the sixth NMOS tube is electrically connected with the drain electrode of the seventh NMOS tube and the rectifying module, and the source electrodes of the sixth NMOS tube and the seventh NMOS tube are grounded.
4. The radio frequency analog circuit of claim 2, wherein the voltage regulator module comprises an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a first capacitor;
The drain electrode of the eighth PMOS tube is electrically connected with the source electrode of the tenth PMOS tube and the rectifying module, the source electrode of the eighth PMOS tube is electrically connected with the source electrode of the eleventh PMOS tube, one end of the first capacitor and the drain electrode of the ninth PMOS tube, and the grid electrode of the ninth PMOS tube is electrically connected with the source electrode of the ninth PMOS tube; the grid electrode of the tenth PMOS tube is electrically connected with the drain electrode of the tenth PMOS tube, the drain electrode of the eighth NMOS tube, the grid electrode of the eleventh PMOS tube and the grid electrode of the ninth NMOS tube, the drain electrode of the eleventh PMOS tube is electrically connected with the grid electrode of the eighth PMOS tube and the drain electrode of the ninth NMOS tube, and the source electrode of the eighth NMOS tube is grounded with the source electrode of the ninth NMOS tube and the other end of the first capacitor.
5. A radio frequency analog circuit according to any one of claims 1-3, wherein the radio frequency analog circuit further comprises a demodulation module;
the demodulation module is electrically connected with the rectification module and the control module;
The demodulation module is configured to form corresponding control level from the command information carried in the first signal and send the corresponding control level to the control module.
6. A radio frequency analog circuit according to any one of claims 1-3, wherein the radio frequency analog circuit further comprises a clock module;
The clock module is electrically connected with the resonance signal, the rectifying module and the control module;
the clock module is configured to generate clock information according to the resonance signal and send the clock information to the control module.
7. A radio frequency analog circuit according to any of claims 1-3, further comprising a power-on reset module;
The power-on reset module is electrically connected with the rectifying module and the control module;
the power-on reset module is configured to output a low-level signal for a preset time to the control module according to the first signal.
8. An electronic tag comprising the radio frequency analog circuit of any one of claims 1-7 and a memory circuit;
the storage circuit is electrically connected with the radio frequency analog circuit;
The memory circuit is configured to store internal data.
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| CN114219058B true CN114219058B (en) | 2024-06-11 |
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| CN114219058A (en) | 2022-03-22 |
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