CN114217482A

CN114217482A - Display panel and display device

Info

Publication number: CN114217482A
Application number: CN202111512916.1A
Authority: CN
Inventors: 胡洋; 袁海江
Original assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Priority date: 2021-12-11
Filing date: 2021-12-11
Publication date: 2022-03-22

Abstract

The application discloses display panel and display device belongs to and shows technical field. The display panel includes a plurality of first electrodes, a liquid crystal layer, a second electrode, and a third electrode. The plurality of first electrodes are arranged in an array mode, the liquid crystal layer comprises a plurality of liquid crystal units, and the plurality of liquid crystal units are located between the plurality of first electrodes and the second electrodes one by one. The second electrode is positioned between the liquid crystal layer and the third electrode, and the third electrode and the second electrode form a capacitor. When the display panel works, an electric field can be formed between the first electrode and the second electrode and drives the liquid crystal unit to deflect. Meanwhile, the voltage on the second electrode can be kept stable under the action of the capacitor formed by the second electrode and the third electrode, so that the voltage of the second electrode cannot be changed along with the voltage change of the pixel electrode, and the display effect of the display panel is improved.

Description

Display panel and display device

Technical Field

The present disclosure relates to display technologies, and particularly to a display panel and a display device.

Background

The display panel includes a backlight, a plurality of pixel electrodes, a plurality of liquid crystal cells, and a common electrode. The liquid crystal units are positioned between the pixel electrodes and the common electrode one by one. The backlight source is positioned on one side of the pixel electrodes far away from the liquid crystal units and emits light rays to the positions of the pixel electrodes. When the display panel works, a plurality of pixel electrodes and a plurality of common electrodes are all inputted with voltages, and an electric field is formed between the pixel electrodes and the common electrodes, wherein the electric field can deflect liquid crystal cells in the electric field. After the liquid crystal unit deflects, the light emitted by the backlight can penetrate through the liquid crystal unit.

In the related art, when the display panel is operated, it is desirable that the voltage of the common electrode is kept constant, and the deflection angle of each liquid crystal cell is changed by changing only the voltage of each pixel electrode, thereby changing the light transmittance of each liquid crystal cell.

However, when the display panel operates, the voltage of the pixel electrode may change continuously, and the voltage change of the pixel electrode may be coupled to the common electrode, which may cause the voltage of the common electrode to change, and affect the display effect of the display panel.

Disclosure of Invention

The application provides a display panel and a display device, which can solve the problem that the voltage change of a pixel electrode can be coupled to a common electrode to cause the voltage change of the common electrode in the related art, thereby improving the display effect of the display panel. The technical scheme is as follows:

in a first aspect, a display panel is provided, including: a plurality of first electrodes, a liquid crystal layer, and a second electrode;

the plurality of first electrodes are arranged in an array;

the liquid crystal layer comprises a plurality of liquid crystal units, and the liquid crystal units are located between the first electrodes and the second electrodes one by one, so that when an electric field is formed between one first electrode of the first electrodes and the second electrode, the liquid crystal unit located between the first electrode and the second electrode deflects under the action of the electric field;

the display panel further includes: a third electrode;

the second electrode is positioned between the liquid crystal layer and the third electrode, and the third electrode and the second electrode form a first capacitor; the second electrode is used for being connected with a public voltage driver so as to input public voltage, the third electrode is used for being connected with a preset voltage end so as to input preset voltage, and the preset voltage is not equal to the public voltage.

In the present application, the display panel includes a plurality of first electrodes, a liquid crystal layer, a second electrode, and a third electrode. The plurality of first electrodes are arranged in an array mode, the liquid crystal layer comprises a plurality of liquid crystal units, and the plurality of liquid crystal units are located between the plurality of first electrodes and the second electrodes one by one. The second electrode is positioned between the liquid crystal layer and the third electrode, and the third electrode and the second electrode form a capacitor. When the display panel works, the plurality of first electrodes are used as pixel electrodes, the second electrodes are used as common electrodes for inputting common voltage, and an electric field can be formed between the first electrodes and the second electrodes and drives the liquid crystal unit to deflect. Meanwhile, under the condition that the third electrode inputs the preset voltage, the voltage on the second electrode can be kept stable under the action of the capacitor formed by the second electrode and the third electrode, so that the voltage of the second electrode cannot be changed along with the voltage change of the pixel electrode, and the display effect of the display panel is improved.

Optionally, the display panel further comprises: a dielectric layer;

the dielectric layer is located between the second electrode and the third electrode.

Optionally, the display panel further comprises: a glass substrate and a plurality of color resists;

the color resistors are located between the glass substrate and the third electrode, and the third electrode is located between the color resistors and the dielectric layer.

the third electrode is located between the glass substrate and the plurality of color resistors, and the plurality of color resistors are located between the third electrode and the second electrode.

Optionally, a plane of the third electrode is parallel to a plane of the second electrode;

and the vertical projection of the second electrode on the plane where the third electrode is positioned in the coverage range of the third electrode.

In a second aspect, there is provided a display device comprising a common voltage driver and the display panel of any one of the first aspect;

and the output end of the common voltage driver is connected with the second electrode so as to output common voltage to the second electrode.

Optionally, the display device further comprises: a second capacitor;

and the first pole plate of the second capacitor is connected with the second electrode, and the second pole plate of the second capacitor is connected with the preset voltage end so as to input the preset voltage.

Optionally, the display device comprises a display area and a non-display area adjacent to the display area; the second electrode at least covers the display area, and the common voltage driver is positioned in the non-display area;

the display device comprises a plurality of second capacitors, the plurality of second capacitors are all positioned in the non-display area, and second pole plates of the plurality of second capacitors are all connected with the preset voltage end;

the display device further includes: a plurality of connection lines; the first ends of the connecting wires are connected with the first pole plates of the second capacitors one by one, the second ends of the connecting wires are connected with the second electrodes, and the second ends of different connecting wires in the connecting wires are connected to different positions of the second electrodes.

Optionally, the plurality of first electrodes have a space between vertical projections of the plane where the second electrode is located, and the plurality of connection lines are located in the space.

Optionally, the display device further comprises: an operational amplifier and a push-pull circuit;

the non-inverting input end of the operational amplifier is connected with the output end of the common voltage driver, and the output end of the operational amplifier is connected with the input end of the push-pull circuit;

and the output end of the push-pull circuit is connected with the second electrode and the inverting input end of the operational amplifier.

It is understood that the beneficial effects of the second aspect can be referred to the related description of the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a first display panel according to a second embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a second display panel provided in the second embodiment of the present application;

fig. 5 is a schematic structural diagram of a third display panel provided in the second embodiment of the present application;

fig. 6 is a schematic structural diagram of a first display panel according to a third embodiment of the present application;

fig. 7 is a schematic structural diagram of a second display panel according to a third embodiment of the present application;

fig. 8 is a schematic structural diagram of a display device according to a fourth embodiment of the present application;

fig. 9 is a schematic diagram illustrating region division of a display device according to a fifth embodiment of the present application;

fig. 10 is a schematic structural diagram of a display device according to a fifth embodiment of the present application;

fig. 11 is a connection structure diagram of a first connection line and a second electrode according to a fifth embodiment of the present application;

fig. 12 is a connection structure diagram of a second connection line and a second electrode according to a fifth embodiment of the present application;

fig. 13 is a circuit configuration diagram of an internal circuit of a first display device according to a sixth embodiment of the present application;

fig. 14 is a circuit configuration diagram of an internal circuit of a second display device according to a sixth embodiment of the present application.

Wherein, the meanings represented by the reference numerals of the figures are respectively as follows:

10. a display panel;

110. an array substrate;

112. a first electrode;

1122. a first projection;

114. a drive transistor;

120. a liquid crystal layer;

122. a liquid crystal cell;

130. a second electrode;

140. a third electrode;

150. a dielectric layer;

160. a glass substrate;

172. color resistance;

174. a black matrix;

180. a planarization layer;

20. a display device;

22. a display area;

24. a non-display area;

210. a common voltage driver;

212. a connecting wire;

214. an insulator;

220. a time schedule controller;

230. a gate driver;

240. a source driver;

250. a push-pull circuit.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that reference to "a plurality" in this application means two or more. In the description of the present application, "/" means "or" unless otherwise stated, for example, a/B may mean a or B; "and/or" herein is only an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, for the convenience of clearly describing the technical solutions of the present application, the terms "first", "second", and the like are used to distinguish the same items or similar items having substantially the same functions and actions. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

The following explains and describes in detail different structures of the display panel according to the embodiment of the present application from the first embodiment to the third embodiment.

The first embodiment is as follows:

fig. 1 is a schematic structural diagram of a display panel 10 according to an embodiment of the present application. Referring to fig. 1, the display panel 10 includes a plurality of first electrodes 112, a liquid crystal layer 120, a second electrode 130, and a third electrode 140.

The first electrodes 112 are pixel electrodes in the display panel 10. Specifically, the display panel 10 may generally include an array substrate 110, and fig. 2 is a schematic structural diagram of the array substrate 110 according to an embodiment of the present disclosure, and as shown in fig. 2, the array substrate 110 includes a plurality of gate lines, a plurality of source lines, a plurality of driving transistors 114, and a plurality of first electrodes 112. In the embodiment shown in fig. 2, the plurality of gate lines includes G1, G2, and G3, and the plurality of source lines includes S1, S2, and S3. Each drive transistor 114 has a first pole, a second pole, and a control pole (not shown). The gate of each driving transistor 114 is connected to one gate line, so that when the gate line outputs a high-level signal, the driving transistor 114 connected to the gate line is turned on. A first electrode of each of the driving transistors 114 is connected to a source line, so that when the driving transistor 114 is turned on and the source line connected to the driving transistor 114 outputs a data voltage, the data voltage can be input to the first electrode 112 through the driving transistor 114. The driving transistor 114 may be a P-type MOS (metal oxide semiconductor) field effect transistor. The gate of the driving transistor 114 is the gate of a P-type MOS field effect transistor, the first pole of the driving transistor 114 is the source of the P-type MOS field effect transistor, and the second pole of the driving transistor 114 is the drain of the P-type MOS field effect transistor. Generally, as shown in fig. 2, the source lines to which the plurality of driving transistors 114 connected to the same gate line are connected are different. When the array substrate 110 operates, the plurality of gate lines output high-level signals one by one, so that the plurality of driving transistors 114 are turned on one by one. When each gate line outputs a high level signal, i.e., each row of driving transistors 114 is turned on, the source lines each output a data voltage, thereby outputting the data voltage to different driving transistors 114 in the same row. Thus, the data voltages can be inputted to all the first electrodes 112, and the data voltage inputted to each first electrode 112 can be individually controlled. The plurality of first electrodes 112 may be arranged in an array, that is, the plurality of first electrodes 112 are arranged in a plurality of rows and a plurality of columns.

The second electrode 130 is a common electrode in the display panel 10. The second electrode 130 is for connection with the common voltage driver 210, thereby inputting the common voltage VCOM. Generally, the common voltage VCOM output by the common voltage driver 210 is a constant voltage direct current, for example, the common voltage VCOM may be a constant 1V (volt) direct current. Thus, when a data voltage is inputted to any one of the first electrodes 112, an electric field is formed between the first electrode 112 to which the data voltage is inputted and the second electrode 130 to which the common voltage VCOM is inputted.

The liquid crystal layer 120 includes a plurality of liquid crystal cells 122. The liquid crystal cells 122 are located between the first electrodes 112 and the second electrodes 130. Thus, when an electric field is formed between the first electrode 112 to which the data voltage is input and the second electrode 130 to which the common voltage VCOM is input, the liquid crystal cell 122 in the electric field is deflected by the electric field. In other words, when a data voltage is inputted to any one of the first electrodes 112, the liquid crystal cell 122 located between the first electrode 112 and the second electrode 130 is deflected by the electric field formed by the first electrode 112 and the second electrode 130. By controlling the magnitude of the data voltage inputted from the first electrode 112, the deflection angle of the liquid crystal can be controlled.

The third electrode 140 is positioned such that the second electrode 130 is positioned between the liquid crystal layer 120 and the third electrode 140. In other words, the third electrode 140 is located on the side of the second electrode 130 away from the liquid crystal layer 120. The third electrode 140 is insulated from the second electrode 130, so that the third electrode 140 can be coupled with the second electrode 130 to form a capacitor. For convenience of description, a capacitance formed by the third electrode 140 coupled with the second electrode 130 is referred to as a first capacitance. The third electrode 140 is connected to the preset voltage terminal V0, such that when the display panel 10 is in operation, the third electrode 140 inputs a preset voltage. The preset voltage is not equal to the common voltage VCOM. In some embodiments, the predetermined voltage may be 0V, and the predetermined voltage terminal V0 is the ground GND of the display panel 10. In some embodiments, the first electrode 112, the second electrode 130, and the third electrode 140 may be formed of an ITO (Indium tin oxide) material.

In the embodiment of the present application, the second electrode 130 and the third electrode 140 are coupled to form a first capacitor. When the display panel 10 is operated, the plurality of first electrodes 112 are used as pixel electrodes, the second electrode 130 to which the common voltage VCOM is inputted is used as a common electrode, and an electric field for driving the liquid crystal cell 122 to deflect is formed between the first electrodes 112 and the second electrode 130. Meanwhile, when the display panel 10 works, the third electrode 140 inputs a preset voltage, and the voltage on the second electrode 130 can be kept stable under the action of the first capacitor, so that the voltage of the second electrode 130 does not change along with the voltage change of the pixel electrode, and the display effect of the display panel 10 is improved.

In some embodiments, the third electrode 140 is in a plane parallel to the plane of the second electrode 130. The perpendicular projection of the second electrode 130 on the plane of the third electrode 140 is located within the coverage of the third electrode 140. That is, the coverage of the second electrode 130 is within the coverage of the third electrode 140 when viewed from a direction perpendicular to the plane of the second electrode 130. In this case, the effective area of the first capacitor formed by coupling the second electrode 130 and the third electrode 140 can be maximized. That is, under the condition that other conditions are not changed, the capacitance value of the first capacitor is maximized, so that the voltage of the second electrode 130 is not changed along with the voltage change of the pixel electrode, and the display effect of the display panel 10 is improved. Other conditions herein include the spacing of the first electrode 112 and the second electrode 130, the material of the dielectric between the first electrode 112 and the second electrode 130, and the like.

Example two:

fig. 3 is a schematic structural diagram of a display panel 10 according to a second embodiment of the present application. As shown in fig. 3, in some embodiments, a dielectric layer 150 may also be included in the display panel 10.

The dielectric layer 150 is an insulating layer. The dielectric layer 150 may be located between the second electrode 130 and the third electrode 140. The second electrode 130, the dielectric layer 150, and the third electrode 140 are stacked, so that the second electrode 130 and the third electrode 140 are insulated by the dielectric layer 150. Typically, the dielectric of the dielectric layer 150 is solid. In the embodiment of the present application, the dielectric layer 150 is disposed between the second electrode 130 and the third electrode 140, which can increase a capacitance value of a first capacitor formed by coupling the second electrode 130 and the third electrode 140, thereby increasing voltage stability of the second electrode 130 and improving a display effect of the display panel 10.

In some specific embodiments, as shown in fig. 4, the display panel 10 further includes a glass substrate 160 and a plurality of color resists 172.

Specifically, the display panel 10 includes an array substrate 110, a liquid crystal layer 120, and a color film substrate (including a glass substrate 160, a plurality of color resists 172, and a second electrode 130). The structure of the array substrate 110 may be as described in the first embodiment, and is not described again. The color filter substrate may generally include a glass substrate 160, a plurality of color resistors 172, and a second electrode 130. The plurality of color resistors 172 includes equal numbers of red, blue, and green color resistors. Multiple color resists 172 may be located on the same surface of the glass substrate 160. The second electrode 130 is positioned such that the plurality of color resists 172 are positioned between the glass substrate 160 and the second electrode 130. In other words, the second electrode 130 is located on the side of the color resistor 172 away from the glass substrate 160. When the display panel 10 is formed, the color filter substrate may be aligned with the array substrate 110 to form a box. After the color film substrate and the array substrate 110 are aligned and boxed, the plurality of color resistors 172 and the second electrode 130 are located on one side of the glass substrate 160 close to the array substrate 110, the liquid crystal layer 120 is located between the color film substrate and the array substrate 110, and a sealant may be further disposed between the color film substrate and the array substrate 110 for fixing the liquid crystal layer 120 between the color film substrate and the array substrate 110. Generally, after the color filter substrate and the array substrate 110 are aligned and formed into a box, the positions of the color resistors 172 correspond to the positions of the first electrodes 112 one by one. That is, the color resistors 172 are also arranged in an array on the surface of the glass substrate 160. Generally, a black matrix 174 may be disposed between the plurality of color resists 172, and the black matrix 174 may be used to fill the gap between the plurality of color resists 172.

In the embodiment, between the plurality of color resistors 172 and the second electrode 130, there are also a second electrode 130 and a dielectric layer 150. In this case, as shown in fig. 4, the color filter substrate may include a glass substrate 160, a plurality of color resistors 172 (and black matrixes 174), a third electrode 140, a dielectric layer 150, and a second electrode 130, which are sequentially stacked from bottom to top in the paper direction. After the color filter substrate and the array substrate 110 are aligned and boxed, the plurality of color resistors 172, the third electrode 140, the dielectric layer 150 and the second electrode 130 are located on one side of the glass substrate 160 close to the array substrate 110.

Further, as shown in fig. 5, a flat layer 180 may be disposed between the color resistors 172 and the third electrode 140. Specifically, when a color filter substrate is manufactured, a plurality of color resists 172 and black matrices 174 may be manufactured on one surface of the glass substrate 160, and then the planarization layer 180 may be manufactured on the color resists 172 and the black matrices 174. The planarization layer 180 is an insulating layer, and the surface of the planarization layer 180 away from the glass substrate 160 is a planar surface. After the planarization layer 180 is obtained, the third electrode 140, the dielectric layer 150, and the second electrode 130 may be sequentially prepared on the planarization surface of the planarization layer 180 away from the glass substrate 160. Thus, the flatness of the third electrode 140 and the second electrode 130 can be increased, so that the voltages at the positions of the third electrode 140 and the second electrode 130 after being electrified are equal, and the display effect of the display panel 10 is further improved.

Example three:

fig. 6 is a schematic structural diagram of a first display panel 10 according to a third embodiment of the present application. As shown in fig. 6, in some embodiments, the display panel 10 further includes an array substrate 110 and a plurality of color resists 172.

Specifically, the display panel 10 includes an array substrate 110, a liquid crystal layer 120, and a color film substrate (including a glass substrate 160, a plurality of color resists 172, and a second electrode 130). The structure of the array substrate 110 may be as described in the first embodiment, and is not described again. The color filter substrate may generally include a glass substrate 160, a plurality of color resistors 172, and a second electrode 130. The plurality of color resistors 172 includes equal numbers of red, blue, and green color resistors. The multiple color resists 172 may be located on the same side of the glass substrate 160. The second electrode 130 is positioned such that the plurality of color resists 172 are positioned between the glass substrate 160 and the second electrode 130. In other words, the second electrode 130 is located on the side of the color resistor 172 away from the glass substrate 160. When the display panel 10 is formed, the color filter substrate may be aligned with the array substrate 110 to form a box. After the color film substrate and the array substrate 110 are aligned and boxed, the plurality of color resistors 172 and the second electrode 130 are located on one side of the glass substrate 160 close to the array substrate 110, the liquid crystal layer 120 is located between the color film substrate and the array substrate 110, and a sealant may be further disposed between the color film substrate and the array substrate 110 for fixing the liquid crystal layer 120 between the color film substrate and the array substrate 110. Generally, after the color filter substrate and the array substrate 110 are aligned and formed into a box, the positions of the color resistors 172 correspond to the positions of the first electrodes 112 one by one. That is, the color resistors 172 are also arranged in an array on the surface of the glass substrate 160. Generally, a black matrix 174 may be disposed between the plurality of color resists 172, and the black matrix 174 may be used to fill the gap between the plurality of color resists 172.

In the embodiment of the present application, a third electrode 140 is further disposed between the glass substrate 160 and the plurality of color resistors 172. In this case, as shown in fig. 6, the color filter substrate may include a glass substrate 160, a third electrode 140, a plurality of color resistors 172 (and black matrixes 174), and a second electrode 130, which are sequentially stacked from bottom to top in the paper direction. After the color filter substrate and the array substrate 110 are aligned and boxed, the third electrode 140, the color resistors 172 and the second electrode 130 are located on one side of the glass substrate 160 close to the array substrate 110. The color resistors 172 and the black matrix 174 are made of insulating materials. In this embodiment, the color resistor 172 and the black matrix 174 are used to replace the dielectric layer 150 in the third embodiment, so that the second electrode 130 and the third electrode 140 can be coupled to form the first capacitor in an insulated manner, and the number of layers of the color filter substrate can be reduced, thereby reducing the thickness of the display panel 10.

Further, as shown in fig. 7, a flat layer 180 may be disposed between the color resistors 172 and the second electrode 130. Specifically, when a color filter substrate is manufactured, the third electrode 140 may be manufactured on one surface of the glass substrate 160, and then the plurality of color resistors 172 and the black matrix 174 may be manufactured on the third electrode 140. After the color resist 172 and the black matrix 174 are obtained, a planarization layer 180 is prepared on the color resist 172 and the black matrix 174. The planarization layer 180 is an insulating layer, and the surface of the planarization layer 180 away from the glass substrate 160 is a planar surface. After the planarization layer 180 is obtained, the second electrode 130 can be prepared on the planarization surface of the planarization layer 180 away from the glass substrate 160. In the embodiment of the present application, since the third electrode 140 is directly formed on the glass substrate 160, the flatness of the third electrode 140 can be ensured, but the second electrode 130 formed on the color resists 172 and the black matrix 174 needs to be ensured by the flat surface of the flat layer 180. Thus, the flatness of the third electrode 140 and the second electrode 130 can be increased, so that the voltages at the positions of the third electrode 140 and the second electrode 130 after being electrified are equal, and the display effect of the display panel 10 is further improved.

The following explains in detail the different structures of the display device 20 according to the embodiment of the present application from the fourth embodiment to the seventh embodiment.

Fig. 8 is a schematic structural diagram of a display device 20 according to a fourth embodiment of the present application. Referring to fig. 8, the display device 20 includes a common voltage driver 210 and the display panel 10 provided in any one of the above embodiments. The common voltage driver 210 is used to output a common voltage VCOM. The common voltage VCOM may be a constant voltage dc. The common voltage driver 210 has an output terminal, and the output terminal of the common voltage driver 210 is connected to the second electrode 130, thereby outputting the common voltage VCOM to the second electrode 130.

Specifically, as shown in fig. 8, the display device 20 includes a display panel 10, a common voltage driver 210, a timing controller 220, a gate driver 230, and a source driver 240. The display panel 10 includes a plurality of first electrodes 112, a liquid crystal layer 120, and a second electrode 130. The plurality of first electrodes 112 are arranged in an array. The liquid crystal layer 120 includes a plurality of liquid crystal cells 122, and the plurality of liquid crystal cells 122 are located between the plurality of first electrodes 112 and the second electrode 130 one by one, so that when an electric field is formed between one of the plurality of first electrodes 112 and the second electrode 130, the liquid crystal cell 122 located between the one of the first electrodes 112 and the second electrode 130 is deflected under the action of the electric field. The display panel 10 further includes: and a third electrode 140. The second electrode 130 is located between the liquid crystal layer 120 and the third electrode 140, and the third electrode 140 and the second electrode 130 form a first capacitance. The third electrode 140 is connected to the predetermined voltage terminal V0 for inputting a predetermined voltage, wherein the predetermined voltage is not equal to the common voltage VCOM.

When the display device 20 is in operation, the timing controller 220 may acquire image data of an image to be displayed. The image data of the image to be displayed includes a target gray-scale value of each sub-pixel in the display panel 10. Each sub-pixel in the display panel 10 is composed of a first electrode 112, a liquid crystal cell 122, a second electrode 130 and a color resistor 172, and the actual gray level of each sub-pixel is determined by the magnitude of the data voltage inputted by the first electrode 112 of the sub-pixel. After the timing controller 220 obtains the image data of the image to be displayed, it outputs a timing control signal to the gate driver 230 and the source driver 240 according to the image data of the image to be displayed, and controls the common voltage driver 210 to output the common voltage VCOM to the second electrode 130. After acquiring the timing control signal, the gate driver 230 inputs a high level signal to each of the plurality of gate lines one by one according to the timing control signal, so that the plurality of gate lines output the high level signal one by one. The source driver 240 obtains the timing control signal, and outputs a data voltage to the plurality of source lines according to the timing control signal when a high level signal is input to each gate line. The magnitude of the data voltage output by the source driver 240 to each source line at a time depends on the target gray-scale value of each sub-pixel in the display panel 10. Thus, the actual gray scale value of each sub-pixel is equal to the target gray scale value, so that the display panel 10 displays the image to be displayed.

In some specific embodiments, the display panel 10 further includes a dielectric layer 150. The dielectric layer 150 is located between the second electrode 130 and the third electrode 140.

In some specific embodiments, the display panel 10 further includes a glass substrate 160 and a plurality of color resists 172. The color resistors 172 are located between the glass substrate 160 and the third electrode 140, and the third electrode 140 is located between the color resistors 172 and the dielectric layer 150.

In some specific embodiments, the display panel 10 further includes: a glass substrate 160 and a plurality of color resists 172. The third electrode 140 is located between the glass substrate 160 and the color resistors 172, and the color resistors 172 are located between the third electrode 140 and the second electrode 130.

In some embodiments, the third electrode 140 is in a plane parallel to the plane of the second electrode 130. The perpendicular projection of the second electrode 130 on the plane of the third electrode 140 is located within the coverage of the third electrode 140.

In the embodiment of the present application, the display device 20 includes the display panel 10 as in any one of the embodiments described above. In the display panel 10, the second electrode 130 and the third electrode 140 are coupled to form a first capacitor. When the display panel 10 is operated, the plurality of first electrodes 112 are used as pixel electrodes, the second electrode 130 to which the common voltage VCOM is inputted is used as a common electrode, and an electric field for driving the liquid crystal cell 122 to deflect is formed between the first electrodes 112 and the second electrode 130. Meanwhile, when the display panel 10 works, the third electrode 140 inputs a preset voltage, and the voltage on the second electrode 130 can be kept stable under the action of the first capacitor, so that the voltage of the second electrode 130 does not change along with the voltage change of the pixel electrode, and the display effect of the display panel 10 is improved.

In some embodiments, the display device 20 may further include a second capacitor C2 in addition to the common voltage driver 210 and the display panel 10 as described in any of the above embodiments. The first plate of the second capacitor C2 is connected to the second electrode 130, and the second plate of the second capacitor C2 is connected to the predetermined voltage terminal V0 for inputting the predetermined voltage. The predetermined voltage terminal V0 is the same as the predetermined voltage terminal V0 of the first embodiment. That is, in some embodiments, the predetermined voltage may be 0V, and the predetermined voltage terminal V0 is the ground GND of the display panel 10. In the embodiment of the present application, the second electrode 130 is connected to the preset voltage terminal V0 through the second capacitor C2, and when the display panel 10 works, the voltage on the second electrode 130 can also be kept stable under the effect of the second capacitor C2, so that the voltage of the second electrode 130 does not change with the voltage change of the pixel electrode, and the display effect of the display panel 10 is improved.

Example five:

in some embodiments, the display device 20 includes the common voltage driver 210, a display panel not including the third electrode 140, and the second capacitor C2. The common voltage driver 210 is used to output a common voltage VCOM. The common voltage VCOM may be a constant voltage dc. The common voltage driver 210 has an output terminal, and the output terminal of the common voltage driver 210 is connected to the second electrode 130, thereby outputting the common voltage VCOM to the second electrode 130.

In this embodiment, the display device 20 also includes a display panel, a common voltage driver 210, a timing controller 220, a gate driver 230, and a source driver 240. The difference between the fifth embodiment and the fourth embodiment is that: the display panel in the fifth embodiment does not include the third electrode 140. That is, the display panel includes a plurality of first electrodes 112, a liquid crystal layer 120, and a second electrode 130. The plurality of first electrodes 112 are arranged in an array. The liquid crystal layer 120 includes a plurality of liquid crystal cells 122, and the plurality of liquid crystal cells 122 are located between the plurality of first electrodes 112 and the second electrode 130 one by one, so that when an electric field is formed between one of the plurality of first electrodes 112 and the second electrode 130, the liquid crystal cell 122 located between the one of the first electrodes 112 and the second electrode 130 is deflected under the action of the electric field. The output terminal of the common voltage driver 210 is connected to the second electrode 130 such that the second electrode 130 inputs the common voltage VCOM. The first plate of the second capacitor C2 is connected to the second electrode 130, and the second plate of the second capacitor C2 is connected to the predetermined voltage terminal V0 for inputting the predetermined voltage. The predetermined voltage may be 0V, and the predetermined voltage terminal V0 is the ground GND.

When the display device 20 is in operation, the timing controller 220 may acquire image data of an image to be displayed. The image data of the image to be displayed comprises a target gray-scale value of each sub-pixel in the display panel. Each sub-pixel in the display panel is composed of a first electrode 112, a liquid crystal cell 122, a second electrode 130 and a color resistor 172, and the actual gray level of each sub-pixel is determined by the magnitude of the data voltage inputted by the first electrode 112 of the sub-pixel. After the timing controller 220 obtains the image data of the image to be displayed, it outputs a timing control signal to the gate driver 230 and the source driver 240 according to the image data of the image to be displayed, and controls the common voltage driver 210 to output the common voltage VCOM to the second electrode 130. After acquiring the timing control signal, the gate driver 230 inputs a high level signal to each of the plurality of gate lines one by one according to the timing control signal, so that the plurality of gate lines output the high level signal one by one. The source driver 240 obtains the timing control signal, and outputs a data voltage to the plurality of source lines according to the timing control signal when a high level signal is input to each gate line. The magnitude of the data voltage output by the source driver 240 to each source line at a time depends on the target gray-scale value of each sub-pixel in the display panel. Therefore, the actual gray-scale value of each sub-pixel is equal to the target gray-scale value, and the display panel displays the image to be displayed.

In the embodiment of the present application, the second electrode 130 is connected to the preset voltage terminal V0 through the second capacitor C2, and when the display panel works, the voltage on the second electrode 130 can be kept stable under the effect of the second capacitor C2, so that the voltage of the second electrode 130 does not change with the voltage change of the pixel electrode, and the display effect of the display panel is improved.

Example six:

fig. 9 is a schematic diagram illustrating region division of the display device 20 according to the fifth embodiment of the present application. As shown in fig. 9, the display device 20 includes a display area 22 and a non-display area 24. In some specific embodiments, the non-display area 24 is adjacent to the display area 22, and the non-display area 24 may be located at one side of the display area 22, for example, the non-display area 24 may be located below the display area 22 in the direction of the paper. In other embodiments, as shown in FIG. 9, the non-display area 24 is adjacent to the display area 22, and the non-display area 24 surrounds the display area 22.

In the embodiment of the present application, the pixel electrodes are arranged in an array at least in the display region 22, and the second electrode 130 and the liquid crystal layer 120 both cover at least the display region 22, so that the display region 22 can display images. The common voltage driver 210, the timing controller 220, the gate driver 230 and the source driver 240 are all located in the non-display region 24 to avoid affecting the normal display of the image in the display region 22.

Fig. 10 is a schematic structural diagram of a display device 20 according to a fifth embodiment of the present application. As shown in fig. 10, the display device 20 may include a plurality of second capacitors C2. The plurality of second capacitors C2 are all located in the non-display area 24. The second plate of each second capacitor C2 is connected to the preset voltage terminal V0 for inputting the preset voltage. The first plate of each second capacitor C2 is connected to the second electrode 130. Here, the display device 20 may further include a plurality of connection lines 212, and the number of the connection lines 212 is equal to the number of the second capacitors C2. The first end of each connecting line 212 is connected to the first plates of the plurality of second capacitors C2, and the second end of each connecting line 212 is connected to the second electrode 130. In other words, each connection line 212 is connected between the first plate of one second capacitor C2 and the second electrode 130. In the embodiment of the present application, the second ends of different connection lines 212 in the plurality of connection lines 212 are connected to different positions of the second electrode 130. Generally, the second ends of different connection lines 212 in the plurality of connection lines 212 are connected to the second electrode 130 at positions in an array. Thus, under the condition that the area of the second electrode 130 is large, the plurality of capacitors can keep the voltage of each position of the second electrode 130 relatively stable, thereby improving the display effect of the display panel 10.

Fig. 11 is a connection structure diagram of a connection line 212 and a second electrode 130 according to a fifth embodiment of the present disclosure. As shown in fig. 11, in some embodiments, only the second end of each connection line 212 is connected to the second electrode 130, and the connection lines 212 are insulated from the second electrode 130 except the second end. In this case, an insulator 214 may be provided between a portion of the connection line 212 on the second electrode 130 in a perpendicular projection to the plane of the second electrode 130 and the second electrode 130, so that only the second end of the connection line 212 is connected to the second electrode 130.

Fig. 12 is a diagram of another connection structure between the connection line 212 and the second electrode 130 according to the fifth embodiment of the present application. In other embodiments, as shown in fig. 12, a portion of each connection line 212, which is located on the second electrode 130 in a perpendicular projection of the plane where the second electrode 130 is located, is connected to the second electrode 130. In this case, the portion of the connection line 212 that is located on the second electrode 130 in a perpendicular projection to the plane in which the second electrode 130 is located is not provided with the insulator 214 between the second electrode 130 and the portion.

In some embodiments, as also shown in fig. 10, the plurality of first electrodes 112 have a spacing between perpendicular projections of the plane in which the second electrodes 130 lie. Each connection line 212 of the plurality of connection lines 212 is located within the space.

Specifically, in the embodiment shown in fig. 10, the second electrode 130 has a plurality of first projections 1122 arranged in an array. The first projection 1122 is a vertical projection of the first electrode 112 on the plane of the second electrode 130. As shown in fig. 10, there is a space between any two first projections 1122. A perpendicular projection of each connection line 212 of the plurality of connection lines 212 on the plane in which the second electrode 130 is located within the space. Thus, when the sub-pixels emit light, the connecting lines 212 do not refract the light emitted by the sub-pixels, so that the normal display of the image display panel 10 is not performed.

Example seven:

fig. 13 is a circuit configuration diagram of an internal circuit of a display device 20 according to a sixth embodiment of the present application. As shown in fig. 13, the internal circuit here refers to a circuit between the output terminal of the common voltage driver 210 and the second electrode 130. The display device 20 further includes: operational amplifier a and push-pull circuit 250.

Specifically, the operational amplifier a has a non-inverting input terminal, an inverting input terminal, and an output terminal. The push-pull circuit 250 has an input terminal and an output terminal. The non-inverting input terminal of the operational amplifier a is connected to the output terminal of the common voltage driver 210. The output terminal of the operational amplifier a is connected to the input terminal of the push-pull circuit 250, and the output terminal of the push-pull circuit 250 is connected to the second electrode 130 and the inverting input terminal of the operational amplifier a. Thus, the circuit structure constitutes a follower circuit including the push-pull circuit 250. The circuit structure can also maintain the voltage of the second electrode 130 stable. When the circuit structure and the second capacitor C2 exist in the display device 20 at the same time, or the circuit structure and the third electrode 140 exist in the display device 20 at the same time, the voltage of the second electrode 130 can be maintained stable, and the heat generation of the operational amplifier a and the push-pull circuit 250 can be reduced. When this circuit structure and the second capacitor C2 exist in the display device 20 at the same time, the circuit structure is as shown in fig. 14.

In some embodiments, the push-pull circuit 250 is formed by two transistors of different polarities connected and the parameters of the two transistors are the same. For example, the push-pull circuit 250 may be formed by connecting an N-type MOS field effect transistor and a P-type MOS field effect transistor. Alternatively, the push-pull circuit 250 may be formed by connecting an NPN transistor and a PNP transistor. In the embodiment shown in fig. 13 and 14, the push-pull circuit 250 is formed by connecting a transistor Q1 and a transistor Q2, wherein the transistor Q1 is an NPN-type transistor, and the transistor Q2 is a PNP-type transistor. The base electrode of the triode Q1 and the base electrode of the triode Q2 are both connected with the output end of the operational amplifier A, the collector electrode of the triode Q1 is connected with the voltage source VCC, the emitter electrode of the triode Q1 and the emitter electrode of the triode Q2 are both connected with the second electrode 130 and the inverting input end of the operational amplifier A, and the collector electrode of the triode Q2 is connected with the ground wire GND.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A display panel, comprising: a plurality of first electrodes, a liquid crystal layer, and a second electrode;

the plurality of first electrodes are arranged in an array;

characterized in that, the display panel still includes: a third electrode;

2. The display panel of claim 1, wherein the display panel further comprises: a dielectric layer;

3. The display panel of claim 2, wherein the display panel further comprises: a glass substrate and a plurality of color resists;

4. The display panel of claim 1, wherein the display panel further comprises: a glass substrate and a plurality of color resists;

5. The display panel according to any one of claims 1 to 4, wherein a plane in which the third electrode is located is parallel to a plane in which the second electrode is located;

6. A display device comprising a common voltage driver and the display panel according to any one of claims 1 to 5;

7. The display device of claim 6, further comprising: a second capacitor;

8. A display device as claimed in claim 6 or 7, characterized in that the display device comprises a display area and a non-display area adjoining the display area; the second electrode at least covers the display area, and the common voltage driver is positioned in the non-display area;

9. The display device of claim 8, wherein the plurality of first electrodes have a spacing between orthogonal projections of a plane in which the second electrodes lie, the plurality of connecting lines being located within the spacing.

10. The display device of claim 6, further comprising: an operational amplifier and a push-pull circuit;