CN114205181B - Closed loop network and automatic routing method thereof - Google Patents

Closed loop network and automatic routing method thereof Download PDF

Info

Publication number
CN114205181B
CN114205181B CN202111440919.9A CN202111440919A CN114205181B CN 114205181 B CN114205181 B CN 114205181B CN 202111440919 A CN202111440919 A CN 202111440919A CN 114205181 B CN114205181 B CN 114205181B
Authority
CN
China
Prior art keywords
node
clock
data
input
fpga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111440919.9A
Other languages
Chinese (zh)
Other versions
CN114205181A (en
Inventor
宋文生
覃勇
曹伟军
柯有强
程鲲
蒙梁
蒋鹏宇
孙晓亭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 34 Research Institute
Original Assignee
CETC 34 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 34 Research Institute filed Critical CETC 34 Research Institute
Priority to CN202111440919.9A priority Critical patent/CN114205181B/en
Publication of CN114205181A publication Critical patent/CN114205181A/en
Application granted granted Critical
Publication of CN114205181B publication Critical patent/CN114205181B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/22—Alternate routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/422—Synchronisation for ring networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/437—Ring fault isolation or reconfiguration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/16—Multipoint routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/28—Routing or path finding of packets in data switching networks using route fault recovery

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The invention discloses a closed loop network and an automatic routing method thereof, wherein the closed loop network comprises n nodes connected end to end; each node consists of an FPGA, m transmitting units and m receiving units; the input ends of the m receiving units respectively form m input ends of the node, and the output ends of the m transmitting units respectively form m output ends of the node; the output ends of the m receiving units are connected with the input end of the FPGA, and the input ends of the m transmitting units are connected with the output end of the FPGA. Because the link data is automatically selected, when a certain node and a certain loop fail, the system can automatically extract data from other nodes and loops for transmission, and in the limit, as long as a clear link exists in the system, the data of all nodes in the system can be normally transmitted, thereby greatly improving the stability and reliability of the system.

Description

Closed loop network and automatic routing method thereof
Technical Field
The invention relates to the technical field of underwater information networks, in particular to a closed loop network and an automatic routing method thereof.
Background
With the development of underwater information networks and national ocean strategies, various underwater detection, acquisition, communication platforms, underwater navigation and countermeasure platform phase sequence construction are carried out, and the optical fiber has the advantages of light weight, good confidentiality, large transmission capacity and the like, and is increasingly applied to the underwater information networks. However, due to the inherent nature of the underwater information network, the maintenance costs and difficulties are much higher, even orders of magnitude, than those of the surface equipment, and thus the reliability and stability requirements for the signals are also increased.
Disclosure of Invention
Aiming at the transmission requirement of an underwater information network with high requirements on signal transmission reliability and stability, the invention provides a closed loop network and an automatic routing method thereof.
In order to solve the problems, the invention is realized by the following technical scheme:
a closed loop network comprising n nodes. Each node consists of an FPGA, m transmitting units and m receiving units; the output ends of the m receiving units are connected with the input end of the FPGA, and the input ends of the m transmitting units are connected with the output end of the FPGA; the input ends of the m receiving units respectively form m input ends of the node, and the output ends of the m transmitting units respectively form m output ends of the node. n nodes are connected end to end, namely: the 1 st node
Figure BDA0003383327230000011
The input ends are respectively connected with the +.>
Figure BDA0003383327230000012
The 1 st node>
Figure BDA0003383327230000013
The output ends are respectively connected with the nth node
Figure BDA0003383327230000014
The 1 st input terminal>
Figure BDA0003383327230000015
The input terminal is connected with the No. 2 node>
Figure BDA0003383327230000016
The 1 st node>
Figure BDA0003383327230000017
The output terminal is connected with the +.2 of the 2 nd node>
Figure BDA0003383327230000018
A plurality of input terminals; the i-th node->
Figure BDA0003383327230000019
The input ends are respectively connected with the (th) of the (i-1) th node>
Figure BDA00033833272300000110
The output end of the ith node
Figure BDA00033833272300000111
The (th) output ends are respectively connected with the (th) of the (i+1) th nodes>
Figure BDA00033833272300000112
The input end of the ith node
Figure BDA00033833272300000113
The input terminal is connected with the (i) th node of the (i-1) th node>
Figure BDA00033833272300000114
The (th) of the (th) node of the (th) output terminal>
Figure BDA00033833272300000115
The (th) of the (i+1) th node is connected to the (output) terminal>
Figure BDA00033833272300000116
And a plurality of input terminals. The i=2, 3, …, n-1, n is a positive integer greater than or equal to 2; m is an even number of 2 or more.
In the scheme, each receiving unit is internally provided with a serial-parallel conversion module and a CDR module; the serial-parallel conversion module is connected with the input end of the CDR module and forms the input end of the receiving unit; the output end of the serial-parallel conversion module forms one path of output end of the receiving unit, and the output end of the CDR module forms the other path of output end of the receiving unit.
In the scheme, a clock receiving and transmitting module and a data selecting module are arranged in the FPGA; the input end of the clock receiving and transmitting module is connected with the output ends of the CDR modules of all the receiving units in the node, and the input end of the data selecting module is connected with the output ends of the serial-parallel conversion modules of all the receiving units in the node; the output end of the data selection module is connected with the input ends of all the transmitting units in the node.
In the scheme, in the same node, the output end of the receiving unit is connected with the input end of the FPGA in a parallel mode, and the input end of the transmitting unit is connected with the output end of the FPGA in a parallel mode.
In the above scheme, between adjacent nodes, the input end of the receiving unit is connected with the output end of the transmitting unit in a serial mode.
The automatic routing method of the closed loop network realized by the closed loop network comprises the following steps:
the receiving unit of the current node divides the signal transmitted by the transmitting unit of the previous node into two paths: one path of signal is recovered by the CDR module of the receiving unit and the state thereof is input to the clock receiving and transmitting module of the FPGA; one path of signal is transmitted to a data selection module of the FPGA after the data is recovered by a serial-parallel conversion module of the receiving unit and the state of the signal is transmitted to the FPGA;
the clock receiving and transmitting module of the FPGA of the current node selects one clock from all clocks and state information thereof as a working clock of the current node by utilizing a set clock selection strategy for the clocks and state information thereof sent by all receiving units; the data selection module of the FPGA of the current node utilizes a set routing strategy for the data and the state information of the data sent by each receiving unit to send the data from one transmitting unit of the current node to one receiving unit of the subsequent node.
The preferred clock selection strategy is inverse clock priority, outer ring priority; namely: the clock of the reverse time Zhong Waihuan link is preferentially selected; secondly, the clock of the reverse clock inner loop link is adopted; again the clock of the clockwise outer loop link; and finally the clock of the inner loop link clockwise.
The preferred routing strategy is loop-first, co-directional-first, i.e.: preferentially selecting data with the same direction and same as the signal transmission loop; secondly, data in different loops and in the same direction; again, the data is in the same loop and in different directions; and finally, data with different loops and different directions.
Compared with the prior art, the invention has the following characteristics:
1. compared with a point-to-point transmission mode, the method adopts a mode of uploading signals step by step in a closed loop, so that the link bandwidth is utilized to the greatest extent, the requirement of a system on a transmission link is reduced, and the difficulty and cost of system laying are reduced.
2. Because the link data is automatically selected, when a certain node and a certain loop fail, the system can automatically extract data from other nodes and loops for transmission, and in the limit, as long as a clear link exists in the system, the data of all nodes in the system can be normally transmitted, thereby greatly improving the stability and reliability of the system.
Drawings
FIG. 1 is a schematic block diagram of a closed loop network;
fig. 2 is a functional block diagram of a node.
Detailed Description
The present invention will be further described in detail with reference to specific examples in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1, a closed loop network includes n nodes connected end to end. Each node comprises m inputs and m outputs. The 1 st node
Figure BDA0003383327230000031
The input ends are respectively connected with the +.>
Figure BDA0003383327230000032
The 1 st node>
Figure BDA0003383327230000033
The output ends are respectively connected with the (th) of the (n) th node>
Figure BDA0003383327230000034
The 1 st input terminal>
Figure BDA0003383327230000035
The input terminal is connected with the No. 2 node>
Figure BDA0003383327230000036
The 1 st output end
Figure BDA0003383327230000037
The output terminal is connected with the +.2 of the 2 nd node>
Figure BDA0003383327230000038
A plurality of input terminals; the i-th node->
Figure BDA0003383327230000039
The input ends are respectively connected with the (th) of the (i-1) th node>
Figure BDA00033833272300000310
The (th) of the (th) node of the (th) output terminal>
Figure BDA00033833272300000311
The (th) output ends are respectively connected with the (th) of the (i+1) th nodes>
Figure BDA00033833272300000312
The i-th node of the input terminal>
Figure BDA00033833272300000313
The input terminal is connected with the (i) th node of the (i-1) th node>
Figure BDA00033833272300000314
The (th) of the (th) node of the (th) output terminal>
Figure BDA00033833272300000315
The (i+1) th node is connected to the output end
Figure BDA00033833272300000316
And a plurality of input terminals. Between adjacent nodes, the input end of the receiving unit and the output end of the transmitting unit are connected in a serial mode. Wherein i=2, 3, …, n-1, n is a positive integer of 2 or more; m is an even number of 2 or more, and in this embodiment, n=20 and m=4.
Referring to fig. 2, each node is composed of an FPGA, m transmitting units, and m receiving units. FGPA chip logic unit is greater than 43k, slice is greater than 6.8k, IO port number is greater than 300, GTP transceiver number is greater than 4 pairs, signal processing capability is greater than 200MHz, clock frequency is 30 MHz-150 MHz, and frequency stability is kept within 10ppm after multistage transmission. Each receiving unit is internally provided with a serial-parallel conversion module and a CDR (clock recovery) module; the serial-parallel conversion module is connected with the input end of the CDR module and forms the input end of the receiving unit; the output end of the serial-parallel conversion module forms one path of output end of the receiving unit, and the output end of the CDR module forms the other path of output end of the receiving unit. A clock receiving and transmitting module and a data selecting module are arranged in the FPGA; the input end of the clock receiving and transmitting module is connected with the output ends of the CDR modules of all the receiving units in the node, and the input end of the data selecting module is connected with the output ends of the serial-parallel conversion modules of all the receiving units in the node; the output end of the data selection module is connected with the input ends of all the transmitting units in the node. In the same node, the output end of the receiving unit is connected with the input end of the FPGA in a parallel mode, and the input end of the transmitting unit is connected with the output end of the FPGA in a parallel mode. The input ends of the m receiving units respectively form m input ends of the node, and the output ends of the m transmitting units respectively form m output ends of the node.
The automatic routing method for the closed loop network, which is realized by the closed loop network, specifically comprises the following steps:
the receiving unit of the current node divides the signal transmitted by the transmitting unit of the previous node into two paths: one path of signal is recovered by the CDR module of the receiving unit and the state thereof is input to the clock receiving and transmitting module of the FPGA; and one path of signal is transmitted to the data selection module of the FPGA after the data is recovered by the serial-parallel conversion module of the receiving unit and the state of the signal is transmitted to the data selection module of the FPGA.
The clock receiving and transmitting module of the FPGA of the current node selects one clock from all clocks and state information thereof as the working clock of the current node by utilizing a set clock selection strategy for the clocks and state information thereof sent by all receiving units. In this implementation, the clock selection policy is inverse clock priority, outer ring priority; namely: the clock of the reverse time Zhong Waihuan link is preferentially selected; secondly, the clock of the reverse clock inner loop link is adopted; again the clock of the clockwise outer loop link; and finally the clock of the inner loop link clockwise.
The data selection module of the FPGA of the current node utilizes a set routing strategy for the data and the state information of the data sent by each receiving unit to send the data from one transmitting unit of the current node to one receiving unit of the subsequent node. In this implementation, the routing policy is loop-first, co-directional-first, i.e.: preferentially selecting data with the same direction and same as the signal transmission loop; secondly, data in different loops and in the same direction; again, the data is in the same loop and in different directions; and finally, data with different loops and different directions.
Each node automatically performs data and channel selection according to signals of the front node and the rear node connected with the node, and reliable transmission of the signals is completed. The receiving unit of each node receives a signal sent by a previous node of the current loop, automatically judges the data and the state of the previous node and the current node, and outputs the data and the state information thereof to the FPGA; the FPGA automatically selects data to transmit to the transmitting unit according to a routing strategy according to the data of all loops connected with the current node and the state information thereof, and the transmitting unit is responsible for converting the data transmitted by the FPGA into serial high-speed data and transmitting the serial high-speed data to the next node. Each node receiving unit receives a signal sent by a previous node of the current loop, recovers a clock and the state thereof from data by adopting a CDR technology, and outputs the clock and the state information thereof to the FPGA; according to the clocks and state information of all loops connected with the current node, the FPGA automatically selects one clock as the working clock of the node according to a clock selection strategy, and the clock is used as a master clock for subsequent data processing.
The following describes the working procedure of the present invention in detail by taking the 2 nd node as the current node:
the signal transmitted in the ring 1 direction of the first receiving unit of the current node is transmitted from one of the transmitting units of the previous node (1 st node), and is split into two paths in the first receiving unit of the current node: one path of the clock is recovered by a CDR module of the first receiving unit and the state of the clock is input to a clock receiving and transmitting module of the FPGA; and one path of first data and state are recovered through a serial-parallel conversion module of the first receiving unit and are transmitted to a data selection module of the FPGA.
The signal transmitted in the loop 2 direction of the second receiving unit of the current node is transmitted from one transmitting unit of the previous node (1 st node), and is split into two paths in the second receiving unit of the current node: one path of the clock is recovered by a CDR module of the second receiving unit and the state of the second clock is input to a clock receiving and transmitting module of the FPGA; and one path of the second data is recovered through the serial-parallel conversion module of the second receiving unit, and the state of the second data is transmitted to the data selection module of the FPGA.
The signal transmitted in the ring 3 direction of the third receiving unit of the current node is transmitted from one transmitting unit of the following node (3 rd node), and is split into two paths in the third receiving unit of the current node: one path of the clock is recovered by a CDR module of the third receiving unit and the state of the third clock is input to a clock receiving and transmitting module of the FPGA; and one path of third data is recovered through the serial-parallel conversion module of the third receiving unit, and the state of the third data is transmitted to the data selection module of the FPGA.
The signal transmitted in the ring 4 direction of the fourth receiving unit of the current node is transmitted from one transmitting unit of the following node (3 rd node), and is split into two paths in the fourth receiving unit of the current node: one path of the clock is recovered by a CDR module of the fourth receiving unit, and the state of the clock is input to a clock receiving and transmitting module of the FPGA; and one path of the fourth data is recovered through the serial-parallel conversion module of the fourth receiving unit, and the state of the fourth data is transmitted to the data selection module of the FPGA.
The clock transceiver module of the FPGA of the current node selects one clock from the 4 clocks and the state information as the working clock of the current node according to the clocks and the state information provided by the 4 receiving units and the set clock selection strategy. The clock is extracted from the data of the last node in each loop direction and is synchronous with the data of the last node, and all the link nodes trace back step by step to the first node, so that the clocks used by all the nodes on the links are synchronous clocks, and the consistency of the system clock signals is ensured. The clock selection strategy is: reverse clock priority, outer ring priority; namely: the reverse time Zhong Waihuan link clock (ring 1), followed by the reverse time Zhong Nahuan clock (ring 2), followed by the clockwise outer ring clock (ring 3), and finally the clockwise inner ring clock (ring 4) is preferred.
The data selection module of the FPGA of the current node selects one loop from the input data to restore the data and the data of the node together to be transmitted to one of the transmitting units of the adjacent nodes in parallel according to the data state information provided by each receiving unit and the set data selection strategy. The transmitting unit receives the parallel data transmitted by the data selecting module, and transmits the parallel data to the adjacent node through a high-speed serial port after parallel/serial conversion and 8B/10B coding are completed. The signal transmitted by each loop of the current node to the next level node is related to the routing strategy of the data selection module. The same strategy is adopted for each loop data selection: the data selection refers to the upper-level link state, firstly, the loop states (the same-direction same-ring mark S1, the same-direction different-ring mark S3, the different-direction same-ring mark S2, namely the different-direction different-ring mark S4) of four directions connected with the node are judged, and the data needing to be relayed to the next node is selected according to the different link states. The data selection strategy is: loop priority, co-directional priority, i.e.: the data with the same direction as the signal transmission loop is preferentially selected, then the data with different loops and the same direction, and the data with the same loops and the different directions are selected, and finally the data with different directions of the different loops are selected, namely the priorities are S1, S3, S2 and S4. After the data selection is completed, the acquired data of the local terminal and the data are packaged together and sent from four directions. And the reliable transmission of the collected data signals and the status signals of each node is completed by adopting a step-by-step uploading mode. The routing strategy has the advantages that under the condition that four loops of the system are normal, the four loops transmit the same, but the transmission links of the four loops are not crossed, and the data of the four nodes can be checked and compared by the final data aggregation unit, so that the subsequent data analysis is facilitated.
It should be noted that, although the examples described above are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, are considered to be within the scope of the invention as claimed.

Claims (7)

1. A closed loop network comprising n nodes; each node consists of an FPGA, m transmitting units and m receiving units; the output ends of the m receiving units are connected with the input end of the FPGA, and the input ends of the m transmitting units are connected with the output end of the FPGA; the input ends of the m receiving units respectively form m input ends of the node, and the output ends of the m transmitting units respectively form m output ends of the node;
n nodes are connected end to end, namely: the 1 st node
Figure FDA0004041133550000011
The input ends are respectively connected with the nth node
Figure FDA0004041133550000012
The 1 st node>
Figure FDA0004041133550000013
The output ends are respectively connected with the (th) of the (n) th node>
Figure FDA0004041133550000014
The 1 st input terminal>
Figure FDA0004041133550000015
The input terminal is connected with the No. 2 node>
Figure FDA0004041133550000016
The 1 st node>
Figure FDA0004041133550000017
The output terminal is connected with the +.2 of the 2 nd node>
Figure FDA0004041133550000018
A plurality of input terminals; the i-th node->
Figure FDA0004041133550000019
The input ends are respectively connected with the (th) of the (i-1) th node>
Figure FDA00040411335500000110
The (th) of the (th) node of the (th) output terminal>
Figure FDA00040411335500000111
The (th) output ends are respectively connected with the (th) of the (i+1) th nodes>
Figure FDA00040411335500000112
The i-th node of the input terminal>
Figure FDA00040411335500000113
The input terminal is connected with the (i) th node of the (i-1) th node>
Figure FDA00040411335500000114
The (th) of the (th) node of the (th) output terminal>
Figure FDA00040411335500000115
The (i+1) th node is connected to the output end
Figure FDA00040411335500000116
A plurality of input terminals;
the receiving unit of the current node divides the signal transmitted by the transmitting unit of the previous node into two paths: one path of signal is recovered by the CDR module of the receiving unit and the state thereof is input to the clock receiving and transmitting module of the FPGA; one path of signal is transmitted to a data selection module of the FPGA after the data is recovered by a serial-parallel conversion module of the receiving unit and the state of the signal is transmitted to the FPGA;
the clock receiving and transmitting module of the FPGA of the current node selects one clock from all clocks and state information thereof as a working clock of the current node by utilizing a set clock selection strategy for the clocks and state information thereof sent by all receiving units; the data selection module of the FPGA of the current node utilizes a set routing strategy for the data and the state information of the data sent by each receiving unit to send the data from one transmitting unit of the current node to one receiving unit of the next node;
the i=2, 3, …, n-1, n is a positive integer greater than or equal to 2; m is an even number of 2 or more.
2. The closed loop network of claim 1, wherein each receiving unit is provided with a serial-parallel conversion module and a CDR module; the serial-parallel conversion module is connected with the input end of the CDR module and forms the input end of the receiving unit; the output end of the serial-parallel conversion module forms one path of output end of the receiving unit, and the output end of the CDR module forms the other path of output end of the receiving unit.
3. The closed loop network according to claim 2, wherein a clock transceiver module and a data selection module are arranged in the FPGA; the input end of the clock receiving and transmitting module is connected with the output ends of the CDR modules of all the receiving units in the node, and the input end of the data selecting module is connected with the output ends of the serial-parallel conversion modules of all the receiving units in the node; the output end of the data selection module is connected with the input ends of all the transmitting units in the node.
4. The closed loop network of claim 1, wherein in the same node, the output terminal of the receiving unit is connected to the input terminal of the FPGA in a parallel manner, and the input terminal of the transmitting unit is connected to the output terminal of the FPGA in a parallel manner.
5. A closed loop network according to claim 1, wherein between adjacent nodes, the input of the receiving unit and the output of the transmitting unit are connected in series.
6. A closed loop network according to claim 1 wherein the clock selection strategy is inverse clock priority, outer loop priority; namely: the clock of the reverse time Zhong Waihuan link is preferentially selected; secondly, the clock of the reverse clock inner loop link is adopted; again the clock of the clockwise outer loop link; and finally the clock of the inner loop link clockwise.
7. A closed loop network according to claim 1, wherein the routing policy is loop-first, co-directional-first, i.e.: preferentially selecting data with the same direction and same as the signal transmission loop; secondly, data in different loops and in the same direction; again, the data is in the same loop and in different directions; and finally, data with different loops and different directions.
CN202111440919.9A 2021-11-30 2021-11-30 Closed loop network and automatic routing method thereof Active CN114205181B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111440919.9A CN114205181B (en) 2021-11-30 2021-11-30 Closed loop network and automatic routing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111440919.9A CN114205181B (en) 2021-11-30 2021-11-30 Closed loop network and automatic routing method thereof

Publications (2)

Publication Number Publication Date
CN114205181A CN114205181A (en) 2022-03-18
CN114205181B true CN114205181B (en) 2023-05-12

Family

ID=80649697

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111440919.9A Active CN114205181B (en) 2021-11-30 2021-11-30 Closed loop network and automatic routing method thereof

Country Status (1)

Country Link
CN (1) CN114205181B (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3285138B2 (en) * 1997-10-20 2002-05-27 富士通株式会社 Transmission device in ring network
US6331905B1 (en) * 1999-04-01 2001-12-18 The Trustees Of Columbia University In The City Of New York Network switch failure restoration
CN100361099C (en) * 2004-01-15 2008-01-09 武汉理工大学 Fibre optical CAN bus self-healing ring network interface device
JP4776374B2 (en) * 2005-12-27 2011-09-21 株式会社東芝 Redundant supervisory control system and redundant switching method for the same system
CN100461736C (en) * 2007-03-26 2009-02-11 华为技术有限公司 Resilient packet ring business board, system and clock information selecting method
CN106656716B (en) * 2016-12-28 2019-08-20 中国人民解放军海军工程大学 Ring network topology structure with common clock
CN108449154B (en) * 2018-02-26 2020-02-28 柳州达迪通信技术股份有限公司 Clock system and clock self-healing method for synchronous network ring network

Also Published As

Publication number Publication date
CN114205181A (en) 2022-03-18

Similar Documents

Publication Publication Date Title
US7242861B2 (en) Optical path cross-connect and optical wavelength multiplexing diversity communication system using the same
CN101826919B (en) Mixed type passive optical network structure and method for positioning and restoring faults thereof
US7761006B2 (en) Method for designing optical network, and computer readable medium
CN102013922B (en) Information processing method as well as optical communication device and system in optical network
CN104244118A (en) Modularization interconnecting network, establishing method and application based on arrayed waveguide gratings
CN107104737B (en) A kind of node device port expansion system and method based on optical fiber interconnections
JP5786492B2 (en) COMMUNICATION DEVICE, COMMUNICATION CIRCUIT, AND COMMUNICATION METHOD
Shi et al. Hierarchical self-healing rings
CN109361473A (en) High-speed high capacity photonic transport networks
CN105187255A (en) Fault analysis method, fault analysis device and server
CN112788446A (en) Optical transmission system and optical transmission method applied to submarine observation network
CN102946305A (en) Method and equipment for synchronizing link state protocol data unit (LSP)
CN114205181B (en) Closed loop network and automatic routing method thereof
CN110062303B (en) Mesh network-based self-adaptive high-capacity cross optical communication equipment architecture
CN201674613U (en) Hybrid passive optical network structure with protection function
RU2543612C2 (en) Load cross-switching processing method for optical transport network (otn) equipment and corresponding otn equipment
CN1983881B (en) Passive optical network media access controller assisted clock recovery
CN101547054B (en) Data receiving device of parallel optical inter-connected system based on programmable device and method thereof
CN113722266B (en) Bridge, acceleration equipment interconnection system and data acceleration processing method
US6393019B1 (en) Matrix switch
CN112383348B (en) Time-sharing multiplexing time-frequency transmission method based on optical fiber ring network system
CN101222405A (en) Module for fast recovering looped network redundancy and its use method
EP0843434A2 (en) Line interface circuit for wideband transmission
Gerla et al. A guide to data communications: high-speed local-area networks
CN114499666B (en) Double-ring self-healing underwater optical fiber network signal transmission system and method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant