CN114203907A - Gate surrounding transistor based on CNT array channel and preparation method - Google Patents

Gate surrounding transistor based on CNT array channel and preparation method Download PDF

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CN114203907A
CN114203907A CN202111486399.5A CN202111486399A CN114203907A CN 114203907 A CN114203907 A CN 114203907A CN 202111486399 A CN202111486399 A CN 202111486399A CN 114203907 A CN114203907 A CN 114203907A
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layer
substrate
insulating layer
electrode
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韩拯
陈茂林
张静
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Shanxi University
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Shanxi University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors

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Abstract

The invention belongs to the technical field of micro-nano devices, and particularly relates to a grid surrounding type transistor based on a CNT array channel and a preparation method thereof. According to the invention, a high-quality semiconductor CNT array is prepared directly on a vertical silicon step template by adopting a bottom-up mode and a purification and self-assembly method, and is used as a channel material, and then on the basis, the CNT FinFET with the sub-nanometer fin width is constructed by combining the technologies of anisotropic dry etching, selective wet etching, micro-nano processing and the like. And the metal Pd or Sc is respectively adopted to realize p-type or n-type ohmic contact with the CNT, so that p-type and n-type CNT FinFETs can be prepared, and an inverter is easy to construct.

Description

Gate surrounding transistor based on CNT array channel and preparation method
Technical Field
The invention belongs to the technical field of micro-nano devices, and particularly relates to a grid surrounding type transistor based on a CNT array channel and a preparation method thereof.
Background
The birth of the transistor lays a foundation for the prosperous development of integrated circuits, microprocessors and electronic equipment, and the birth of the Moore's law pushes the transistor to the prosperous development. Following the development of moore's law, the integrated circuit industry has rapidly developed with the continued reduction in transistor size using semiconductor processing techniques. However, as the size of the transistor is continuously reduced, short channel effects, increased heat generation power consumption, physical limitations of the process technology, and the like are also generated. In order to continue moore's law, researchers have developed transistor structures that start with an initial planar transistor, go to a fin field effect transistor (FinFET), and then to a gate-wrap-around field effect transistor (GAAFET), which, in contrast, has a gate that wraps around the channel material and has greater gate controllability over the channel.
In addition, breaking through the traditional silicon-based material system, preparing a new-structure field effect transistor by applying a new material system is also an important research direction of researchers, and there have been many advances at present, such as people using a single-layer extreme two-dimensional material as a FinFET of a channel, and at the same time, successfully preparing a FinFET array (Chen M L, Sun X, Liu H, et al.a FinFET with one atomic layer channel [ J ]. Nature communications,2020,11 FinFET (1):1-7.), and a carbon nanotube three-dimensional structure based on an embedded gate fin using a two-dimensional semimetal as a source and drain, described in chinese patent CN 110416308B.
Single-walled Carbon Nanotubes (CNTs), which are a new type of carbon nanomaterial, are rolled from graphene, have high mobility, high carrier concentration, high thermal conductivity, high strength, etc., and have 5-10 times advantages over the speed and power consumption of silicon-based devices, and furthermore, high-purity and high-density CNT arrays can be prepared on 4-inch silicon wafers by CNT deposition techniques (Liu L, Han J, Xu L, et al, aligned, high-density semiconducting carbon nanotubes arrays for high-performance electronics [ J ] Science,2020,368(6493): 850-.
Disclosure of Invention
The invention aims to break through the framework of a traditional silicon-based material system, firstly provides a preparation method of a gate surrounding type transistor based on a CNT array channel, and further constructs a CMOS inverter by preparing p-type and n-type CNT FinFETs (carbon nanotube field effect transistors) by adopting different contact metals.
In order to achieve the purpose, the invention adopts the following technical scheme:
a gate-around transistor based on a CNT array channel comprises a substrate, a channel, a source electrode, a drain electrode, an insulating layer, a dielectric layer and a gate;
the substrate is provided with a channel, a source electrode and a drain electrode are deposited at the front end and the rear end of the channel, insulating layers are deposited on the surfaces of the channel, the source electrode and the drain electrode, dielectric layers are deposited on the surfaces of the insulating layers and the substrate, and a grid electrode is deposited in the middle of the dielectric layers;
the channel is a vertical standing single-layer high-density CNT parallel array, the insulating layer and the dielectric layer are insulating material films, the gate is a metal or metallic CNT film, and the source electrode and the drain electrode are metals.
A preparation method of the gate surrounding transistor based on the CNT array channel comprises the following steps:
(1) processing the substrate by adopting a micro-nano processing technology to obtain a vertical step with controllable height, then depositing an insulating layer on the surface of the step, then removing the insulating layer in a plane area, and reserving the insulating layer on the side wall of the step;
(2) preparing a single-layer semiconductor CNT array film which is arranged in sequence and uniform on the substrate by adopting a CNT liquid phase interface purification and self-assembly method based on the step (1);
(3) defining the areas of a source electrode and a drain electrode, and depositing metal electrodes on the front area and the rear area of the single-layer semiconductor CNT array film on the substrate to be used as the source electrode and the drain electrode;
(4) depositing an insulating layer on the surface of the sample in the step (3);
(5) removing the insulating layer and the single-layer semiconductive CNT array film in the plane area and reserving the single-layer semiconductive CNT array film and the insulating layer in the side wall area by adopting a plane removal process to obtain a vertically-standing directionally-arranged semiconductive CNT array;
(6) removing the vertical steps by adopting a selective wet etching process to obtain a semiconductor CNT array, a source electrode and a drain electrode which stand vertically and are clamped by an insulating layer;
(7) depositing a dielectric layer on the surface of the obtained sample based on the step (6) for encapsulating the single-layer semiconductor CNT array, and simultaneously encapsulating the source electrode and the drain electrode;
(8) and defining a gate region, and depositing a gate to form the transistor.
Further, there are two specific methods for obtaining the height-controllable vertical step: the first method comprises the steps that an SOI type substrate is used, exposure development is carried out on the surface of the substrate by using an electron beam exposure technology or a photoetching technology to obtain a single pattern, then the etching technology is used for removing the top layer material of the substrate in an exposure pattern area, and a middle insulating layer and a bottom layer of the substrate are reserved to obtain a vertical step; in the second method, an electron beam exposure technology or a photolithography technology is used for exposure and development on the surface of an insulating substrate to obtain a single pattern, and then an evaporation process is used for obtaining the vertical metal step.
Further, the insulating layer is a high dielectric constant material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, tantalum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium silicide, zirconium aluminide, tin oxide, zirconium oxide, titanium oxide, aluminum oxide; the deposited insulating layer adopts any one of magnetron sputtering, a chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method, thermal evaporation, electron beam evaporation and a low-pressure chemical vapor deposition method.
Further, the specific method for defining the source electrode region and the drain electrode region in the step (3) is as follows: exposing and developing the surface of the semiconductor CNT array region by using an electron beam exposure technology or a photoetching technology, and defining a source electrode region and a drain electrode region; the deposited metal electrode adopts any one of electron beam evaporation, magnetron sputtering, CVD, ALD, physical vapor deposition, thermal evaporation and low-pressure chemical vapor deposition.
Further, in the step (3), the metal electrode respectively adopts metal palladium and cesium to realize p-type and n-type ohmic contact with the semiconducting CNT, so as to prepare p-type and n-type transistors.
Further, the dielectric layer in step (7) is a dielectric constant material, including but not limited to hafnium oxide, yttrium oxide, tantalum oxide, tin oxide, zirconium oxide, titanium oxide, aluminum oxide; the deposited dielectric layer adopts any one of magnetron sputtering, CVD, ALD, physical vapor deposition, thermal evaporation and low-pressure chemical vapor deposition.
Further, the gate electrode region is defined in the step (8), and a specific method for depositing the gate electrode is as follows: patterning the grid region by using an electron beam exposure or photoetching process, and then directly depositing a metal material by using one of methods such as electron beam evaporation, magnetron sputtering, thermal evaporation and the like to obtain the metal grid.
Further, the gate region is defined in the step (8), and a specific method for depositing the gate is as follows: depositing a metallic CNT film in a large area, patterning by using an electron beam exposure or photoetching process, and etching the metallic CNT film by using an oxygen plasma cleaning machine to obtain a metallic CNT film gate.
Further, the metallic CNT film is deposited by any one of CVD, CNT liquid phase interface purification and self-assembly.
Compared with the prior art, the invention has the following advantages:
the invention provides a gate surrounding transistor based on a CNT array channel and a preparation method thereof. Compared with the complex top-down processing process, the preparation process of the invention is simpler, the used micro-nano processing technology is also simpler, and the p-type ohmic contact and the n-type ohmic contact with the semiconducting CNT can be respectively realized by adopting metal palladium and cesium to prepare the p-type transistor and the n-type transistor, so that the phase inverter is easy to construct.
Drawings
Fig. 1 is a cross-sectional schematic diagram of a CNT FinFET.
Fig. 2 is a flow chart of transistor fabrication.
FIG. 3 is a first schematic diagram of a transistor fabrication process; (FIG. 3a) a schematic structural diagram of an SOI substrate, (FIG. 3b) a schematic structural diagram after etching a step, (FIG. 3c) a schematic structural diagram of a step after depositing an insulating layer, and (FIG. 3d) a schematic structural diagram after planarization and etching of the insulating layer.
FIG. 4 is a second schematic diagram of a transistor fabrication process; (fig. 4a) a schematic structural diagram of a single-layer CNT array grown in a step structure region, (fig. 4b) a schematic structural diagram of source and drain electrodes deposited, (fig. 4c) a schematic structural diagram of an insulating layer deposited (fig. 4d) a schematic structural diagram after removing a planar insulating layer and the single-layer CNT array.
FIG. 5 is a third schematic diagram of a transistor fabrication process; (fig. 5a) a schematic structural diagram after removing the top step by wet etching, (fig. 5b) a schematic structural diagram after depositing a dielectric layer, and (fig. 5c) a schematic structural diagram after depositing a gate electrode.
FIG. 6 is a cross-sectional schematic view of a CNT FinFET array;
101-substrate bottom layer, 102-substrate middle insulating layer, 103-substrate top layer, 104-insulating layer, 105-channel, 106-source electrode, 107-dielectric layer, 108-gate electrode, 109-drain electrode.
Detailed Description
Example 1
As shown in fig. 1 and 5c, a gate-around transistor based on a CNT array channel comprises a substrate, a channel 105, a source electrode 106, a drain electrode 109, an insulating layer 104, a dielectric layer 107 and a gate 108;
as shown in fig. 3a, the substrate is an SOI substrate, and includes a substrate bottom layer 101, a substrate middle insulating layer 102, and a substrate top layer 103, which are sequentially arranged from bottom to top;
the substrate is provided with a channel 105, a source electrode 106 and a drain electrode 109 are deposited at the front end and the rear end of the channel 105, an insulating layer 104 is deposited on the surfaces of the channel 105, the source electrode 106 and the drain electrode 109, a dielectric layer 107 is deposited on the surfaces of the insulating layer 104 and the substrate, and a grid 108 is deposited in the middle of the dielectric layer 107;
the channel 105 is a vertical standing single-layer high-density parallel array of CNTs;
the insulating layer 104 and the dielectric layer 107 are insulating material films, and the insulating layer 104 and the dielectric layer 107 are hafnium oxide films in this embodiment;
the gate 108 is a metallic or metallic CNT film;
the source electrode and the drain electrode are made of metal, and the embodiment is made of metal Pd.
As shown in fig. 3-5, a method for manufacturing a gate-around transistor based on a CNT array channel includes the following steps:
(1) processing a substrate by adopting a micro-nano processing technology, exposing by using an electron beam exposure technology, developing by using a developing solution, drying by blowing nitrogen, etching by using reactive plasma to remove a silicon material on the top layer 103 of the substrate without the protection of photoresist, keeping the middle insulating layer 102 not damaged, and finally removing the photoresist to obtain a vertical step structure, wherein the structure is shown in figure 3b, then depositing an insulating layer 104 on the surface of the step by adopting a magnetron sputtering method, the structure is shown in figure 3c, then removing the insulating layer 104 in a plane area by using a reactive ion etching technology, keeping the insulating layer 104 on the side wall of the step, and the structure is shown in figure 3 d;
(2) preparing a single-layer semiconductor CNT array film 105 which is arranged in parallel and uniform on the surface of the step by adopting a CNT liquid phase interface purification and self-assembly method based on the step (1), wherein the structure is shown in FIG. 4 a;
(3) defining the areas of the source electrode 106 and the drain electrode 109, depositing metal Pd by electron beam evaporation in the front and back areas of the single-layer semiconducting CNT array film 105 as the source electrode 106 and the drain electrode 109, and the structure is shown in FIG. 4 b;
the specific method for defining the source electrode and the drain electrode area comprises the following steps: exposing and developing the surface of the semiconductor CNT array region by using an electron beam exposure technology or a photoetching technology, and defining a source electrode region and a drain electrode region;
(4) depositing an insulating layer 104 on the surface of the sample in the step (3) by magnetron sputtering, wherein the structure is shown in fig. 4 c;
(5) removing the insulating layer and the single-layer semiconducting CNT array film 105 in the planar region and the single-layer semiconducting CNT array film 105 and the insulating layer 104 in the sidewall region by using a planar removal process to obtain a vertically standing and directionally arranged semiconducting CNT array 105, wherein the structure is shown in FIG. 4 d;
(6) removing the steps on the top layer 103 of the substrate by using a selective wet etching process to obtain a semiconducting CNT array, a source electrode 106 and a drain electrode 109 which stand vertically and are clamped by an insulating layer 104, wherein the structure is shown in FIG. 5 a;
(7) based on the step (6), depositing a dielectric layer 107 on the surface of the obtained sample by magnetron sputtering, wherein the dielectric layer is used for encapsulating the vertically standing aligned semiconducting CNT array 105, and simultaneously encapsulating the source electrode 106 and the drain electrode 109, and the structure is shown in FIG. 5 b;
(8) defining the gate 108 area, depositing the gate 108, and forming the transistor structure, as shown in fig. 5c, the transistor is a P-type gate-around transistor based on the highly oriented CNT array channel.
Defining a gate electrode area, and depositing a gate electrode by the specific method: patterning the grid region by using an electron beam exposure or photoetching process, and then directly depositing a metal material by using an electron beam evaporation, magnetron sputtering or thermal evaporation method to obtain the metal grid.
Example 2
The difference from example 1 is that: the materials of the source electrode 106 and the drain electrode 109 in the step (3) may also be replaced by metal Sc.
An N-type gate-around transistor based on a highly aligned CNT array channel can be obtained.
Example 3
The difference from example 1 is that: the substrate in the step (1) can be replaced by other substrates, such as a substrate with a similar SOI type three-layer structure, or a substrate with a double-layer structure, wherein the upper layer can be a semiconductor, a metal or an insulator, the lower layer is made of an insulator or a simple substance insulating substrate, and a metal step can be obtained by utilizing a photoetching process and an evaporation process.
A gate-around transistor based on a highly aligned CNT array channel can be obtained.
Example 4
The difference from example 1 is that: and (8) defining a gate electrode area, wherein the specific method for depositing the gate electrode comprises the following steps: depositing a metallic CNT film in a large area by CVD (chemical vapor deposition), patterning by using an electron beam exposure or photoetching process, and finally etching the metallic CNT film by using an oxygen plasma cleaning machine to obtain the metallic CNT film gate.
A highly aligned CNT array channel based gate-around transistor with a metallic CNT thin film as the gate can be obtained.

Claims (10)

1. A gate-around transistor based on a CNT array channel comprises a substrate, a channel, a source electrode, a drain electrode, an insulating layer, a dielectric layer and a gate;
the substrate is provided with a channel, a source electrode and a drain electrode are deposited at the front end and the rear end of the channel, insulating layers are deposited on the surfaces of the channel, the source electrode and the drain electrode, dielectric layers are deposited on the surfaces of the insulating layers and the substrate, and a grid electrode is deposited in the middle of the dielectric layers;
the channel is a vertical standing single-layer high-density CNT parallel array, the insulating layer and the dielectric layer are insulating material films, the gate is a metal or metallic CNT film, and the source electrode and the drain electrode are metals.
2. The method of claim 1, comprising the steps of:
(1) processing the substrate by adopting a micro-nano processing technology to obtain a vertical step with controllable height, then depositing an insulating layer on the surface of the step, removing the insulating layer in a plane area by utilizing a reactive ion etching technology, and reserving the insulating layer on the side wall of the step;
(2) preparing a single-layer semiconductor CNT array film which is arranged in sequence and uniform on the substrate by adopting a CNT liquid phase interface purification and self-assembly method based on the step (1);
(3) defining the areas of a source electrode and a drain electrode, and depositing metal electrodes on the front area and the rear area of the single-layer semiconductor CNT array film on the substrate to be used as the source electrode and the drain electrode;
(4) depositing an insulating layer on the surface of the sample in the step (3);
(5) removing the insulating layer and the single-layer semiconductive CNT array film in the plane area and reserving the single-layer semiconductive CNT array film and the insulating layer in the side wall area by adopting a plane removal process to obtain a vertically-standing directionally-arranged semiconductive CNT array;
(6) removing the vertical steps by adopting a selective wet etching process to obtain a semiconductor CNT array, a source electrode and a drain electrode which stand vertically and are clamped by an insulating layer;
(7) depositing a dielectric layer on the surface of the obtained sample based on the step (6) for encapsulating the single-layer semiconductor CNT array, and simultaneously encapsulating the source electrode and the drain electrode;
(8) and defining a gate electrode area, and depositing a gate electrode to form the transistor.
3. The method of claim 2, wherein the two specific methods for obtaining the height-controllable vertical step are as follows: the first method comprises the steps that an SOI type substrate is used, exposure development is carried out on the surface of the substrate by using an electron beam exposure technology or a photoetching technology to obtain a pattern, then the top layer material of the substrate in an exposure pattern area is removed by using an etching process, and a middle insulating layer and a bottom layer of the substrate are reserved to obtain a vertical step; in the second method, an electron beam exposure technology or a photolithography technology is used to perform exposure and development on the surface of an insulating substrate to obtain a pattern, and then an evaporation process is used to obtain a vertical metal step.
4. The method of claim 2, wherein the insulating layer is a high-k material; the deposited insulating layer adopts any one of magnetron sputtering, a chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method, thermal evaporation, electron beam evaporation and a low-pressure chemical vapor deposition method.
5. The method of claim 2, wherein the source and drain electrode regions are defined in step (3) by the following specific method: exposing and developing the surface of the semiconductor CNT array region by using an electron beam exposure technology or a photoetching technology, and defining a source electrode region and a drain electrode region; the deposited metal electrode adopts any one of electron beam evaporation, magnetron sputtering, CVD, ALD, physical vapor deposition, thermal evaporation and low-pressure chemical vapor deposition.
6. The method as claimed in claim 2, wherein the metal electrode in step (3) is in p-type and n-type ohmic contact with semiconducting CNT by using metal palladium and cesium, respectively, to fabricate p-type and n-type transistors.
7. The method of claim 2, wherein the dielectric layer in step (7) is a dielectric constant material; the deposited dielectric layer adopts any one of magnetron sputtering, CVD, ALD, physical vapor deposition method, thermal evaporation, electron beam evaporation and low-pressure chemical vapor deposition method.
8. The method of claim 2, wherein the gate electrode area is defined in the step (8), and the gate electrode is deposited by the following specific method: patterning the grid region by using an electron beam exposure or photoetching process, and directly depositing a metal material by adopting any one of electron beam evaporation, magnetron sputtering or thermal evaporation methods to obtain the metal grid.
9. The method of claim 2, wherein the gate electrode area is defined in the step (8), and the gate electrode is deposited by the following specific method: depositing a metallic CNT film in a large area, patterning by using an electron beam exposure or photoetching process, and etching the metallic CNT film by using an oxygen plasma cleaning machine to obtain a metallic CNT film gate.
10. The method of claim 9, wherein the metallic CNT film is deposited by any one of CVD, CNT liquid phase interface purification and self-assembly.
CN202111486399.5A 2021-12-07 2021-12-07 Gate surrounding transistor based on CNT array channel and preparation method Pending CN114203907A (en)

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