CN114200796B - Alignment mark and forming method thereof - Google Patents

Alignment mark and forming method thereof Download PDF

Info

Publication number
CN114200796B
CN114200796B CN202010911176.8A CN202010911176A CN114200796B CN 114200796 B CN114200796 B CN 114200796B CN 202010911176 A CN202010911176 A CN 202010911176A CN 114200796 B CN114200796 B CN 114200796B
Authority
CN
China
Prior art keywords
opening
layer
mark
forming
processed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010911176.8A
Other languages
Chinese (zh)
Other versions
CN114200796A (en
Inventor
张瑞麟
邢滨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202010911176.8A priority Critical patent/CN114200796B/en
Publication of CN114200796A publication Critical patent/CN114200796A/en
Application granted granted Critical
Publication of CN114200796B publication Critical patent/CN114200796B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

An alignment mark and a method for forming the same, comprising: providing a substrate, wherein the substrate comprises a marking area, and the marking area is provided with a layer to be processed; forming a first mark opening in the layer to be treated on the mark area; and forming a second mark opening in the layer to be treated on the mark area by taking the first mark opening as an alignment mark, wherein the first mark opening and the second mark opening are mutually separated. Through forming first mark opening and second mark opening in the mark district, and first mark opening and second mark opening are discrete each other for first mark opening with the second mark opening can not produce the overlap, avoid because of repeated etching the etching penetration that the same position in the mark district caused, and then avoided the production of the etching environmental pollution and the residual that cause because of etching penetration, avoided the residual in the mark district enters into the influence that causes to the device structure in the device district, effectively promoted the performance of the semiconductor structure of final formation.

Description

Alignment mark and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to an alignment mark and a method for forming the same.
Background
Photolithography is a critical technique in semiconductor fabrication that enables transfer of patterns from a reticle to a wafer surface to form a semiconductor product that meets design requirements. In the photoetching process, firstly, through an exposure step, light irradiates a silicon wafer coated with photoresist through a light-transmitting or light-reflecting area in a mask plate and performs photochemical reaction with the photoresist; then, through a developing step, a photoetching pattern is formed by utilizing the dissolution degree of photosensitive and non-photosensitive photoresist to a developer, so that transfer of a mask pattern is realized; then, the silicon wafer is etched based on the photoetching pattern formed by the photoresist layer through an etching step, and the mask pattern is further transferred to the silicon wafer.
The wafer must be aligned prior to photolithography so that the pattern can be transferred precisely to the photoresist layer of the wafer. There are two kinds of alignment marks in the prior art, namely a zero layer mark and a scribe line mark.
However, the alignment marks formed by the prior art still have a plurality of problems.
Disclosure of Invention
The invention solves the technical problem of providing an alignment mark and a forming method thereof, which can effectively improve the performance of a finally formed semiconductor structure.
In order to solve the above problems, the present invention provides an alignment mark comprising: a substrate comprising a marking zone having a layer to be processed thereon; a first marking opening in the layer to be treated on the marking zone; and a second mark opening in the layer to be treated on the mark region, wherein the first mark opening and the second mark opening are mutually separated.
Optionally, the substrate further includes: a device region; the marking region surrounds the device region, the layer to be processed is further positioned on the device region, and the first marking opening and the second marking opening are positioned at corner positions of the device region.
Optionally, the method further comprises a plurality of first device openings and a plurality of second device openings located in the layer to be processed on the device region.
Optionally, the first mark opening includes: a first opening extending along a first direction, a second opening extending along a second direction, wherein the first direction is perpendicular to the second direction, and the first opening exposes the side wall of the second opening.
Optionally, the second mark opening includes: a third opening and a fourth opening extending along the first direction, the fourth opening exposing a sidewall of the third opening, the first opening and the third opening being arranged in parallel along the second direction, the third opening having a first width dimension along the second direction, the fourth opening having a second width dimension along the second direction, the second width dimension being greater than the first width dimension; a fifth opening and a sixth opening extending along the second direction, the sixth opening exposing a sidewall of the fifth opening, the second opening and the fifth opening being arranged in parallel along the first direction, the fifth opening having a third width dimension along the first direction, the sixth opening having a fourth width dimension along the first direction, the fourth width dimension being greater than the third width dimension.
Optionally, the first width dimension ranges from 0.3 μm to 0.5 μm; the third width dimension is in the range of 0.3 μm to 0.5 μm.
Optionally, the first mark opening and the second mark opening have a first distance therebetween.
Optionally, the first pitch size is a pitch size between the first opening and the third opening, or a pitch size between the second opening and the fifth opening.
Optionally, the first pitch dimension ranges from 0.2 μm to 0.4 μm.
Optionally, the method further comprises: and a third mark opening and a fourth mark opening which are positioned in the layer to be treated on the mark area, wherein the first mark opening, the second mark opening, the third mark opening and the fourth mark opening are mutually separated.
Optionally, a second space size is provided between the third mark opening and the second mark opening, and a third space size is provided between the fourth mark opening and the third mark opening.
Optionally, the third mark opening includes: a seventh opening extending in the first direction, an eighth opening extending in the second direction, the eighth opening exposing a sidewall of the seventh opening, a ninth opening extending in the first direction, the ninth opening exposing a sidewall of the eighth opening, and a tenth opening extending in the second direction, the tenth opening exposing a sidewall of the ninth opening.
Optionally, the fourth mark opening includes: an eleventh opening extending in the first direction, a twelfth opening extending in the second direction, the twelfth opening exposing a sidewall of the eleventh opening, a thirteenth opening extending in the first direction, the thirteenth opening exposing a sidewall of the twelfth opening, and a fourteenth opening extending in the second direction, the fourteenth opening exposing a sidewall of the thirteenth opening.
Optionally, the method further comprises a plurality of third device openings and a plurality of fourth device openings in the layer to be processed on the device region.
Optionally, the substrate further includes: the device comprises a substrate and a layer to be etched, wherein the layer to be processed is positioned on the substrate and is positioned on the layer to be etched.
Optionally, the layer to be etched includes: the device comprises a device layer and a hard mask layer positioned on the device layer, wherein the layer to be processed is positioned on the hard mask layer.
Optionally, the method further comprises: a first stop layer located between the substrate and the device layer; a second stop layer located between the device layer and the hard mask layer; and the third stopping layer is positioned between the hard mask layer and the layer to be processed.
Correspondingly, the technical scheme of the invention also provides a method for forming the alignment mark, which comprises the following steps: providing a substrate, wherein the substrate comprises a marking area, and the marking area is provided with a layer to be processed; forming a first mark opening in the layer to be processed on the mark area by adopting first patterning; and performing second patterning processing on the layer to be processed by taking the first mark opening as an alignment mark, and forming a second mark opening in the layer to be processed on the mark region, wherein the first mark opening and the second mark opening are mutually separated.
Optionally, the method for first patterning includes: forming a first patterning layer on the layer to be treated, wherein the first patterning layer exposes part of the top surface of the layer to be treated; etching the layer to be processed by taking the first graphical layer as a mask, and forming the first mark opening in the layer to be processed; after forming the first mark opening, the first patterned layer is removed.
Optionally, before forming the first patterned layer, the method further includes: and forming a first sacrificial layer on the layer to be treated, and a first anti-reflection layer on the first sacrificial layer, wherein the first patterning layer is positioned on the first anti-reflection layer.
Optionally, the method for second patterning includes: forming a second patterned layer on the layer to be treated, wherein the second patterned layer exposes part of the top surface of the layer to be treated; etching the layer to be processed by taking the second graphical layer as a mask, and forming a second mark opening in the layer to be processed; after forming the second mark opening, the second patterned layer is removed.
Optionally, before forming the second patterned layer, the method further includes: and forming a second sacrificial layer on the layer to be treated, wherein the second sacrificial layer fills the first mark opening, and is positioned on a second anti-reflection layer on the second sacrificial layer, and the second patterned layer is positioned on the second anti-reflection layer.
Optionally, the substrate further includes: a device region; the marking region surrounds the device region, the layer to be processed is further positioned on the device region, and the first marking opening and the second marking opening are positioned at corner positions of the device region.
Optionally, in the process of forming the first mark opening, the method further includes: and forming a plurality of first device openings in the layer to be treated on the device region.
Optionally, in the process of forming the second mark opening, the method further includes: and forming a plurality of second device openings in the layer to be treated on the device region.
Optionally, the first mark opening includes: a first opening extending along a first direction, a second opening extending along a second direction, wherein the first direction is perpendicular to the second direction, and the first opening exposes the side wall of the second opening.
Optionally, the second mark opening includes: a third opening and a fourth opening extending along the first direction, the fourth opening exposing a sidewall of the third opening, the first opening and the third opening being arranged in parallel along the second direction, the third opening having a first width dimension along the second direction, the fourth opening having a second width dimension along the second direction, the second width dimension being greater than the first width dimension; a fifth opening and a sixth opening extending along the second direction, the sixth opening exposing a sidewall of the fifth opening, the second opening and the fifth opening being arranged in parallel along the first direction, the fifth opening having a third width dimension along the first direction, the sixth opening having a fourth width dimension along the first direction, the fourth width dimension being greater than the third width dimension.
Optionally, the first width dimension ranges from 0.3 μm to 0.5 μm; the third width dimension is in the range of 0.3 μm to 0.5 μm.
Optionally, the first mark opening and the second mark opening have a first distance therebetween.
Optionally, the first pitch size is a pitch size between the first opening and the third opening, or a pitch size between the second opening and the fifth opening.
Optionally, the first pitch dimension ranges from 0.2 μm to 0.4 μm.
Optionally, after forming the first mark opening and the second mark opening, the method further includes: performing third graphical processing on the layer to be processed by taking the second mark opening as an alignment mark, and forming a third mark opening in the layer to be processed; and performing fourth patterning processing on the layer to be processed by taking the third mark opening as an alignment mark, and forming a fourth mark opening in the layer to be processed, wherein the first mark opening, the second mark opening, the third mark opening and the fourth mark opening are mutually separated.
Optionally, a second space size is provided between the third mark opening and the second mark opening, and a third space size is provided between the fourth mark opening and the third mark opening.
Optionally, the third mark opening includes: a seventh opening extending in the first direction, an eighth opening extending in the second direction, the eighth opening exposing a sidewall of the seventh opening, a ninth opening extending in the first direction, the ninth opening exposing a sidewall of the eighth opening, and a tenth opening extending in the second direction, the tenth opening exposing a sidewall of the ninth opening.
Optionally, the fourth mark opening includes: an eleventh opening extending in the first direction, a twelfth opening extending in the second direction, the twelfth opening exposing a sidewall of the eleventh opening, a thirteenth opening extending in the first direction, the thirteenth opening exposing a sidewall of the twelfth opening, and a fourteenth opening extending in the second direction, the fourteenth opening exposing a sidewall of the thirteenth opening.
Optionally, in the process of forming the third mark opening, the method further includes: and forming a plurality of third device openings in the layer to be treated on the device region.
Optionally, in forming the fourth mark opening, the method further includes: and forming a plurality of fourth device openings in the layer to be treated on the device region.
Optionally, the substrate further includes: the device comprises a substrate and a layer to be etched, wherein the layer to be processed is positioned on the substrate and is positioned on the layer to be etched.
Optionally, the layer to be etched includes: the device comprises a device layer and a hard mask layer positioned on the device layer, wherein the layer to be processed is positioned on the hard mask layer.
Optionally, the method further comprises: a first stop layer located between the substrate and the device layer; a second stop layer located between the device layer and the hard mask layer; and the third stopping layer is positioned between the hard mask layer and the layer to be processed.
Optionally, after forming the first device opening, the second device opening, the third device opening, and the fourth device opening, the method further includes: and forming a first side wall on the side walls of the first device opening, the second device opening, the third device opening and the fourth device opening.
Optionally, in the process of forming the first side wall, the method further includes: and forming second side walls on the side walls of the first mark opening, the second mark opening, the third mark opening and the fourth mark opening.
Optionally, after forming the first side wall and the second side wall, the method further includes: removing the layer to be treated; and etching the substrate by taking the first side wall and the second side wall as masks, and forming a graphical opening in the substrate.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the structure of the technical scheme, the first mark opening and the second mark opening are located in the mark region, and the first mark opening and the second mark opening are mutually separated, so that the first mark opening and the second mark opening cannot overlap, etching penetration caused by repeated etching of the same position in the mark region is avoided, further, etching environmental pollution and residue generation caused by etching penetration are avoided, influence on a device structure caused by entering of the residue in the mark region into the device region is avoided, and performance of a finally formed semiconductor structure is effectively improved.
According to the forming method of the technical scheme, the first mark opening and the second mark opening are formed in the mark region and are separated from each other, so that the first mark opening and the second mark opening cannot overlap, etching penetration caused by repeated etching of the same position in the mark region is avoided, further, etching environmental pollution and residue generation caused by etching penetration are avoided, influence on a device structure caused by entering of the residue in the mark region into the device region is avoided, and performance of a finally formed semiconductor structure is effectively improved.
Drawings
FIGS. 1 to 3 are schematic views of a structure of an alignment mark;
fig. 4 to 16 are schematic structural views illustrating steps of an alignment mark forming method according to an embodiment of the present invention.
Detailed Description
As described in the background, however, the alignment marks formed in the prior art still have a number of problems. The following will make a detailed description with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 including a mark region, the substrate having a layer 101 to be processed thereon; forming a first sacrificial layer 102 on the layer to be treated 101; forming a first patterned layer 103 on the first sacrificial layer 102, the first patterned layer 103 exposing a portion of a top surface of the first sacrificial layer 102; and etching the first sacrificial layer 102 and the layer to be processed 101 by taking the first patterned layer 103 as a mask, and forming a first mark opening 104 in the layer to be processed 101.
Referring to fig. 2, after the first mark opening 104 is formed, the first patterned layer 103 and the first sacrificial layer 102 are removed; forming a second sacrificial layer 105 on the layer to be processed 101, wherein the second sacrificial layer 105 fills the first mark opening 104; forming a second patterned layer 106 on the second sacrificial layer 105, the second patterned layer 106 exposing a portion of a top surface of the second sacrificial layer 105; and etching the second sacrificial layer 105 and the layer to be processed 101 by taking the second patterned layer 106 as a mask, forming a second mark opening 107 in the layer to be processed 101, wherein the first mark opening 104 and the second mark opening 107 are overlapped.
Referring to fig. 3, after the second mark openings 107 are formed, the second patterned layer 106 and the second sacrificial layer 105 are removed.
In this embodiment, the first mark opening 104 and the second mark opening 107 are used as alignment marks during a photolithography process, so as to facilitate measurement of the device size during a co-channel etching process. However, in this embodiment, since the first mark opening 104 and the second mark opening 107 are overlapped in the to-be-processed layer, the first mark opening 104 and the second mark opening 107 are formed at the same position of the to-be-processed layer 101, so that the to-be-processed layer 101 is easily etched through, so that an etching solution or etching gas for etching the second mark opening 107 reacts with a hard mask layer under the to-be-processed layer, and substances are easily remained in the hard mask layer, and the residual substances easily enter into a device region to affect the device structure; in addition, the gas generated after the reaction also causes pollution of the etching environment.
On the basis, the invention provides the alignment mark and the forming method thereof, the first mark opening and the second mark opening are formed in the mark region, and the first mark opening and the second mark opening are mutually separated, so that the first mark opening and the second mark opening cannot be overlapped, etching penetration caused by repeated etching of the same position in the mark region is avoided, further, etching environmental pollution and residue generation caused by etching penetration are avoided, influence on a device structure caused by entering of the residue in the mark region into the device region is avoided, and the performance of a finally formed semiconductor structure is effectively improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 16 are schematic structural views illustrating a process of forming an alignment mark according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 5 is a schematic cross-sectional view taken along line A-A in fig. 4, and fig. 4 is a top view of fig. 5, wherein a substrate is provided, and the substrate includes a marking area I having a layer 203 to be processed thereon.
In this embodiment, the substrate further includes: a device region II; the marking region I surrounds the device region II, and the layer to be processed 203 is further located on the device region II.
The mark region I is used for forming corresponding alignment marks during each photoetching process, and provides a measuring reference for the device structure formed in the device region II. The device region II is used for forming a device structure with an actual function, and the marking region I also forms a corresponding device structure due to the global process while the device region II forms the device structure, but the device structure formed in the marking region I does not have an actual function.
In this embodiment, the substrate further includes: a substrate 200 and a layer to be etched on the substrate 200, wherein the layer to be processed is positioned on the layer to be etched.
In this embodiment, the layer to be etched includes: a device layer 201 and a hard mask layer 202 on the device layer 201, wherein the layer to be processed 203 is on the hard mask layer 202.
In this embodiment, the material of the device layer 201 is a low-K dielectric material.
In this embodiment, the hard mask layer 202 is made of titanium nitride; in other embodiments, the hard mask layer may also be made of tantalum nitride.
In this embodiment, further comprising: a first stop layer 204, the first stop layer 204 being located between the substrate 200 and the device layer 201; a second stop layer 205, the second stop layer 205 being located between the device layer 201 and the hard mask layer 202; a third stop layer 206, the third stop layer 206 being located between the hard mask layer 202 and the layer to be processed 203.
The first stop layer 204, the second stop layer 205 and the third stop layer 206 function as: stopping each etching process on the corresponding stopping layer, and avoiding the damage of the etching process to the lower layer structure.
Referring to fig. 6, 7 and 8, fig. 7 is an enlarged schematic view of a portion a in fig. 6, and fig. 8 is a schematic view of a cross section along line B-B in fig. 7; a first patterning process is used to form a first mark opening 207 in the layer 203 to be processed over the mark region I.
In this embodiment, the method for performing the first patterning process includes: forming a first patterned layer (not shown) on the layer to be processed 203, the first patterned layer exposing a portion of a top surface of the layer to be processed 203; etching the layer to be processed 203 by taking the first patterned layer as a mask, and forming the first mark opening 207 in the layer to be processed 203; after the first mark openings 207 are formed, the first patterned layer is removed.
In this embodiment, the material of the first patterned layer is photoresist.
In this embodiment, before forming the first patterned layer, the method further includes: a first sacrificial layer, a first anti-reflection layer (not shown) on the first sacrificial layer, and a first patterning layer on the first anti-reflection layer are formed on the layer to be treated 203.
In this embodiment, amorphous carbon is used as the material of the first sacrificial layer, which acts to provide a flat top surface for etching the layer to be processed 203.
In this embodiment, the first anti-reflection layer is used to reflect light during exposure in smaller lithography, so as to improve the lithography effect.
In this embodiment, the first mark opening 207 includes: a first opening 207a extending in a first direction X and a second opening 207b extending in a second direction Y, the first direction X being perpendicular to the second direction Y, the first opening 207a exposing a sidewall of the second opening 207 b.
In this embodiment, in the process of forming the first mark opening 207, it further includes: first device openings (not shown) are formed in the layer to be processed 203 over the device region II.
Referring to fig. 9 and 10, fig. 10 is a schematic cross-sectional view taken along line C-C in fig. 9, wherein the first mark opening 207 is used as an alignment mark for performing a second patterning process on the layer to be processed 203, and a second mark opening 208 is formed in the layer to be processed 203 on the mark region I, and the first mark opening 207 and the second mark opening 208 are separated from each other.
By forming the first mark opening 207 and the second mark opening 208 in the mark region, and the first mark opening 207 and the second mark opening 208 are separated from each other, so that the first mark opening 207 and the second mark opening 208 do not overlap, etching penetration caused by repeated etching of the same position in the mark region I is avoided, further, etching environmental pollution and residue caused by etching penetration are avoided, influence of residues in the mark region on a device structure caused by entering the device region is avoided, and performance of a finally formed semiconductor structure is effectively improved.
In this embodiment, the method for second patterning includes: forming a second patterned layer (not shown) on the layer to be processed 203, the second patterned layer exposing a portion of a top surface of the layer to be processed 203; etching the layer to be processed 203 by taking the second patterned layer as a mask, and forming the second mark opening 208 in the layer to be processed 203; after forming the second marker openings 208, the second patterned layer is removed.
In this embodiment, the material of the second patterned layer is photoresist.
In this embodiment, before forming the second patterned layer, the method further includes: a second sacrificial layer is formed on the layer to be processed 203, the second sacrificial layer filling the first mark opening 207, a second anti-reflective layer (not shown) on the second sacrificial layer, the second patterned layer being on the second anti-reflective layer.
In this embodiment, the second mark opening 208 includes: a third opening 208a and a fourth opening 208b extending along the first direction X, the fourth opening 208b exposing a sidewall of the third opening 208a, the first opening 207a being arranged in parallel with the third opening 208a along the second direction Y, the third opening 208a having a first width dimension d1 along the second direction Y, the fourth opening 208b having a second width dimension d2 along the second direction Y, the second width dimension d2 being greater than the first width dimension d1; a fifth opening 208c and a sixth opening 208d extending along the second direction Y, the sixth opening 208d exposing a sidewall of the fifth opening 208c, the second opening 207b being arranged parallel to the fifth opening 208c along the first direction X, the fifth opening 208c having a third width dimension d3 along the first direction X, the sixth opening 208d having a fourth width dimension d4 along the first direction X, the fourth width dimension d4 being greater than the third width dimension d3.
In this embodiment, the first width d1 is in the range of 0.3 μm to 0.5 μm; the third width d3 is in the range of 0.3 μm to 0.5 μm. The first width dimension and the third width dimension in the range of 0.3 μm to 0.5 μm facilitate center recognition of the image.
In this embodiment, the first mark opening 207 and the second mark opening 208 have a first spacing dimension s1 therebetween. The first pitch dimension s1 is a pitch dimension between the first opening 207a and the third opening 208a, or a pitch dimension between the second opening 207b and the fifth opening 208 c.
In this embodiment, the first pitch dimension s1 ranges from 0.2 μm to 0.4 μm.
When the first interval size s1 is smaller than 0.2 mu m, the formed processing window is smaller, and certain difficulty is brought to the manufacturing process; when the first pitch dimension s1 is greater than 0.4 μm, center recognition of the image is affected.
In this embodiment, in the process of forming the second mark opening 208, the method further includes: a number of second device openings (not shown) are formed in the layer to be processed 203 over the device region II.
In this embodiment, the first mark opening 207 and the second mark opening 208 are located at corner positions of the device region II.
Referring to fig. 11 and 12, fig. 12 is a schematic cross-sectional view taken along line D-D in fig. 11, after the first mark opening 207 and the second mark opening 208 are formed, a third patterning process is performed on the layer to be processed 203 by using the second mark opening 208 as an alignment mark, and a third mark opening 209 is formed in the layer to be processed 203.
In this embodiment, the third mark opening 209 includes: a seventh opening 209a extending in the first direction X, an eighth opening 209b extending in the second direction Y, the eighth opening 209b exposing a sidewall of the seventh opening 209a, a ninth opening 209c extending in the first direction X, the ninth opening 209c exposing a sidewall of the eighth opening 209b, and a tenth opening 209d extending in the second direction Y, the tenth opening 209d exposing a sidewall of the ninth opening 209 c.
In this embodiment, the third mark opening 209 and the second mark opening 208 have a second space dimension s2 therebetween.
In this embodiment, the second pitch dimension s2 is in the range of 0.2 μm to 0.4 μm.
In this embodiment, in the process of forming the third mark opening 209, the method further includes: a number of third device openings (not shown) are formed in the layer to be processed 203 over the device region II.
Referring to fig. 13 and 14, fig. 14 is a schematic cross-sectional view taken along line E-E in fig. 13, the third mark opening 209 is used as an alignment mark to perform a fourth patterning process on the layer to be processed, a fourth mark opening 210 is formed in the layer to be processed 203, and the first mark opening 207, the second mark opening 208, the third mark opening 209 and the fourth mark opening 210 are separated from each other.
In this embodiment, the fourth mark opening 210 includes: an eleventh opening 210a extending in the first direction X, a twelfth opening 210b extending in the second direction Y, the twelfth opening 210b exposing a sidewall of the eleventh opening 210a, a thirteenth opening 210c extending in the first direction X, the thirteenth opening 210c exposing a sidewall of the twelfth opening 210b, and a fourteenth opening 210d extending in the second direction Y, the fourteenth opening 210d exposing a sidewall of the thirteenth opening 210 c.
In this embodiment, the fourth mark opening 210 and the third mark opening 209 have a third space dimension s3 therebetween.
In this embodiment, the third pitch dimension s3 is in the range of 0.2 μm to 0.4 μm.
In this embodiment, by using 4 photolithography processes as an example, the number of mark openings formed is also 4. In other embodiments, the photolithography process may be used less than 4 times or more than 4 times, and thus the number of correspondingly formed mark openings may be less than 4 or more than 4.
In this embodiment, the third mark opening 209 and the fourth mark opening 210 are also located at corner positions of the device region II, and the patterns formed by the first mark opening 207, the second mark opening 208, the third mark opening 209 and the fourth mark opening 210 are in an "L" shape, and when 4 wafers are spliced together, the patterns formed by the mark openings at the corner positions of the 4 wafers will have a "+" structure.
In this embodiment, in the process of forming the fourth mark opening 210, the method further includes: fourth device openings (not shown) are formed in the layer to be processed 203 over the device region II.
Referring to fig. 15, the view directions of fig. 15 and 14 are identical, and after forming the first device opening, the second device opening, the third device opening, and the fourth device opening, a first sidewall (not shown) is formed on sidewalls of the first device opening, the second device opening, the third device opening, and the fourth device opening.
In this embodiment, in a process of forming the first side wall, the method further includes: a second sidewall 211 is formed on the sidewalls of the first mark opening 207, the second mark opening 208, the third mark opening 209, and the fourth mark opening 210.
In this embodiment, the method for forming the first sidewall and the second sidewall 211 includes: forming initial side walls (not shown) in the first device opening, the second device opening, the third device opening, the fourth device opening, the first mark opening 207, the second mark opening 208, the third mark opening 209, and the fourth mark opening 210, and on the top surface of the layer to be processed 203; and etching the initial side wall until the top surfaces of the layer to be processed 203 and the third stop layer 206 are exposed, thereby forming the first side wall and the second side wall 211.
In this embodiment, the forming the first side wall on the side walls of the first device opening, the second device opening, the third device opening and the fourth device opening has the following functions: spatial frequency doubling of the lithographic pattern is achieved by Self-aligned dual imaging (Self-aligned Double Patterning, SADP), i.e. after one lithographic completion, using non-lithographic process steps (thin film deposition, etching, etc.) successively.
Referring to fig. 16, after forming the first sidewall and the second sidewall 211, the layer to be processed 203 is removed; and etching the substrate by taking the first side wall and the second side wall 211 as masks, and forming a patterned opening 212 in the substrate.
In this embodiment, a wet etching process is used to remove the layer 203 to be treated; in other embodiments, the process of removing the layer to be treated may also use a dry etching process.
In this embodiment, a wet etching process is adopted in the process of etching the substrate by using the first sidewall and the second sidewall 211 as masks; in other embodiments, the process of etching the substrate with the first sidewall and the second sidewall as masks may also use a dry etching process.
Accordingly, in an embodiment of the present invention, an alignment mark is further provided, please continue to refer to fig. 13 and 14, which includes: a substrate comprising a marking zone I having thereon a layer 203 to be processed; a first marking opening 207 in the layer to be treated 203 on the marking area I; a second marking opening 208 in the layer 203 to be processed is located on the marking area I, and the first marking opening 207 and the second marking opening 208 are separated from each other.
Through the first mark opening 207 and the second mark opening 208 which are positioned in the mark region, and the first mark opening 207 and the second mark opening 208 are mutually separated, so that the first mark opening 207 and the second mark opening 208 cannot overlap, etching penetration caused by repeated etching at the same position in the mark region I is avoided, further, etching environmental pollution and residue caused by etching penetration are avoided, influence on a device structure caused by entering of residues in the mark region into the device region is avoided, and performance of a finally formed semiconductor structure is effectively improved.
In this embodiment, the substrate further includes: a device region II; the marking region I surrounds the device region II, the layer to be processed 203 is further located on the device region II, and the first marking opening 207 and the second marking opening 208 are located at corner positions of the device region II.
In this embodiment, the method further includes a plurality of first device openings and a plurality of second device openings located in the layer 103 to be processed on the device region II.
In this embodiment, the first mark opening 207 includes: a first opening 207a extending in a first direction X and a second opening 207b extending in a second direction Y, the first direction X being perpendicular to the second direction Y, the first opening 207a exposing a sidewall of the second opening 207 b.
In this embodiment, the second mark opening 208 includes: a third opening 208a and a fourth opening 208b extending along the first direction X, the fourth opening 208b exposing a sidewall of the third opening 208a, the first opening 207a being arranged in parallel with the third opening 208a along the second direction Y, the third opening 208a having a first width dimension d1 along the second direction Y, the fourth opening 208b having a second width dimension d2 along the second direction Y, the second width dimension d2 being greater than the first width dimension d1; a fifth opening 208c and a sixth opening 208d extending along the second direction Y, the sixth opening 208d exposing a sidewall of the fifth opening 208c, the second opening 207b being arranged parallel to the fifth opening 208c along the first direction X, the fifth opening 208c having a third width dimension d3 along the first direction X, the sixth opening 208d having a fourth width dimension d4 along the first direction X, the fourth width dimension d4 being greater than the third width dimension d3.
In this embodiment, the first width d1 is in the range of 0.3 μm to 0.5 μm; the third width d3 is in the range of 0.3 μm to 0.5 μm.
In this embodiment, the first mark opening 207 and the second mark opening 208 have a first spacing dimension s1 therebetween.
In the present embodiment, the first pitch dimension s1 is a pitch dimension between the first opening 207a and the third opening 208a, or a pitch dimension between the second opening 207b and the fifth opening 208 c.
In this embodiment, the first pitch dimension s1 ranges from 0.2 μm to 0.4 μm.
In this embodiment, further comprising: a third marking opening 209 and a fourth marking opening 210 in the layer 203 to be processed on the marking area I, and the first marking opening 207, the second marking opening 208, the third marking opening 209, and the fourth marking opening 210 are separated from each other.
In this embodiment, the third mark opening 209 and the second mark opening 208 have a second space dimension s2 therebetween, and the fourth mark opening 210 and the third mark opening 209 have a third space dimension s3 therebetween.
In this embodiment, the third mark opening 209 includes: a seventh opening 209a extending in the first direction X, an eighth opening 209b extending in the second direction Y, the eighth opening 209b exposing a sidewall of the seventh opening 209a, a ninth opening 209c extending in the first direction X, the ninth opening 209c exposing a sidewall of the eighth opening 209b, and a tenth opening 209d extending in the second direction Y, the tenth opening 209d exposing a sidewall of the ninth opening 209 c.
In this embodiment, the fourth mark opening 210 includes: an eleventh opening 210a extending in the first direction X, a twelfth opening 210b extending in the second direction Y, the twelfth opening 210b exposing a sidewall of the eleventh opening 210a, a thirteenth opening 210c extending in the first direction X, the thirteenth opening 210c exposing a sidewall of the twelfth opening 210b, and a fourteenth opening 210d extending in the second direction Y, the fourteenth opening 210d exposing a sidewall of the thirteenth opening 210 c.
In this embodiment, the method further includes a plurality of third device openings and a plurality of fourth device openings located in the layer to be processed 203 on the device region II.
In this embodiment, the substrate further includes: a substrate 200 and a layer to be etched on the substrate 200, wherein the layer to be processed 203 is located on the layer to be etched.
In this embodiment, the layer to be etched includes: a device layer 201 and a hard mask layer 202 on the device layer 201, wherein the layer to be processed 203 is on the hard mask layer 202.
In this embodiment, further comprising: a first stop layer 204, the first stop layer 204 being located between the substrate 200 and the device layer 201; a second stop layer 205, the second stop layer 205 being located between the device layer 201 and the hard mask layer 202; a third stop layer 206, the third stop layer 206 being located between the hard mask layer 202 and the layer to be processed 203.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (41)

1. An alignment mark, comprising:
a substrate comprising a marking zone having a layer to be processed thereon;
a first marking opening in the layer to be treated on the marking zone;
a second marking opening in the layer to be treated on the marking zone, the first marking opening being separated from the second marking opening;
the first indicia opening includes: a first opening extending along a first direction, a second opening extending along a second direction, the first direction being perpendicular to the second direction, the first opening exposing a sidewall of the second opening;
the second indicia opening comprises: and the third opening and the fourth opening extend along the first direction, the fourth opening exposes the side wall of the third opening, the first opening and the third opening are arranged in parallel along the second direction, the third opening has a first width dimension along the second direction, the fourth opening has a second width dimension along the second direction, and the second width dimension is larger than the first width dimension.
2. The alignment mark of claim 1, wherein the substrate further comprises: a device region; the marking region surrounds the device region, the layer to be processed is further positioned on the device region, and the first marking opening and the second marking opening are positioned at corner positions of the device region.
3. The alignment mark of claim 2, further comprising a number of first device openings and a number of second device openings located within a layer to be processed on the device region.
4. The alignment mark of claim 1, wherein the second mark opening further comprises: a fifth opening and a sixth opening extending along the second direction, the sixth opening exposing a sidewall of the fifth opening, the second opening and the fifth opening being arranged in parallel along the first direction, the fifth opening having a third width dimension along the first direction, the sixth opening having a fourth width dimension along the first direction, the fourth width dimension being greater than the third width dimension.
5. The alignment mark of claim 4, wherein the first width dimension ranges from 0.3 μm to 0.5 μm; the third width dimension is in the range of 0.3 μm to 0.5 μm.
6. The alignment mark of claim 4, wherein the first mark opening and the second mark opening have a first pitch dimension therebetween.
7. The alignment mark of claim 6, wherein the first pitch dimension is a pitch dimension between the first opening and the third opening, or a pitch dimension between the second opening and the fifth opening.
8. The alignment mark of claim 6, wherein the first pitch dimension ranges from 0.2 μm to 0.4 μm.
9. The alignment mark of claim 1, further comprising: and a third mark opening and a fourth mark opening which are positioned in the layer to be treated on the mark area, wherein the first mark opening, the second mark opening, the third mark opening and the fourth mark opening are mutually separated.
10. The alignment mark of claim 9, wherein the third mark opening and the second mark opening have a second pitch dimension therebetween, and the fourth mark opening and the third mark opening have a third pitch dimension therebetween.
11. The alignment mark of claim 9, wherein the third mark opening comprises: a seventh opening extending in the first direction, an eighth opening extending in the second direction, the eighth opening exposing a sidewall of the seventh opening, a ninth opening extending in the first direction, the ninth opening exposing a sidewall of the eighth opening, and a tenth opening extending in the second direction, the tenth opening exposing a sidewall of the ninth opening.
12. The alignment mark of claim 9, wherein the fourth mark opening comprises: an eleventh opening extending in the first direction, a twelfth opening extending in the second direction, the twelfth opening exposing a sidewall of the eleventh opening, a thirteenth opening extending in the first direction, the thirteenth opening exposing a sidewall of the twelfth opening, and a fourteenth opening extending in the second direction, the fourteenth opening exposing a sidewall of the thirteenth opening.
13. The alignment mark of claim 2, further comprising a third plurality of device openings and a fourth plurality of device openings located in a layer to be processed on the device region.
14. The alignment mark of claim 1, wherein the substrate further comprises: the device comprises a substrate and a layer to be etched, wherein the layer to be processed is positioned on the substrate and is positioned on the layer to be etched.
15. The alignment mark of claim 14, wherein the layer to be etched comprises: the device comprises a device layer and a hard mask layer positioned on the device layer, wherein the layer to be processed is positioned on the hard mask layer.
16. The alignment mark of claim 15, further comprising: a first stop layer located between the substrate and the device layer; a second stop layer located between the device layer and the hard mask layer; and the third stopping layer is positioned between the hard mask layer and the layer to be processed.
17. A method of forming an alignment mark, comprising:
providing a substrate, wherein the substrate comprises a marking area, and the marking area is provided with a layer to be processed;
forming a first mark opening in the layer to be processed on the mark area by adopting first patterning;
performing second patterning processing on the layer to be processed by taking the first mark opening as an alignment mark, and forming a second mark opening in the layer to be processed on the mark region, wherein the first mark opening and the second mark opening are mutually separated;
the first indicia opening includes: a first opening extending along a first direction, a second opening extending along a second direction, the first direction being perpendicular to the second direction, the first opening exposing a sidewall of the second opening;
the second indicia opening comprises: and the third opening and the fourth opening extend along the first direction, the fourth opening exposes the side wall of the third opening, the first opening and the third opening are arranged in parallel along the second direction, the third opening has a first width dimension along the second direction, the fourth opening has a second width dimension along the second direction, and the second width dimension is larger than the first width dimension.
18. The method of forming an alignment mark of claim 17, wherein the method of first patterning comprises: forming a first patterning layer on the layer to be treated, wherein the first patterning layer exposes part of the top surface of the layer to be treated; etching the layer to be processed by taking the first graphical layer as a mask, and forming the first mark opening in the layer to be processed; after forming the first mark opening, the first patterned layer is removed.
19. The method of forming an alignment mark of claim 18, further comprising, prior to forming the first patterned layer: and forming a first sacrificial layer on the layer to be treated, and a first anti-reflection layer on the first sacrificial layer, wherein the first patterning layer is positioned on the first anti-reflection layer.
20. The method of forming an alignment mark of claim 17, wherein the method of second patterning comprises: forming a second patterned layer on the layer to be treated, wherein the second patterned layer exposes part of the top surface of the layer to be treated; etching the layer to be processed by taking the second graphical layer as a mask, and forming a second mark opening in the layer to be processed; after forming the second mark opening, the second patterned layer is removed.
21. The method of forming an alignment mark of claim 20, further comprising, prior to forming the second patterned layer: and forming a second sacrificial layer on the layer to be treated, wherein the second sacrificial layer fills the first mark opening, and is positioned on a second anti-reflection layer on the second sacrificial layer, and the second patterned layer is positioned on the second anti-reflection layer.
22. The method of forming an alignment mark of claim 17, wherein the substrate further comprises: a device region; the marking region surrounds the device region, the layer to be processed is further positioned on the device region, and the first marking opening and the second marking opening are positioned at corner positions of the device region.
23. The method of forming an alignment mark of claim 22, further comprising, during forming the first mark opening: and forming a plurality of first device openings in the layer to be treated on the device region.
24. The method of forming an alignment mark of claim 23, further comprising, during forming the second mark opening: and forming a plurality of second device openings in the layer to be treated on the device region.
25. The method of forming an alignment mark of claim 17, wherein the second mark opening further comprises: a fifth opening and a sixth opening extending along the second direction, the sixth opening exposing a sidewall of the fifth opening, the second opening and the fifth opening being arranged in parallel along the first direction, the fifth opening having a third width dimension along the first direction, the sixth opening having a fourth width dimension along the first direction, the fourth width dimension being greater than the third width dimension.
26. The method of forming an alignment mark of claim 25, wherein the first width dimension is in a range of 0.3 μm to 0.5 μm; the third width dimension is in the range of 0.3 μm to 0.5 μm.
27. The method of forming alignment marks of claim 25, wherein the first mark opening and the second mark opening have a first pitch dimension therebetween.
28. The method of forming alignment marks of claim 27, wherein the first pitch dimension is a pitch dimension between the first opening and the third opening, or a pitch dimension between the second opening and the fifth opening.
29. The method of forming alignment marks of claim 27, wherein the first pitch dimension is in a range of 0.2 μm to 0.4 μm.
30. The method of forming an alignment mark of claim 24, further comprising, after forming the first mark opening and the second mark opening: performing third graphical processing on the layer to be processed by taking the second mark opening as an alignment mark, and forming a third mark opening in the layer to be processed; and performing fourth patterning processing on the layer to be processed by taking the third mark opening as an alignment mark, and forming a fourth mark opening in the layer to be processed, wherein the first mark opening, the second mark opening, the third mark opening and the fourth mark opening are mutually separated.
31. The method of forming an alignment mark of claim 30, wherein the third mark opening and the second mark opening have a second pitch dimension therebetween, and the fourth mark opening and the third mark opening have a third pitch dimension therebetween.
32. The method of forming alignment marks of claim 30, wherein the third mark opening comprises: a seventh opening extending in the first direction, an eighth opening extending in the second direction, the eighth opening exposing a sidewall of the seventh opening, a ninth opening extending in the first direction, the ninth opening exposing a sidewall of the eighth opening, and a tenth opening extending in the second direction, the tenth opening exposing a sidewall of the ninth opening.
33. The method of forming an alignment mark of claim 30, wherein the fourth mark opening comprises: an eleventh opening extending in the first direction, a twelfth opening extending in the second direction, the twelfth opening exposing a sidewall of the eleventh opening, a thirteenth opening extending in the first direction, the thirteenth opening exposing a sidewall of the twelfth opening, and a fourteenth opening extending in the second direction, the fourteenth opening exposing a sidewall of the thirteenth opening.
34. The method of forming an alignment mark of claim 30, further comprising, during forming the third mark opening: and forming a plurality of third device openings in the layer to be treated on the device region.
35. The method of forming an alignment mark of claim 34, further comprising, during forming the fourth mark opening: and forming a plurality of fourth device openings in the layer to be treated on the device region.
36. The method of forming an alignment mark of claim 17, wherein the substrate further comprises: the device comprises a substrate and a layer to be etched, wherein the layer to be processed is positioned on the substrate and is positioned on the layer to be etched.
37. The method of forming an alignment mark of claim 36, wherein the layer to be etched comprises: the device comprises a device layer and a hard mask layer positioned on the device layer, wherein the layer to be processed is positioned on the hard mask layer.
38. The method of forming an alignment mark of claim 37, further comprising: a first stop layer located between the substrate and the device layer; a second stop layer located between the device layer and the hard mask layer; and the third stopping layer is positioned between the hard mask layer and the layer to be processed.
39. The method of forming alignment marks of claim 35, further comprising, after forming the first device opening, the second device opening, the third device opening, and the fourth device opening:
and forming a first side wall on the side walls of the first device opening, the second device opening, the third device opening and the fourth device opening.
40. The method of forming an alignment mark as claimed in claim 39, further comprising, during forming said first sidewall: and forming second side walls on the side walls of the first mark opening, the second mark opening, the third mark opening and the fourth mark opening.
41. The method of forming an alignment mark of claim 40, further comprising, after forming said first sidewall and said second sidewall: removing the layer to be treated; and etching the substrate by taking the first side wall and the second side wall as masks, and forming a graphical opening in the substrate.
CN202010911176.8A 2020-09-02 2020-09-02 Alignment mark and forming method thereof Active CN114200796B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010911176.8A CN114200796B (en) 2020-09-02 2020-09-02 Alignment mark and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010911176.8A CN114200796B (en) 2020-09-02 2020-09-02 Alignment mark and forming method thereof

Publications (2)

Publication Number Publication Date
CN114200796A CN114200796A (en) 2022-03-18
CN114200796B true CN114200796B (en) 2024-01-26

Family

ID=80644417

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010911176.8A Active CN114200796B (en) 2020-09-02 2020-09-02 Alignment mark and forming method thereof

Country Status (1)

Country Link
CN (1) CN114200796B (en)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002236371A (en) * 2000-12-05 2002-08-23 Dainippon Printing Co Ltd Method for manufacturing rugged pattern layer and liquid crystal display and color filter manufactured by using the method
JP2003234272A (en) * 2002-02-07 2003-08-22 Sanyo Electric Co Ltd Semiconductor apparatus and its manufacturing method
TW200919548A (en) * 2007-07-20 2009-05-01 Toshiba Kk Method of manufacturing a semiconductor device
TW201011811A (en) * 2008-09-03 2010-03-16 Macronix Int Co Ltd Alignment mark and method of getting position reference for wafer
CN102290330A (en) * 2011-08-29 2011-12-21 上海宏力半导体制造有限公司 Forming method of capacitor structure
WO2014134888A1 (en) * 2013-03-08 2014-09-12 京东方科技集团股份有限公司 Substrate alignment mark and manufacturing method therefor, and substrate
CN104124203A (en) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure forming method
WO2017067305A1 (en) * 2015-10-19 2017-04-27 无锡华润上华科技有限公司 Alignment mark, method for forming alignment mark, and semiconductor component
CN107037699A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of mark structure
CN107785242A (en) * 2016-08-31 2018-03-09 中芯国际集成电路制造(上海)有限公司 Triple patterned methods
CN111077685A (en) * 2018-10-22 2020-04-28 三星显示有限公司 Display device
CN111508897A (en) * 2019-01-31 2020-08-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6331634B2 (en) * 2014-04-17 2018-05-30 住友電気工業株式会社 Method for manufacturing silicon carbide semiconductor device
CN109643700B (en) * 2018-11-21 2019-09-10 长江存储科技有限责任公司 Method, device and structure for the engagement alignment mark at joint interface

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002236371A (en) * 2000-12-05 2002-08-23 Dainippon Printing Co Ltd Method for manufacturing rugged pattern layer and liquid crystal display and color filter manufactured by using the method
JP2003234272A (en) * 2002-02-07 2003-08-22 Sanyo Electric Co Ltd Semiconductor apparatus and its manufacturing method
TW200919548A (en) * 2007-07-20 2009-05-01 Toshiba Kk Method of manufacturing a semiconductor device
TW201011811A (en) * 2008-09-03 2010-03-16 Macronix Int Co Ltd Alignment mark and method of getting position reference for wafer
CN102290330A (en) * 2011-08-29 2011-12-21 上海宏力半导体制造有限公司 Forming method of capacitor structure
WO2014134888A1 (en) * 2013-03-08 2014-09-12 京东方科技集团股份有限公司 Substrate alignment mark and manufacturing method therefor, and substrate
CN104124203A (en) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure forming method
WO2017067305A1 (en) * 2015-10-19 2017-04-27 无锡华润上华科技有限公司 Alignment mark, method for forming alignment mark, and semiconductor component
CN107037699A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of mark structure
CN107785242A (en) * 2016-08-31 2018-03-09 中芯国际集成电路制造(上海)有限公司 Triple patterned methods
CN111077685A (en) * 2018-10-22 2020-04-28 三星显示有限公司 Display device
CN111508897A (en) * 2019-01-31 2020-08-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same

Also Published As

Publication number Publication date
CN114200796A (en) 2022-03-18

Similar Documents

Publication Publication Date Title
KR100843870B1 (en) Method for manufacturing fine pattern of a semiconductor device
US5300379A (en) Method of fabrication of inverted phase-shifted reticle
US20070082296A1 (en) Method of forming micro-patterns using multiple photolithography process
US20110191728A1 (en) Integrated circuit having line end created through use of mask that controls line end shortening and corner rounding arising from proximity effects
KR100403933B1 (en) Method for fabricating mask
KR100907898B1 (en) Semiconductor device manufacturing method
KR0156316B1 (en) Patterning method of semiconductor device
CN114200796B (en) Alignment mark and forming method thereof
US6630408B1 (en) Self alignment process to fabricate attenuated shifting mask with chrome border
US6210842B1 (en) Method for fabricating stencil mask
KR100230351B1 (en) Pattern forming method
CN115458507A (en) Alignment mark and forming method thereof
US6686129B2 (en) Partial photoresist etching
JPH10106971A (en) Manufacture for semiconductor device
KR100930380B1 (en) How to fix defects in the photomask
CN113130303B (en) Mask and triple patterning method
JP5423073B2 (en) Stencil mask and electron beam exposure method
JPH04291345A (en) Pattern forming method
JP2001133957A (en) Photomask capable of obtaining inclined pattern section on photoresist
US8507190B2 (en) Method for preparing alignment mark for multiple patterning
KR100209231B1 (en) Method of forming fine pattern
KR100866725B1 (en) Method for manufacturing fine pattern of a semiconductor device
CN116954012A (en) Optical proximity correction method
KR100289664B1 (en) Manufacturing Method of Exposure Mask
CN117008413A (en) Method for manufacturing photoresist undercut morphology

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant