CN114189314B - BMC signal receiving method and device, USB power supply and readable storage medium - Google Patents
BMC signal receiving method and device, USB power supply and readable storage medium Download PDFInfo
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Abstract
A BMC signal receiving method, device, USB power supply and readable storage medium. The method comprises the following steps: sequentially carrying out analog filtering and first-stage digital filtering on the received BMC signal to obtain a first-stage digital filtering result signal; performing second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal; sampling the second-level digital filtering result signal to obtain a sampling result signal; decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal; if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level; the preset intermediate position is determined according to the baud rate and the duty cycle of the previous bit of the first-stage digital filtering result signal. By applying the scheme, the reliability of BMC signal transmission can be improved.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a BMC signal receiving method and device, a USB power supply and a readable storage medium.
Background
A serial bus (Universal Serial Bus, USB) Type-C Power Delivery (PD) protocol is a Type-C interface based Power transfer protocol. The USB PD protocol supports various combinations of voltage and current, can support 100W (20V/5A) power transmission at maximum, supports power supply role conversion, and meets the power supply requirements of most electronic equipment.
In the USB Type-C interface, a configuration channel (Configure Channel, CC) line is used as a dedicated plug detect and PD communication channel. It employs a half duplex communication mechanism, transmitting data using bi-directional tag coding (Biphase Mark Coding, BMC). BMC coding belongs to a phase modulation coding technology, and is a coding method for mixing clock and data together for transmission. The signal encoded using the BMS is referred to as a BMS signal. The PD protocol allows for a certain frequency deviation of the code.
However, in practical application, the baud rate deviation exists between the transmitting end and the receiving end, and the local clock precision is different, so that the communication channel is easily affected by the load of the transmission medium, high voltage and heavy current of the power supply and the ground wire, noise and the like. The communication channel is affected, which may cause the BMC signal to be interfered, causing the BMC signal to be distorted by distortion, and eventually causing communication failure.
Disclosure of Invention
The invention aims to solve the problems that: and the reliability of BMC signal transmission is improved.
In order to solve the above problems, an embodiment of the present invention provides a method for receiving a BMC signal, where the method includes: sequentially carrying out analog filtering and first-stage digital filtering on the received BMC signal to obtain a first-stage digital filtering result signal; performing second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal; sampling the second-stage digital filtering result signal to obtain a sampling result signal; decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal; if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level; i is a positive integer; when i is more than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
The embodiment of the invention also provides a BMC signal receiving device, which comprises: the analog filter circuit is suitable for sequentially performing analog filtering on the received BMC signals; the first-stage digital filter circuit is suitable for carrying out first-stage digital filtering on the analog filtered BMC signal to obtain a first-stage digital filtering result signal; the second digital filtering circuit is suitable for carrying out second digital filtering on the first digital filtering signal to obtain a second digital filtering result signal; the sampling circuit is suitable for sampling the second-level digital filtering result signal to obtain a sampling result signal; the decoding circuit is suitable for decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal; if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level; i is a positive integer; when i is more than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
The embodiment of the invention also provides a USB power supply, which comprises the BMC signal receiving device.
Embodiments of the present invention also provide a computer readable storage medium having stored thereon a computer program for execution by a processor to perform the steps of any of the methods described above.
The embodiment of the invention also provides a USB power supply, which comprises a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor executes the steps of any one of the methods when running the computer program.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
by applying the scheme of the invention, when the middle position of the ith bit time of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, the ith bit of the second-stage digital filtering result signal is set, otherwise, the ith bit is kept at a low level, so that the influence of interference pulses in the first-stage digital filtering result signal on the second-stage digital filtering can be reduced as much as possible, and the reliability of BMC signal transmission is improved. In addition, the middle position of the ith bit of the first-stage digital filtering result signal is determined according to the baud rate and the duty cycle of the previous bit of the first-stage digital filtering result signal, so that the second-stage digital filtering result of the current bit can be dynamically adjusted based on the baud rate and the duty cycle of the previous bit, communication failure caused by the baud rate imbalance or the duty cycle imbalance of the sending end and the receiving end is avoided, and the reliability of BMC signal transmission is further improved.
Drawings
Fig. 1 is a flowchart of a BMC signal receiving method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the bit length of a BMC signal portion;
FIG. 3 is a diagram showing a normal waveform of each signal when the BMC signal is free of interference;
FIG. 4 is a schematic waveform diagram of signals when the BMC signal is disturbed;
fig. 5 is a schematic structural diagram of a BMC signal receiving apparatus 50 according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a USB power supply according to an embodiment of the present invention;
fig. 7 is a schematic diagram of BMC signal reception according to an embodiment of the present invention.
Detailed Description
BMC coding belongs to a phase modulation coding technology, and is a coding method for mixing clock and data together for transmission. The BMC code is characterized in that: at the beginning of each bit, the level is toggled. A level change is used within a bit to represent logic, a logic "1" if the level jumps among bits, and a logic "0" otherwise. By using BMC coding, the transmitting end and the receiving end can correctly transmit and receive data only by one data line, and good synchronism is maintained at the transmitting and receiving ends.
The PD protocol specifies a BMC signaling frequency of 300K, i.e. 3.33us per bit. The PD protocol allows for +/-10% frequency deviation of the code.
However, in practical application, the BMC signal is interfered, and the interfered BMC signal has a duty cycle imbalance and a baud rate imbalance, so that the rising and falling time of the BMC signal does not meet the system requirement, and finally, the BMC signal is distorted, distorted and failed in communication.
In order to solve the problem, the invention provides a BMC signal receiving method, in the method, the middle position of each bit of a first-stage digital filtering result signal can be dynamically adjusted according to the baud rate and the duty cycle of the previous bit, so that the middle position of the current bit is dynamically adjusted based on the baud rate and the duty cycle of the previous bit, the influence of interference pulses in the first-stage digital filtering result signal on the second-stage digital filtering can be reduced as much as possible, and the reliability is effectively improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 1, an embodiment of the present invention provides a method for receiving a BMC signal, which may include the steps of:
and step 11, sequentially performing analog filtering and first-stage digital filtering on the received BMC signal to obtain a first-stage digital filtering result signal.
In a specific implementation, the BMC signal is an analog signal. When the BMC signal is subjected to analog filtering, low-pass filtering of less than 30ns can be performed, so that the BMC signal of less than 30ns can pass through.
In some embodiments, after the low-pass filtering is performed on the BMC signal, a DC Offset removal (DC Offset) process may be performed on the low-pass filtered BMC signal, that is, the DC Offset in the ac signal is eliminated, so as to filter out an interference signal generated by the BMC signal due to the DC Offset.
In a specific implementation, the BMC signal after dc offset removal may be subjected to a first stage digital filtering. After the BMC signal subjected to DC offset removal treatment is subjected to first-stage digital filtering, burr pulses in the range of 100 ns-1000 ns are filtered. After the first stage of digital filtering, the overall delay (Latency) is a few bits, which can be determined according to the programmed filter depth. For example, a trigger with 4-stage depth can be used, and after the first-stage digital filtering, the BMC signal subjected to DC offset removal is wholly delayed by 1-16 programmable bits. After the first-stage digital filtering, the obtained first-stage digital filtering result signal is a digital signal.
And step 12, performing second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal.
And if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level. i is a positive integer; and when i is more than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
In the current USB communication standard protocol, the baud rate allowed by the BMC signal ranges from 270Kbps to 330Kbps. The Baud (Baud), i.e., the modulation rate, refers to the rate at which the effective data signal modulates the carrier, i.e., the number of changes in the carrier modulation state per unit time. The baud rate, which is a measure of the symbol transmission rate, is expressed in terms of the number of carrier modulation state changes per unit time, i.e., the number of transmitted symbol symbols per unit time. Symbols, such as binary symbols, hexadecimal symbols, and the like. In the digital signal, one symbol is a pulse signal.
In a specific implementation, the preset middle position of the ith bit of the first-stage digital filtering result signal is not the middle position of the ith bit in the actual transmission process, but the middle position estimated according to the baud rate of the ith-1 bit.
In an embodiment of the present invention, performing a second level digital filtering on the first level digital filtered signal to obtain a second level digital filtered result signal may include: detecting the edge of the ith bit of the first-stage digital filtering result signal to obtain an edge detection result signal; judging whether the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the ith bit of the edge detection result signal, if so, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level.
In particular implementations, the predetermined intermediate position of the ith bit of the first stage digital filter result signal may be determined by a variety of methods, and is not limited herein.
In an embodiment of the present invention, a preset intermediate position of an i-th bit of the first-stage digital filtering result signal may be determined according to a baud rate and a duty cycle of a previous bit of the first-stage digital filtering result signal.
In implementations, each bit of the received first stage digital filter result signal may be counted separately. Based on the individual count result for each bit, the bit for that bit may be determined, thereby determining the baud rate for that bit.
For the ith bit, according to the bit of the ith-1 bit of the first-stage digital filtering result signal, the baud rate of the ith-1 bit of the first-stage digital filtering result signal, and then according to the duty ratio of the previous bit of the first-stage digital filtering result signal, judging whether to adjust the baud rate of the ith bit of the first-stage digital filtering result signal, and finally according to the judging result, determining the counting length of the ith bit of the first-stage digital filtering result signal, and obtaining the preset middle position of the ith bit of the first-stage digital filtering signal.
Typically, the duty cycle of each bit of the first stage digital filter result signal should be equal to 1. Therefore, after determining the baud rate of the i-1 th bit, if the duty cycle of the previous bit of the first-stage digital filtering result signal is smaller than 1, it indicates that the count length of the previous bit is greater than the actual length, and the count length of the i-th bit of the first-stage digital filtering result signal should be reduced. If the duty ratio of the previous bit of the first-stage digital filtering result signal is greater than 1, the counting length of the previous bit is smaller than the actual length, and the counting length of the ith bit of the first-stage digital filtering result signal is increased. If the duty ratio of the previous bit of the first-stage digital filtering result signal is equal to 1, the counting length is equal to the actual length, and the counting length of the previous bit is taken as the counting length of the ith bit.
For example, when the duty ratio of the i-1 th bit of the first stage digital filtering result signal is less than 1, if the count length of the i-1 th bit is 8, the count length of the i-th bit should be less than 8.
In a specific implementation, when counting each bit of the first-stage digital filtering result signal, according to the determined baud rate, a preset time length required by each bit of the first-stage digital filtering signal is estimated and obtained, and then based on the preset time length, the step length of the counter is adjusted, so that the counting length of each bit of the first-stage digital filtering signal is an even number of counter step lengths. For example, the preset duration is 80ns, and the counter step length can be set to be 10ns, and the corresponding count length of each bit of the first-stage digital filtering signal is 8 counter step lengths.
In an implementation, for each bit of the first stage digital filtered signal, a separate count is performed, e.g., the counter counts from 0 in the first bit and counts again from 0 in the second bit. Thus, each bit corresponds to a middle position of the count length, i.e., a preset middle position of each bit of the first-stage digital filtered signal.
Based on the baud rate and the duty cycle of the previous bit of the first-stage digital filtering result signal, determining a preset middle position of the current bit, and performing second-stage digital filtering on the first-stage digital filtering result signal according to the determined preset middle position, so that interference pulses which do not meet the baud rate requirement can be filtered, and the obtained second-stage digital filtering result signal can meet the baud rate requirement, and BCM signal distortion caused by baud rate imbalance and duty cycle imbalance is avoided.
In a specific implementation, for any bit of the first-stage digital filtering result signal, the second-stage digital filtering result signal remains low when a preset intermediate position of the bit is not reached. When reaching the preset middle position of the bit, if the edge of the first-stage digital filtering result signal is just corresponding to the moment, the second-stage digital filtering result signal is set, namely, the low level is converted into the high level and is kept until the bit is ended.
In a specific implementation, determining whether a certain moment corresponds to an edge of the first-stage digital filtering result signal may be determined by performing edge detection on the first-stage digital filtering result signal. Specifically, the edge of the first-stage digital filtering result signal may be detected first to obtain an edge detection result signal, and then it is determined whether the preset middle position of each bit of the first-stage digital filtering signal corresponds to the edge pulse of the edge detection result signal, if yes, the second-stage digital filtering result signal is set, otherwise, the second-stage digital filtering result signal is kept at a low level.
In a specific implementation, the edge detection result signal keeps a low level when the edge of the first-stage digital filtering result signal is not detected, and changes from a low level to a high level when the edge of the first-stage digital filtering result signal is detected, and the edge detection result signal appears as an edge pulse. When reaching the preset middle position of each bit of the first-stage digital filtering signal, if the second-stage digital filtering signal corresponds to the edge pulse of the edge detection result signal at the same time, the second-stage digital filtering result signal is set, otherwise, the second-stage digital filtering result signal is kept at a low level.
In practical application, in the process of receiving a frame of BMC signal, a receiving end will generally first receive a preamble corresponding to the frame of BMC signal, where the preamble includes the first several bits of the BMC signal. Upon receiving the preamble, it may be determined whether the baud rate of each bit of the preamble is within the allowed baud rate range. If the received BMC signal is within the allowed baud rate range, after receiving the preamble, receiving the corresponding BMC signal, otherwise stopping receiving the subsequent BMC signal.
In practical application, due to factors such as high impedance of the receiving end, the duty ratio of the first bit in the first-stage digital filtering signal is inconsistent with the duty ratio of other bits. Specifically, referring to fig. 2, it is assumed that the length of the other bits of the first-stage digital filtered signal is 1UI, but the existence of high impedance makes the actual high-level duration tStartDrive when the receiving end receives the first bit of the first-stage digital filtered signal. Whereas tStartDrive is present such that the first bit of the first stage digital filtered signal has a length of more than 1UI, i.e. is actually inconsistent with the bits of the other bits, i.e. the duty cycle is off-set.
In view of the above, in order to avoid that the first bit of the first-stage digital filtered signal is filtered due to being mistaken for an interference pulse, in an embodiment of the present invention, special consideration is performed on the first bit of the first-stage digital filtered signal, so that the first bit of the first-stage digital filtered signal can be decoded and output, thereby obtaining the data information carried by the first bit.
Specifically, a second count length corresponding to a first bit of the first-stage digital filtered signal may be set to be greater than the first count lengths of other bits of the first-stage digital filtered signal, thereby enabling the second-stage digital filtered result signal to include the first bit of the first-stage digital filtered signal. For example, when the first count length is 8 count steps, the second count length may be set to 10 count steps.
In a specific implementation, when i=1, the preset middle position of the first bit of the first stage digital filtering result signal may be determined according to the baud rate range allowed by the BMC signal (i.e. 270Kbps to 330 Kbps).
In an embodiment of the present invention, a preset middle position of the first bit of the first-stage digital filtering result signal may be determined according to the maximum baud rate allowed by the BMC signal, so that the second-stage filtering result signal includes the information of the first bit to the maximum extent. For example, when the maximum baud rate allowed by the BMC signal is 330Kbps, the first-stage digital filtering result signal has a first bit length=1/330 k≡3.3us. Accordingly, the preset intermediate position of the first bit is 151.5 ns.
In another embodiment of the present invention, a certain clock precision tolerance may be added on the basis of the baud rate range allowed by the BMC signal. For example, the clock precision tolerance can be increased by 3% -5%, and the total error range can be enlarged to 15%. At this time, the baud rate is allowed to range from 270 x (1-15%) Kbps to 330 (1+15%) Kbps.
And step 13, sampling the second-stage digital filtering result signal to obtain a sampling result signal.
In a specific implementation, at a preset end position of each bit of the first-stage digital filtering result signal, whether the second-stage digital filtering result signal corresponds to an edge of the first-stage digital filtering result signal is judged, if yes, the second-stage digital filtering result signal is sampled, otherwise, the second-stage digital filtering result signal is not sampled. The preset end position of each bit of the first-stage digital filtering result signal is preset according to the baud rate range allowed by the BMC signal.
And the preset middle position of each bit of the first-stage digital filtering result signal is the middle position of the preset starting position and the preset ending position of each bit of the first-stage digital filtering result signal. Similar to the preset intermediate position of each bit of the first-stage digital filter result signal, the preset end position of each bit of the first-stage digital filter result signal is also determined according to the baud rate of the previous bit. In other words, after the baud rate of the current bit is determined based on the baud rate of the previous bit, the preset intermediate position and the preset end position of the current bit are determined.
In a specific implementation, if the preset end position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, sampling the ith bit of the second-stage digital filtering result signal, otherwise, not sampling the ith bit of the second-stage digital filtering result signal. The resulting sample result signal is delayed with respect to the second digital filtered result signal.
By setting the preset end position of each bit of the first-stage digital filtering result signal and sampling the second-stage digital filtering result signal, sampling dislocation caused by the baud rate imbalance and duty cycle imbalance of the first-stage digital filtering result signal can be avoided.
And step 14, decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal.
In an implementation, if the sampling result signal level transitions between each bit of the first stage digital filtering result signal, then a logic "1" is decoded and otherwise a logic "0" is decoded.
From the above, it can be seen that the BMC signal receiving method in the embodiment of the present invention aims to dynamically monitor the baud rate and the duty cycle, and then set a reasonable sampling point, so as to ensure the reliability of communication.
The following is a detailed description with reference to fig. 3 and 4:
referring to fig. 3 and 4, clk is a local clock signal. bmc_in_gap is the first level digital filtering result signal, edge_both is the edge detection result signal, bmc_bitwd_cnt is the count signal, bit_key is the second level digital filtering result signal, rx_bitsample is the sampling trigger signal, and rx_bit_dec is the sampling result signal.
Fig. 3 is a schematic diagram of normal waveforms of signals when the BMC signal is not interfered. And detecting the edge of the first-stage digital filtering result signal bmc_in_gap to obtain an edge detection result signal edge_both. The position of the edge detection result signal edge_both corresponding to the first-stage digital filtering result signal bmc_in_gap appears as an edge pulse.
When the edge of the first-stage digital filtering result signal bmc_in_gap is detected, the first-stage digital filtering result signal bmc_in_gap is started to count each bit, as indicated by a count signal bmc_bitwd_cnt. The corresponding count length of each bit of the first-stage digital filtering result signal bmc_in_gap is 8, and the count value is 0-7. The preset intermediate position of each bit of the first-stage digital filtering result signal bmc_in_gap, namely the end position of the count value 3.
The second digital filtering result signal bit_key remains low until the end position of the count value 3. After the end position of the count value 3, if an edge pulse of the edge detection result signal adge_both is encountered, the second level digital filtering result signal bitone_key is set up until the end of the bit.
At the counting end position of each bit of the first-stage digital filtering result signal bmc_in_gap, the sampling trigger signal rx_bitsample is at a high level so as to trigger the sampling of the second-stage digital filtering result signal bitone_key.
When the sampling trigger signal rx_bit_sample is at a high level, if an edge pulse of the edge detection result signal edge_both is encountered, the sampling result signal rx_bit_dec is at a high level, otherwise, is at a low level.
For example, at time t1, the sampling trigger signal rx_bitsample is at a high level, and at this time, an edge pulse of the edge detection result signal edge_both is just encountered, and if the second level digital filtering result signal bit_key is at a high level, the sampling result signal rx_bit_dec delays to output a sampling result at a high level. At time t2, the sampling trigger signal rx_bitsample is at a high level, and at the moment, an edge pulse of the edge detection result signal adge_both is just encountered, and if the second level digital filtering result signal bitone_key is at a low level, the sampling result signal rx_bit_dec delays to output a sampling result at the low level.
Fig. 4 is a schematic waveform diagram of each signal when the BMC signal has interference. Referring to fig. 4, since the BMC signal has an interference, the first stage digital filtering result signal bmc_in_gap has an interference pulse of a low level at time t2 and has an interference pulse of a high level at time t 3.
When the BMC receiving method in the embodiment of the invention is applied to receive the BMC signal, the edge of the first-stage digital filtering result signal bmc_in_gap is detected, and an edge detection result signal edge_both is obtained. When the edge of the first-stage digital filtering result signal bmc_in_gap is detected, the first-stage digital filtering result signal bmc_in_gap is started to count each bit, as indicated by a count signal bmc_bitwd_cnt. The preset intermediate position of each bit of the first-stage digital filtering result signal bmc_in_gap is still the end position of the count value 3.
The second digital filtering result signal bit_key remains low until the end position of the count value 3. At this time, even if there is a low-level interference pulse at time t2, the second digital filtering result signal bitone_keep remains at a low level, and the second digital filtering result signal bitone_keep is not affected by the interference pulse, i.e., the interference pulse is filtered out.
Until the count value 3 ends, and at the same time encounters an edge pulse of the edge detection result signal add_both, the second digital filtering result signal bit_key is not set until the bit ends.
Similarly, at time t3, the second digital filtering result signal bitone_key remains low since no edge pulse of the edge detection result signal edge_both is encountered. Since the time t3 is not the preset end position of the bit, the sampling result signal rx_bit_dec is also low.
Therefore, by adopting the method for receiving the BMC signal in the embodiment of the invention, even if the front bit and the back bit have interference, the interference can be effectively filtered, and the communication failure caused by sampling dislocation and communication baud rate imbalance due to duty cycle imbalance is avoided.
In order to better understand and implement the present invention, a user terminal and a computer-readable storage medium corresponding to the above method are described in detail below.
Referring to fig. 5, an embodiment of the present invention provides a BMC signal receiving apparatus 50, where the apparatus 50 may include: an analog filter circuit 51, a first stage digital filter circuit 52, a second stage digital filter circuit 53, a sampling circuit 54, and a decoding circuit 55. Wherein:
The analog filter circuit 51 is adapted to sequentially perform analog filtering on the received BMC signal;
the first-stage digital filtering circuit 52 is adapted to perform first-stage digital filtering on the analog filtered BMC signal to obtain a first-stage digital filtering result signal;
the second digital filtering circuit 53 is adapted to perform second digital filtering on the first digital filtered signal to obtain a second digital filtered result signal;
the sampling circuit 54 is adapted to sample the second digital filtering result signal to obtain a sampling result signal;
the decoding circuit 55 is adapted to decode the sampling result signal to obtain a decoded signal corresponding to the BMC signal;
if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level; i is a positive integer; when i is more than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal.
In an embodiment of the present invention, the second digital filtering circuit 53 may include: the edge detection module 531, the judgment module 532 and the output module 533. Wherein:
The edge detection module 531 is adapted to detect an edge of the ith bit of the first stage digital filtering result signal, to obtain an edge detection result signal;
the judging module 532 is adapted to judge whether the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the ith bit of the edge detection result signal;
the output module 533 is adapted to start the output second digital filtering result signal at the i-th bit position when the judging module judges that the preset intermediate position of the i-th bit of the first digital filtering result signal corresponds to the edge pulse of the edge detection result signal, and otherwise, keep the output second digital filtering result signal at the low level.
In an embodiment of the present invention, the second digital filtering circuit 53 may further include: a first count storage module (not shown) and a second count storage module (not shown). Wherein:
the first count storage module is suitable for storing first count lengths corresponding to other bits except the first bit in the first-stage digital filtering signal;
the second count storage module is suitable for storing a preset count difference value; and the sum of the preset count difference value and the first count length is a second count length corresponding to a first bit in the first-stage digital filtering signal.
In an implementation, the apparatus 50 may further be configured with a counter (not shown) that may count bits of the first stage digital filtering result signal according to the determined count length of the bits. The counter may be connected to the first count storage module and the second count storage module, and when counting the first bits of the first-stage digital filtering result signal, obtains a second count length from the second count storage module, and performs a count operation. When counting other bits of the first-stage digital filtering result signal, a corresponding first count length is obtained from the first count storage module, and a counting operation is performed.
In an embodiment of the present invention, a second count length corresponding to a first bit of the first-stage digital filtered signal is greater than a first count length of other bits of the first-stage digital filtered signal, so that the second-stage digital filtered result signal includes the first bit of the first-stage digital filtered signal.
In an embodiment of the present invention, when i=1, the preset middle position of the first bit of the first stage digital filtering result signal is determined according to the maximum baud rate allowed by the BMC signal.
In an embodiment of the present invention, the sampling circuit 54 is adapted to sample the ith bit of the second digital filtering result signal when the preset end position of the ith bit time of the first digital filtering result signal corresponds to the edge of the ith bit of the first digital filtering result signal, and otherwise not sample the ith bit of the second digital filtering result signal.
The BMC signal receiving device 50 in the embodiment of the invention avoids the problem that complex analog circuit filtering is not easy to adjust, and adjusts the BMC communication robustness in a digital programmable mode. From a cost perspective, the first stage digital filter circuit 52 may be a 4 stage depth trigger. The counting section in the second digital filter circuit 53 can be hardware-counted by using a 6-bit adjustable width counter and a 2-bit baud rate preset tolerance range. The device 50 accepts single-bit flipping, clears the end-of-every-bit counter, and decodes and outputs the corresponding 0 or 1. The noise signal can be received within 20 of the whole triggers, and the power output deterministic test (Power Delivery Determinstic Test) of the USB protocol organization can be satisfied without simulation assistance in actual measurement of a Field programmable gate array (Field-Programmable Gate Array, FPGA).
The embodiment of the invention also provides a USB power supply, which comprises the BMC signal receiving device 50.
Specifically, referring to fig. 6, the USB power supply 61, as a power supply terminal, may perform BMC communication with the device terminal (i.e., a transmitting terminal) 62 through a configuration channel.
After the BMC signal sent by the device end 62 is received by the USB power supply 61 through the configuration channel, the received BMC signal is decoded by the BMC signal receiving apparatus 50, the decoded data is transmitted to the protocol layer (PRL) and the policy management layer apparatus (PE) 63, and the protocol layer and the policy management layer apparatus 63 perform operations such as header removal and tail reporting on the decoded data according to a transmission protocol, so as to obtain effective information carried in the BMC signal. The effective information carried in the BMC signal is stored in a corresponding memory 65, such as ROM, RAM, etc., under control of an MCU Core 64 via a data selection BUS MUX.
In an embodiment of the present invention, referring to fig. 7, in the BMC signal receiving apparatus 50, after analog filtering and DC removal, the BMC signal sequentially performs first-stage digital filtering and second-stage digital filtering, and then decodes and outputs the result to the protocol layer and policy management layer apparatus 63 of the USB power supply 61.
In some embodiments, when the BMC signal is first-stage digitally filtered, MCU core 64 may digitally program, via data selector BUS MUX, the depth of first-stage digital filter circuit 52 to control the depth of first-stage digital filter circuit 52. When the BMC signal is subjected to the second digital filtering, the MCU core 64 may further transmit the baud rate of the second digital filtering circuit 53 to the second digital filtering circuit 53 through the data selector BUS MUX in a digital programming manner, so as to control the baud rate of the second digital filtering circuit 53 to filter the current bit. Thus, the first digital filter circuit 52 may perform a first digital filter on the BMC signal under the control of the MCU core 64, and the second digital filter circuit 53 may perform a second digital filter on the BMC signal under the control of the MCU core 64.
In an embodiment of the present invention, the MCU core 64 may adaptively determine the baud rate of the current bit according to the baud rate of the previous bit, and control the second digital filter circuit 53 to perform decoding.
The USB power supply 61 may further include: other processing modules, such as Analog-to-Digital conversion (ADC) circuits, digital-to-Analog conversion (DAC) circuits, digital processing modules (Digital Blocks), analog processing modules (Analog Blocks), and the like. The MCU core 64 may control the other processing modules via the data selector to perform other processing of the data.
The USB power supply 61 may further include: direct memory access (Direct Memory Access, DMA) controller 66. Under the control of the DMA controller 66, the USB power supply 61 can realize direct data transfer between the internal memory and the external device without the participation of the MCU core 64.
The BMC signal receiving device 50 in the embodiment of the invention can be applied to a USB power supply 61 with a digital-analog hybrid chip, thereby avoiding BMC communication faults caused by deviation of a device end and a power supply end.
The embodiment of the invention also provides another computer readable storage medium, on which computer instructions are stored, and when the computer instructions run, the steps of the BMC signal receiving method in any one of the above embodiments are executed, and are not repeated.
In particular implementations, the computer-readable storage medium may include: ROM, RAM, magnetic or optical disks, etc.
The embodiment of the invention also provides a USB power supply, which can comprise a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor executes the steps of the control method of any one of the electronic devices in the above embodiment when running the computer program, and the steps are not repeated.
With respect to each of the apparatuses and each of the modules/units included in the products described in the above embodiments, it may be a software module/unit, a hardware module/unit, or a software module/unit, and a hardware module/unit. For example, for each device or product applied to or integrated on the chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least part of the modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the rest of the modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a circuit and other hardware mode, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program running in a processor integrated in the chip module, and the rest of the modules/units can be realized in a circuit and other hardware mode; for each device and product applied to or integrated in the terminal, each module/unit contained in the device and product may be implemented in hardware such as a circuit, different modules/units may be located in the same component (for example, a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented in a software program, where the software program runs on a processor integrated in the terminal, and the remaining part of the modules/units may be implemented in hardware such as a circuit.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (15)
1. A BMC signal receiving method, comprising:
sequentially carrying out analog filtering and first-stage digital filtering on the received BMC signal to obtain a first-stage digital filtering result signal;
performing second-stage digital filtering on the first-stage digital filtering signal to obtain a second-stage digital filtering result signal;
sampling the second-stage digital filtering result signal to obtain a sampling result signal;
decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal;
if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level; i is a positive integer; when i is more than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal;
The preset middle position of the ith bit of the first-stage digital filtering result signal is determined by the following method, which comprises the following steps: determining the baud rate of the previous bit of the first-stage digital filtering result signal according to the bit time of the previous bit of the first-stage digital filtering result signal; judging whether the baud rate of the ith bit of the first-stage digital filtering result signal is to be adjusted according to the duty ratio of the previous bit of the first-stage digital filtering result signal; and determining the counting length of the ith bit of the first-stage digital filtering result signal according to the judging result, and obtaining the preset intermediate position of the ith bit time of the first-stage digital filtering signal.
2. The BMC signal receiving method according to claim 1, wherein the performing a second digital filtering on the first digital filtered signal to obtain a second digital filtered result signal comprises:
detecting the edge of the ith bit of the first-stage digital filtering result signal to obtain an edge detection result signal;
judging whether the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the ith bit of the edge detection result signal, if so, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level.
3. The BMC signal receiving method of claim 2, wherein the determining whether to adjust the count length of the i-th bit of the first stage digital filtering result signal according to the duty ratio of the previous bit of the first stage digital filtering result signal comprises:
and when the duty ratio of the previous bit of the first-stage digital filtering result signal is smaller than 1, reducing the counting length of the ith bit of the first-stage digital filtering result signal, otherwise, increasing the counting length of the ith bit of the first-stage digital filtering result signal.
4. The BMC signal receiving method of claim 2, wherein the middle position of the i-th bit of the first-stage digital filtered signal corresponding to the count length is a preset middle position of the i-th bit time of the first-stage digital filtered signal.
5. The BMC signal receiving method of claim 2, wherein the second count length corresponding to the first bit of the first stage digital filtering result signal is greater than the first count length of the other bits of the first stage digital filtering result signal such that the second stage digital filtering result signal includes the first bit of the first stage digital filtering signal.
6. The BMC signal receiving method of claim 1, wherein when i=1, the preset middle position of the first bit of the first stage digital filtering result signal is determined according to a baud rate allowed by the BMC signal.
7. The method of claim 6, wherein the predetermined middle position of the first bit of the first digital filtering result signal is determined according to a maximum baud rate allowed by the BMC signal.
8. The BMC signal receiving method according to claim 1, wherein the sampling the second digital filtering result signal to obtain a sampling result signal comprises:
and if the preset end position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, sampling the ith bit of the second-stage digital filtering result signal, otherwise, not sampling the ith bit of the second-stage digital filtering result signal.
9. A BMC signal receiving apparatus, comprising:
the analog filter circuit is suitable for sequentially performing analog filtering on the received BMC signals;
the first-stage digital filter circuit is suitable for carrying out first-stage digital filtering on the analog filtered BMC signal to obtain a first-stage digital filtering result signal;
The second digital filtering circuit is suitable for carrying out second digital filtering on the first digital filtering signal to obtain a second digital filtering result signal;
the sampling circuit is suitable for sampling the second-level digital filtering result signal to obtain a sampling result signal;
the decoding circuit is suitable for decoding the sampling result signal to obtain a decoding signal corresponding to the BMC signal;
if the preset middle position of the ith bit of the first-stage digital filtering result signal corresponds to the edge of the ith bit of the first-stage digital filtering result signal, starting the ith bit of the second-stage digital filtering result signal, otherwise, keeping the ith bit as a low level; i is a positive integer; when i is more than 1, the preset middle position is determined according to the baud rate and the duty ratio of the previous bit of the first-stage digital filtering result signal;
the preset intermediate position of the ith bit of the first-stage digital filtering result signal is determined by the following method, which comprises the following steps: determining the baud rate of the previous bit of the first-stage digital filtering result signal according to the bit time of the previous bit of the first-stage digital filtering result signal; judging whether the baud rate of the ith bit of the first-stage digital filtering result signal is to be adjusted according to the duty ratio of the previous bit of the first-stage digital filtering result signal; and determining the counting length of the ith bit of the first-stage digital filtering result signal according to the judging result, and obtaining the preset intermediate position of the ith bit time of the first-stage digital filtering signal.
10. The BMC signal receiving device according to claim 9, wherein the second digital filtering circuit comprises:
the edge detection module is suitable for detecting the edge of the ith bit of the first-stage digital filtering result signal to obtain an edge detection result signal;
the judging module is suitable for judging whether the preset middle position of the ith bit of the first-stage digital filtering signal corresponds to the edge pulse of the ith bit of the edge detection result signal or not;
and the output module is suitable for starting the ith bit of the output second-level digital filtering result signal when the judging module judges the preset middle position of the ith bit of the first-level digital filtering signal and corresponds to the edge pulse of the edge detection result signal, and otherwise, the ith bit of the output second-level digital filtering result signal is kept at a low level.
11. The BMC signal receiving device according to claim 10, wherein said second digital filter circuit further comprises:
the first count storage module is suitable for storing first count lengths corresponding to other bits except the first bit in the first-stage digital filtering signal;
the second count storage module is suitable for storing a preset count difference value; the sum of the preset count difference value and the first count length is a second count length corresponding to a first bit in the first-stage digital filtering signal;
And the counting module is suitable for acquiring corresponding counting lengths from the first counting storage module and the second counting storage module and executing counting operation.
12. The BMC signal receiving device of claim 11, wherein the second count length corresponding to the first bit of the first stage digital filtered signal is greater than the first count length of the other bits of the first stage digital filtered signal such that the second stage digital filtered result signal comprises the first bit of the first stage digital filtered signal.
13. A USB power supply, comprising a BMC signal receiving apparatus according to any of claims 9 to 12.
14. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program is executed by a processor to implement the steps of the method of any of claims 1 to 8.
15. A USB power supply comprising a memory and a processor, said memory having stored thereon a computer program capable of being run on said processor, characterized in that said processor executes the steps of the method according to any of claims 1 to 8 when said computer program is run on said processor.
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| CN105915327A (en) * | 2015-02-23 | 2016-08-31 | 瑞萨电子株式会社 | BMC processing circuit, USB power delivery controller and BMC reception method |
| CN108551387A (en) * | 2018-06-27 | 2018-09-18 | 珠海市微半导体有限公司 | A kind of BMC code self-adaptings decoding system and coding/decoding method |
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| CN105915327A (en) * | 2015-02-23 | 2016-08-31 | 瑞萨电子株式会社 | BMC processing circuit, USB power delivery controller and BMC reception method |
| CN108551387A (en) * | 2018-06-27 | 2018-09-18 | 珠海市微半导体有限公司 | A kind of BMC code self-adaptings decoding system and coding/decoding method |
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