CN114189145A

CN114189145A - Voltage modulation circuit and method thereof

Info

Publication number: CN114189145A
Application number: CN202010959680.5A
Authority: CN
Inventors: 简志刚
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2022-03-15

Abstract

The disclosure relates to a voltage modulation circuit and a method thereof. A voltage modulation circuit, comprising: a charge pump circuit and a voltage detection circuit. The voltage detection circuit is coupled with the charge pump circuit. The charge pump circuit adopts a selected power supply mode of a plurality of power supply modes with different power supply conversion rates to perform power supply operation according to a control signal so as to convert a power supply voltage into at least one output voltage, and outputs a wake-up signal when the selected power supply mode is switched to meet a specific condition. The voltage detection circuit is started by the wake-up signal to detect the output voltage and suspend the power supply operation of the charge pump circuit according to the magnitude of at least one output voltage.

Description

Voltage modulation circuit and method thereof

Technical Field

The present invention relates to a charge pump (charge pump) circuit and a related method thereof, and more particularly, to a voltage modulation circuit and a related method thereof.

Background

CODEC chips (CODEC ICs) are mainly used in Personal Computers (PCs) and Consumer Electronics (CE). In terms of CE, both mobile phones and multimedia players (MP3) have emphasized the application of power saving mode to achieve the effect of long standby time. In the PC field, with the popularization of notebook computers (NB) and the rise of tablet computers, the power saving requirement for internal chips is becoming more and more strict. In the power supply planning of the whole encoding and decoding chip, except for a loudspeaker (speaker) driving circuit with the largest output required wattage, an earphone (headphone) driving circuit consumes considerable power. Therefore, in these driving circuits, a charge pump (charge pump) circuit is used to generate a stable output voltage to drive an amplifier in the driving circuit.

The charge pump circuit utilizes power supply modulation technology to make the output voltage change in a large range and maintain a certain level of conversion efficiency so as to provide output voltages of different multiples of the power supply voltage in various operation modes. Therefore, the efficiency of playing audio by the amplifier of the driving circuit at the rear stage of the charge pump circuit can be greatly improved. However, the mode switching process of the charge pump circuit is often accompanied by a situation that the input power voltage is recharged by a large amount of charges. When this happens, it is possible to trigger the input overvoltage protection to restart the device, which may cause signal interruption, and even burn the front or back chip to cause serious loss.

Disclosure of Invention

In one embodiment, a voltage modulation circuit includes: a charge pump circuit and a voltage detection circuit. The voltage detection circuit is coupled with the charge pump circuit. The charge pump circuit adopts a selected power supply mode of a plurality of power supply modes with different power supply conversion rates to perform power supply operation according to the control signal so as to convert the power supply voltage into at least one output voltage, and outputs a wake-up signal when the selected power supply mode is switched to meet a specific condition. The voltage detection circuit is started by the wake-up signal to detect the output voltage and suspend the power supply operation of the charge pump circuit according to the magnitude of the output voltage.

In one embodiment, a voltage modulation method includes: switching from one of a plurality of power supply modes having different conversion rates to another as a selected power supply mode according to a control signal; a power supply circuit performs a power supply operation in the selected power supply mode so as to convert a power supply voltage into at least one output voltage for supplying power to a post-stage circuit; outputting a wake-up signal when the switching of the selected power supply mode meets a specific condition; starting a detection program of the output voltage according to the wake-up signal; and under the detection program, suspending the power supply operation of the power supply circuit according to the magnitude of the output voltage.

In summary, according to the voltage modulation circuit and the method thereof of any embodiment, when the switching of the selected power supply mode meets a specific condition, the power supply operation of the charge pump circuit is suspended, so that the subsequent circuit pumps current by itself to make the output voltage change slowly. Therefore, the original residual charge can not be recharged to the power supply, and can be effectively utilized without loss, thereby being beneficial to reducing long-time power consumption and eliminating heat accumulation. Moreover, the circuit architecture of the voltage detection circuit used in the method is very easy to implement, the resolution of the voltage detection circuit is not required to be too high, and the required hardware area is very small.

Drawings

Fig. 1 is a schematic diagram of a voltage modulation circuit according to an embodiment.

Fig. 2 is a schematic diagram of a voltage modulation circuit according to another embodiment.

Fig. 3 is a schematic diagram of an exemplary charge pump circuit of fig. 2.

FIG. 4 is a timing diagram of an example of the control signals of FIG. 2 in a selected power mode.

Fig. 5 is a schematic diagram of an exemplary switching circuit of fig. 3.

Fig. 6 is an equivalent circuit diagram of the switching circuit of fig. 3 in the first phase of the first power supply mode.

Fig. 7 is an equivalent circuit diagram of the switching circuit of fig. 3 in the second phase of the first power mode.

Fig. 8 is an equivalent circuit diagram of the switching circuit of fig. 3 in the first phase in the second power supply mode.

Fig. 9 is an equivalent circuit diagram of the switching circuit of fig. 3 in the second phase of the second power supply mode or in the power supply suspended mode.

Fig. 10 is an equivalent circuit diagram of the switching circuit of fig. 3 at the first phase in the third power supply mode.

Fig. 11 is an equivalent circuit diagram of the switching circuit of fig. 3 in the second phase in the third power supply mode.

FIG. 12 is a timing diagram of signals in a selected power mode.

FIG. 13 is a diagram of an exemplary voltage detection circuit of FIG. 2.

FIG. 14 is a diagram of another exemplary voltage detection circuit of FIG. 2.

Detailed Description

As used herein, a "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other or in indirect physical or electrical contact with each other, and the "coupled" or "connected" may also mean that two or more elements are in mutual operation or action. Also, the terms "first," "second," "third," and "fourth" are used herein to distinguish one element from another, to order or define differences between the elements, and not to limit the scope of the invention. As used herein, "a and/or B" refers to any combination of one or more of the listed associated items (A, B) (e.g., A, B or a combination of a and B).

Referring to fig. 1, the voltage modulation circuit 10 includes a charge pump circuit 110 and a voltage detection circuit 130. The charge pump circuit 110 is coupled to the voltage detection circuit 130.

The charge pump circuit 110 has multiple power supply modes with different power supply conversion rates. Here, the charge pump circuit 110 is configured to output a control signal PM < 1: 0> assume a power supply operation with one of such power supply modes (hereinafter referred to as a selected power supply mode) in order to convert the power supply voltage VDD into at least one output voltage Vo for supplying the subsequent stage circuit 20.

When the selected power supply mode is switched to meet a specific condition, the charge pump circuit 110 outputs a wake-up signal (e.g., the control signal EN1 with a high level) to the voltage detection circuit 130 to activate the voltage detection circuit 130.

In other words, the voltage detection circuit 130 is activated by a wake-up signal (e.g., the control signal EN1 with a high level). After the start-up, the voltage detecting circuit 130 receives and detects the output voltage Vo, and suspends the power supply operation of the charge pump circuit 110 according to the magnitude of the output voltage Vo.

In some embodiments, when the power supply operation of the charge pump circuit 110 is suspended (i.e., the charge pump circuit 110 is in the suspended power supply mode), the post-stage circuit 20 will pump a current to the charge pump circuit 110 by itself, so that the output voltage Vo of the charge pump circuit 110 changes slowly. In an exemplary embodiment, for example, the later-stage circuit 20 is an audio amplifier circuit, the audio amplifier circuit self-pumps current to the charge pump circuit 110 in the power-suspended mode, so that in addition to slowly changing the output voltage Vo of the charge pump circuit 110, the audio amplifier circuit driven by the charge pump circuit 110 is not prone to generate Pop Noise (Pop Noise).

In some embodiments, the charge pump circuit 110 can design the number of output voltages Vo output by the charge pump circuit according to the number of power supplies required by the subsequent stage circuit 20. In an exemplary embodiment, the charge pump circuit 110 can provide a single output voltage Vo (e.g., a single positive output voltage) to the subsequent circuit 20. In some examples, the charge pump circuit 110 can also provide two output voltages Vo (e.g., a positive output voltage VPP and a negative output voltage VEE, or two positive output voltages) to the post-stage circuit 20. In some examples, the charge pump circuit 110 may also provide three or more output voltages Vo to the subsequent circuit 20.

In some embodiments, referring to fig. 1 or 2, the control signal PM < 1: 0> may be generated by the control circuit 40 according to the amplitude of the signal (e.g., the input signal Si or the output signal So) of the subsequent stage circuit 20. In other words, the control circuit 40 determines the power supply mode to be executed by the charge pump circuit 110 according to the amplitude of the signal of the post-stage circuit 20 (i.e. generates the corresponding control signals PM < 1: 0 >). Since the structure and operation principle of the control circuit 40 are well known to those skilled in the art, they are not described herein again.

In an example, referring to fig. 1 or fig. 2, the post-stage circuit 20 is an amplifier circuit (e.g., an audio amplifier circuit), and the charge pump circuit 110 supplies power to the amplifier circuit so as to operate the amplifier circuit. In operation, the amplifier circuit generates an output signal So to drive a load 30 (e.g., a speaker or a headphone) according to the input signal Si. For example, the amplifier circuit may include an amplifier AMP. The power source terminal of the amplifier AMP is coupled to the output terminal of the charge pump circuit 110, and the output voltage Vo (or the positive output voltage VPP and the negative output voltage VEE) provided by the output terminal of the charge pump circuit 110 supplies the power required for operation. The amplifier AMP amplifies the input signal Si into an output signal So and supplies to the load 30, with power supplied from the charge pump circuit 110.

Referring to fig. 1 or 2, the control circuit 40 is coupled to the input or the output of the amplifier circuit. In operation, the control circuit 40 detects the input signal Si or the output signal So of the amplifier circuit and generates the control signal PM < 1: 0 >. It should be understood that although fig. 1 illustrates the generation of the control signal PM <1 from the input signal Si: 0>, or generate the control signal PM < 1: 0 >.

The charge pump circuit 110 provides two output voltages (i.e., the positive output voltage VPP and the negative output voltage VEE) as an example.

In some embodiments, referring to fig. 2, the charge pump circuit 110 may have three power supply modes with different conversion rates. In the three power supply modes, the output voltage (i.e., the voltage difference between the positive output voltage VPP and the negative output voltage VEE) outputted by the charge pump circuit 110 is three different multiplying factors of the power supply voltage VDD. For example, the three power modes are referred to as a high power mode, a medium power mode and a low power mode. In the high power mode, the charge pump circuit 110 generates a positive output voltage VPP of + VDD and a negative output voltage VEE of-VDD. In the mid-power mode, the charge pump circuit 110 generates a positive output voltage VPP of + VDD/2 and a negative output voltage VEE of-VDD/2. In the low power mode, the charge pump circuit 110 generates a positive output voltage VPP of + VDD/3 and a negative output voltage VEE of-VDD/3. Therefore, the control circuit 40 can generate the control signal PM <1 according to the required power of the post-stage circuit 20 (the signal range value of the input signal Si or the output signal So within a preset time period): 0> to control the power mode employed by the charge pump circuit 110.

In some embodiments, the control signal PM < 1: 0> may be a digital signal. For example, PM < 1: 0> -00 for low supply mode, PM < 1: 0> -01 represents medium supply mode, and PM < 1: 0> -10 or 11 represents the high power mode. In other words, the charge pump circuit 110 responds to the control signal PM < 1: 0> power supply operation is performed in the low power supply mode. The charge pump circuit 110 responds to the control signal PM < 1: and 0> adopting a middle power supply mode for power supply operation. The charge pump circuit 110 responds to a control signal PM < 1: 0> power supply operation is performed in the high power supply mode.

In some embodiments, the particular condition is that the selected power mode is switched from one of the plurality of power modes to another. In an example, the specific condition may be that the selected power supply mode is switched from a power supply mode with a large power conversion rate to a power supply mode with a small power conversion rate. In another example, the specific condition may be that the selected power supply mode is switched from a specific one of the power supply modes to a specific other one of the power supply modes. For example, in the above example, the charge pump circuit 110 may have a high power mode, a medium power mode, and a low power mode with different and sequentially decreasing power conversion rates. Here, the specific condition may be that the selected power supply mode is switched from the high power supply mode to the medium power supply mode.

In some embodiments, referring to fig. 2 and 3, the charge pump circuit 110 includes a mode control circuit 111 and a power supply circuit, and the power supply circuit includes a first energy storage capacitor Cp1, a second energy storage capacitor Cp2, a first flying capacitor Cf1, a second flying capacitor Cf2, and a switch circuit 113. The mode control circuit 111 is coupled to a control terminal of the switch circuit 113. The first energy storage capacitor Cp1 is coupled between the positive output terminal of the switch circuit 113 (i.e., the positive output voltage VPP output) and the ground GND. The second energy-storage capacitor Cp2 is coupled between the negative output terminal of the switch circuit 113 (i.e., it outputs the negative output voltage VEE) and the ground GND. First and second flying capacitors Cf1 and Cf2 are connected across the switching circuit 113. Also, the switch circuit 113 is also coupled between the power supply voltage VDD and the ground GND.

Here, the mode control circuit 111 controls the operation of the shift register according to the control signal PM < 1: 0> generates a plurality of switching signals Sc1 to Sc11 corresponding to the selected power supply mode, and outputs a wake-up signal to the voltage detection circuit 130 when the switching of the selected power supply mode meets a certain condition. The switch circuit 113 controls the electrical connection relationship among the power voltage VDD, the first storage capacitor Cp1, the second storage capacitor Cp2, the first flying capacitor Cf1, the second flying capacitor Cf2 and the ground GND according to the switching signals Sc1 to Sc11 to output the positive output voltage VPP and the negative output voltage VEE corresponding to the selected power supply mode.

In some embodiments, the mode control circuit 111 may include a frequency generation circuit (not shown) that generates the first frequency CK1 and the second frequency CK2 by non-overlapping modulation (non-overlapping modulation) and provides the first phase PH1 and the second phase PH2, as shown in fig. 4. Here, the first phase PH1 of the first clock CK1 does not overlap the second phase PH2 of the second clock CK 2. The implementation structure and operation principle of the frequency generation circuit are well known to those skilled in the art, and therefore are not described herein again.

In addition, the mode control circuit 111 may further include a signal output circuit (not shown), and the signal output circuit outputs a signal according to the control signal PM < 1: 0> the first clock CK1 and the second clock CK2 are adjusted to control the switch circuit 113. In other words, the signal output circuit outputs a signal according to the control signal PM < 1: 0> the plurality of switching signals Sc1 to Sc11 corresponding to the selected power supply mode are generated by using the first clock CK1 and the second clock CK 2. The signal output circuit can be implemented by one or more multiplexers.

In some embodiments, referring to fig. 2-5, the switching circuit 113 includes a plurality of switches (e.g., Sw 1-Sw 11 in the figures). The switches Sw1 to Sw11 are connected between any two of the power supply voltage VDD, the ground GND, the positive output terminal N1, the negative output terminal N2, the positive electrode of the first flying capacitor Cf1, the negative electrode of the first flying capacitor Cf1, the positive electrode of the second flying capacitor Cf2, and the negative electrode of the second flying capacitor Cf 2. The positive output terminal N1 and the negative output terminal N2 are externally coupled to the post-stage circuit 20. Herein, the mode control circuit 111 is coupled to the control terminals of the switches Sw1 to Sw11, so that the switch signals Sc1 to Sc11 outputted by the mode control circuit 111 are respectively used to control the switches Sw1 to Sw 11.

In the low power supply mode, the mode control circuit 111 takes the first frequency CK1 as the switching signals Sc1, Sc3, Sc4, Sc8 and inputs the switching signals to the control terminals of the switches Sw1, Sw3, Sw4, Sw8, respectively. The mode control circuit 111 receives the second frequency CK2 as switching signals Sc2, Sc5, Sc6, and Sc7, and inputs the switching signals to control terminals of the switches Sw2, Sw5, Sw6, and Sw7, respectively. The control terminals of the switches Sw9, Sw10 and Sw11 do not receive any control signal, so that the switches Sw9, Sw10 and Sw11 are kept disconnected in the first phase PH1 and the second phase PH 2. That is, in the low power supply mode, the switches Sw1 to Sw8 operate, and the switches Sw9 to Sw11 do not operate.

Therefore, in the first phase PH1, the switches Sw1, Sw3, Sw4 and Sw8 are turned on in response to the first frequency CK1, and the switches Sw2, Sw5, Sw6 and Sw7 are turned off according to the second frequency CK2, as shown in fig. 6. In the second phase PH2, the switches Sw1, Sw3, Sw4 and Sw8 are turned off according to the first frequency CK1, and the switches Sw2, Sw5, Sw6 and Sw7 are turned on in response to the operation pulse of the second frequency CK2, as shown in fig. 7. At this time, the positive output voltage VPP outputted from the positive electric output terminal N1 is (1/3) the power voltage VDD, i.e., -VDD/3, and the negative output voltage VEE outputted from the negative electric output terminal N2 is (-1/3) the power voltage VDD, i.e., -VDD/3.

In the medium power supply mode, the mode control circuit 111 takes the first frequency CK1 as the switching signals Sc1, Sc3, Sc4, Sc8 and inputs the switching signals to the control terminals of the switches Sw1, Sw3, Sw4, Sw 8. The mode control circuit 111 inputs the second frequency CK2 as switching signals Sc5, Sc6, Sc7, and Sc9 to control terminals of the switches Sw5, Sw6, Sw7, and Sw 9. The control terminals of the switches Sw2, Sw10 and Sw11 do not receive any control signal, so that the switches Sw2, Sw10 and Sw11 are kept disconnected in the first phase PH1 and the second phase PH 2. That is, in the medium power supply mode, the switches Sw1, Sw3 to Sw9 operate, while the switches Sw2, Sw10, Sw11 do not operate.

Therefore, in the first phase PH1, the switches Sw1, Sw3, Sw4 and Sw8 are turned on in response to the working pulse of the first frequency CK1, and the switches Sw5, Sw6, Sw7 and Sw9 are turned off according to the second frequency CK2, as shown in fig. 8. In the second phase PH2, the switches Sw1, Sw3, Sw4 and Sw8 are turned off according to the first frequency CK1, and the switches Sw5, Sw6, Sw7 and Sw9 are turned on in response to the operation pulse of the second frequency CK2, as shown in fig. 9. At this time, the positive output voltage VPP outputted from the positive electric output terminal N1 is (1/2) the power voltage VDD, i.e., -VDD/2, and the negative output voltage VEE outputted from the negative electric output terminal N2 is (-1/2) the power voltage VDD, i.e., -VDD/2.

In the high power supply mode, the mode control circuit 111 takes the first frequency CK1 as the switching signals Sc1, Sc3, Sc8, Sc10, Sc11 and inputs the switching signals to the control terminals of the switches Sw1, Sw3, Sw8, Sw10, Sw11, respectively. The mode control circuit 111 inputs the second frequency CK2 as the switching signals Sc5, Sc6, Sc7, Sc9, and Sc10 to the control terminals of the switches Sw5, Sw6, Sw7, Sw9, and Sw 10. The control terminals of the switches Sw2 and Sw4 do not receive any control signal, so that the switches Sw2 and Sw4 are kept open in the first phase PH1 and the second phase PH 2. That is, in the high power supply mode, the switches Sw1, Sw3, Sw5 to Sw11 operate, while the switches Sw2, Sw4 do not operate.

Therefore, in the first phase PH1, the switches Sw1, Sw3, Sw8, Sw10 and Sw11 are turned on in response to the working pulse of the first frequency CK1, and the switches Sw5, Sw6, Sw7, Sw9 and Sw10 are turned off according to the second frequency CK2, as shown in fig. 10. In the second phase PH2, the switches Sw1, Sw3, Sw8, Sw10 and Sw11 are turned off according to the first frequency CK1, and the switches Sw5, Sw6, Sw7, Sw9 and Sw10 are turned on in response to the operation pulse of the second frequency CK2, as shown in fig. 11. At this time, the positive output voltage VPP outputted from the positive electric output terminal N1 is (1) the power supply voltage VDD, i.e., VDD, and the negative output voltage VEE outputted from the negative electric output terminal N2 is (-1) the power supply voltage VDD, i.e., -VDD.

In other words, in any power supply mode, the switch circuit 113 alternately switches between the charging connection (i.e., in the first phase PH1) and the discharging connection (i.e., in the second phase PH 2).

Here, with the control signal PM < 1: 0> is a 2-bit digital signal (i.e., PM <1> and PM <0> in FIG. 12) and the particular condition is that the selected power mode is switched from the high power mode to the medium power mode. Wherein PM < 1: 0> -00 for low supply mode, PM < 1: 0> -01 represents medium supply mode, and PM < 1: 0> -10 or 11 represents the high power mode. Referring to fig. 2, 3, 5, and 12, when the mode control circuit 111 is in response to the control signal PM < 1: when the selected power supply mode is switched from the high power supply mode to the medium power supply mode (i.e., the selected power supply mode is switched to satisfy a specific condition) when the "0" is changed from "11" to "01", the mode control circuit 111 pulls the control signal EN1 output to the voltage detection circuit 130 from the low level to the high level (i.e., the wake-up signal). The voltage detection circuit 130 is awakened by the high-level control signal EN1 and starts detecting the positive output voltage VPP and the negative output voltage VEE. When the absolute value of either the positive output voltage VPP or the negative output voltage VEE exceeds a specific threshold (or the absolute values of both the positive output voltage VPP and the negative output voltage VEE exceed a specific threshold), the voltage detection circuit 130 outputs a disable signal (e.g., a low-level control signal EN2) to the charge pump circuit 110. In other words, the voltage detection circuit 130 normally outputs the control signal EN2 with the high level to the charge pump circuit 110. When detecting that the absolute value of the positive output voltage VPP and/or the negative output voltage VEE exceeds a specific threshold, the voltage detection circuit 130 pulls down the control signal EN2 output to the charge pump circuit 110 from the high level to the low level (i.e., a disable signal). The mode control circuit 111 receives the low level control signal EN2 and suspends the power supply operation of the power supply circuit in response to the low level control signal EN2, i.e., stops the switching of the switching circuit 113 alternately between the first phase PH1 and the second phase PH 2. The switch circuit 113 exhibits a specific connection relationship when the charge pump circuit 110 suspends the power supply operation. Until the voltage detection circuit 130 detects that the absolute values of the positive output voltage VPP and the negative output voltage VEE do not exceed the specific threshold (or detects that the absolute value of any one of the positive output voltage VPP and the negative output voltage VEE does not exceed the specific threshold), the voltage detection circuit 130 further pulls the control signal EN2 output to the charge pump circuit 110 from the low level to the high level (i.e., does not output the disable signal), so that the charge pump circuit 110 resumes the power supply operation in the medium power supply mode (i.e., the selected power supply mode) in response to the control signal EN2 at the high level (i.e., the mode control circuit 111 resumes outputting the switching signals Sc1, Sc3, Sc4, Sc5, Sc6, Sc7, Sc8, and Sc9 corresponding to the medium power supply mode in response to the control signal EN2 at the high level).

In some embodiments, a particular connection relationship may be that the switch circuit 113 remains off the supply voltage VDD.

In some embodiments, the specific connection relationship may be that the switch circuit 113 maintains the off-power voltage VDD and the switch circuit 113 maintains the first energy-storing capacitor Cp1, the second energy-storing capacitor Cp2, the first flying capacitor Cf1 and the second flying capacitor Cf2 electrically connected to the rear stage circuit 20.

In some embodiments, the particular connection relationship may correspond to the switch circuit 113 being maintained under control of the second phase PH2 corresponding to the selected power mode. For example, as mentioned above, in the power-supply suspension mode, the mode control circuit 111 outputs the switching signals Sc5, Sc6, Sc7, Sc9 maintained at high level to the control terminals of the switches Sw5, Sw6, Sw7, and Sw 9. The control terminals of the switches Sw1, Sw2, Sw3, Sw4, Sw8, Sw10 and Sw11 do not receive any control signal or receive the switching signals Sc1, Sc2, Sc3, Sc4, Sc8, Sc10 and Sc11 which are output by the mode control circuit 111 and are maintained at a low level. Thus, the switches Sw1, Sw2, Sw3, Sw4, Sw8, Sw10 and Sw11 remain open, while the switches Sw5, Sw6, Sw7 and Sw9 remain open, as shown in fig. 9. In other words, the switch circuit 113 maintains the switch state during the second phase PH2 of the middle power mode, i.e., the first energy-storing capacitor Cp1 is coupled between the positive output terminal N1 and the ground GND, and the second energy-storing capacitor Cp2, the first flying capacitor Cf1 and the second flying capacitor Cf2 are respectively coupled between the negative output terminal N2 and the ground GND. At this time, the subsequent circuit 20 pumps current through the positive output terminal N1 and the negative output terminal N2, that is, the charges on all the capacitors (i.e., the first storage capacitor Cp1, the second storage capacitor Cp2, the first flying capacitor Cf1 and the second flying capacitor Cf2) of the charge pump circuit 110 are sequentially provided to the subsequent circuit 20 along with the time increase, so that the potential of the positive output voltage VPP continuously decreases due to the subsequent circuit 20 and the potential of the negative output voltage VEE continuously increases due to the subsequent circuit 20, as shown in fig. 12.

In one embodiment, referring to fig. 13, the voltage detection circuit 130 includes: a plurality of switches (exemplified by the first switch Sw12 and the second switch Sw 14), a plurality of voltage dividing circuits (exemplified by the first voltage dividing circuit 131 and the second voltage dividing circuit 132), a plurality of comparators (exemplified by the first comparator 133 and the second comparator 134), and a logic circuit 135. The first switch Sw12 is coupled between the first terminal of the first voltage divider circuit 131 and the positive output voltage VPP of the charge pump circuit 110. The second switch Sw14 is coupled between the first terminal of the second voltage divider 132 and the negative output voltage VEE of the charge pump circuit 110. The negative input terminal of the first comparator 133 is coupled to the voltage dividing point of the first voltage dividing circuit 131, and the positive input terminal of the first comparator 133 is coupled to the first reference voltage Vth _ p. The positive input terminal of the second comparator 134 is coupled to the voltage dividing point of the second voltage dividing circuit 132, and the negative input terminal of the second comparator 134 is coupled to the second reference voltage Vth _ n. The output of the first comparator 133 and the output of the second comparator 134 are coupled to the logic circuit 135.

The first switch Sw12 and the second switch Sw14 are normally closed. The control terminals of the first switch Sw12 and the second switch Sw14 receive the wake-up signal (e.g., the control signal EN1 with high level), so that the first switch Sw12 and the second switch Sw14 are turned on in response to the wake-up signal (e.g., the control signal EN1 with high level).

When the first switch Sw12 is turned on, the first voltage division circuit 131 receives the positive output voltage VPP via the first switch Sw12 and generates a first divided voltage Vd1 using the positive output voltage VPP. In other words, the first divided voltage Vd1 is related to the positive output voltage VPP. In an exemplary embodiment, the positive output voltage VPP is proportional to the first divided voltage Vd 1. For example, the positive output voltage VPP is a first particular multiple of the first division voltage Vd 1.

The first comparator 133 compares the first division voltage Vd1 with the first reference voltage Vth _ p to generate a first comparison result.

When the second switch Sw14 is turned on, the second voltage division circuit 132 receives the negative output voltage VEE via the second switch Sw14 and generates a second divided voltage Vd2 using the negative output voltage VEE. In other words, the second division voltage Vd2 is related to the negative output voltage VEE. In an exemplary embodiment, the negative output voltage VEE is in a positive proportion to the second divided voltage Vd 2. For example, the negative output voltage VEE is a second specific multiple of the second divided voltage Vd 2.

The second comparator 134 compares the second divided voltage Vd2 with the second reference voltage Vth _ n to generate a second comparison result.

The logic circuit 135 controls the charge pump circuit 110 to temporarily supply power in a specific power supply mode according to the first comparison result and the second comparison result.

In some embodiments, the ideal value of the positive output voltage VPP is a first specific multiple of the absolute value of the first reference voltage Vth _ p. The ideal value of the negative output voltage VEE is a second specific multiple of the absolute value of the second reference voltage Vth _ n. In an exemplary embodiment, the first reference voltage Vth _ p and the second reference voltage Vth _ n may be the same value. In another example, the first reference voltage Vth _ p and the second reference voltage Vth _ n may be different values.

In some embodiments, the second terminal of the first voltage divider circuit 131 may be coupled to the ground GND via the third switch Sw 13. The third switch Sw13 is also normally off. When the voltage detection circuit 130 receives the wake-up signal (e.g., the control signal EN1 with high level), the first switch Sw12 and the third switch Sw13 are turned on in response to the wake-up signal (e.g., the control signal EN1 with high level), so that the first voltage divider circuit 131 divides the first divided voltage Vd1 between the positive output voltage VPP and 0V (i.e., the voltage of the ground GND). Similarly, the second terminal of the second voltage divider 132 may be coupled to the power voltage VDD via the fourth switch Sw 15. The fourth switch Sw15 is also normally off. When the voltage detection circuit 130 receives the wake-up signal (e.g., the high-level control signal EN1), the second switch Sw14 and the fourth switch Sw15 are turned on in response to the wake-up signal (e.g., the high-level control signal EN1), so that the second voltage division circuit 132 divides the second divided voltage Vd2 between the power voltage VDD and the negative output voltage VEE.

In some embodiments, a first Debounce (Debounce) circuit 136 may be coupled between the first comparator 133 and the logic circuit 135. Therefore, the first comparison result generated by the first comparator 133 is processed by the first de-bounce circuit 136 (i.e., the processed signal CMP _ PO) and then input to the logic circuit 135. Similarly, a second debounce circuit 137 may be coupled between the second comparator 134 and the logic circuit 135. Therefore, the first comparison result generated by the second comparator 134 is processed by the second debounce circuit 137 (i.e., the processed signal CMP _ NO) and then input to the logic circuit 135. Here, the control signal PM < 1: FIG. 12 shows timing diagrams of 0>, the control signal EN1, the positive output voltage VPP, the negative output voltage VEE, the signal CMP _ PO, the signal CMP _ NO, and the control signal EN 2.

In an example, referring to fig. 12 and 13, the logic circuit 135 may be an or gate. When the first division voltage Vd1 is higher than the first reference voltage Vth _ p, the first comparison result output by the first comparator 133 is at a low level (i.e., the signal CMP _ PO is at a low level); when the second divided voltage Vd2 is lower than the second reference voltage Vth _ n, the second comparison result output by the second comparator 134 is low (i.e., the signal CMP _ NO is low). At this time, the or gate 135 outputs a disable signal (e.g., outputs the low-level control signal EN2) in response to the low-level signal CMP _ PO and the low-level signal CMP _ NO to suspend the power-up operation of the charge pump circuit 110. When the first reference voltage Vth _ p is higher than the first division voltage Vd1, the first comparison result output by the first comparator 133 is at a high level (i.e., the signal CMP _ PO is at a high level); when the second division voltage Vd2 is higher than the second reference voltage Vth _ n, the second comparison result output by the second comparator 134 is at a high level (i.e., the signal CMP _ NO is at a high level). Herein, the or gate (135) stops outputting the disable signal in response to the high-level signal CMP _ PO or the high-level signal CMP _ NO (e.g., the low-level control signal EN2 is not outputted, and the high-level control signal EN2 is outputted instead); at this time, the charge pump circuit 110 resumes being powered in the selected power mode. In other words, the operation of the voltage detection circuit 130 is equivalent to detecting whether the absolute value of the positive output voltage VPP and the absolute value of the negative output voltage VEE both exceed a certain threshold. When both are exceeded, the voltage detection circuit 130 outputs a disable signal to the charge pump circuit 110. On the contrary, if either of the voltages is not exceeded, the voltage detection circuit 130 does not output the disable signal to the charge pump circuit 110.

In another example, the logic circuit 135 may be an and gate. When the first division voltage Vd1 is higher than the first reference voltage Vth _ p (i.e., the first comparison result output by the first comparator 133 is at a low level) or the second division voltage Vd2 is lower than the second reference voltage Vth _ n (i.e., the second comparison result output by the second comparator 134 is at a low level), the and gate (135) outputs a disable signal (e.g., outputs the low-level control signal EN2) to suspend the power supply operation of the charge pump circuit 110. When the first divided voltage Vd1 is lower than the first reference voltage Vth _ p (i.e., the first comparison result output by the first comparator 133 is at a high level) and the second divided voltage Vd2 is higher than the second reference voltage Vth _ n (i.e., the second comparison result output by the second comparator 134 is at a high level), the and gate (135) stops outputting the disable signal (e.g., the control signal EN2 at a high level is output instead of outputting the control signal EN2 at a low level); at this time, the charge pump circuit 110 resumes the power supply operation in the selected power supply mode. In other words, the operation of the voltage detection circuit 130 is equivalent to detecting whether the absolute value of at least one of the positive output voltage VPP and the negative output voltage VEE exceeds a specific threshold. When the absolute value of at least one of the signals exceeds, the voltage detection circuit 130 outputs a disable signal to the charge pump circuit 110. Otherwise, if none of the signals exceeds the threshold, the voltage detection circuit 130 does not output the disable signal to the charge pump circuit 110.

In some embodiments, the first voltage divider circuit 131 may be implemented by a serial circuit of a plurality of resistors R12, R13. Here, the junction between the resistors R12 and R13 is the voltage dividing point of the first voltage dividing circuit 131. Similarly, the second voltage divider 132 may be implemented by a serial circuit of a plurality of resistors R14 and R15. Here, the junction between the resistors R14 and R15 is the voltage dividing point of the second voltage dividing circuit 132. In some embodiments, the resistors R12, R13, R14 and R15 may be fixed-value resistors or variable-value resistors. The voltage detection circuit 130 can adjust the detection sensitivity by adjusting the resistances of the resistors R12, R13, R14, and R15.

In another embodiment, referring to fig. 14, the voltage detection circuit 130 includes: a plurality of switches (exemplified by the first switch Sw16 and the second switch Sw 18), a plurality of voltage dividing circuits (exemplified by the first voltage dividing circuit 141 and the second voltage dividing circuit 142), a plurality of analog-to-digital converters (exemplified by the first analog-to-digital converter 143 and the second analog-to-digital converter 144), and a digital circuit 145. The first switch Sw16 is coupled between the first terminal of the first voltage divider 141 and the positive output voltage VPP of the charge pump circuit 110. The second switch Sw18 is coupled between the first terminal of the second voltage divider 142 and the negative output voltage VEE of the charge pump circuit 110. A first input terminal of the first adc 143 is coupled to the voltage dividing point of the first voltage dividing circuit 141, and a second input terminal of the first adc 143 is coupled to the first reference voltage Vth _ p. A first input terminal of the second adc 144 is coupled to the voltage dividing point of the second voltage dividing circuit 142, and a second input terminal of the second adc 144 is coupled to the second reference voltage Vth _ n. The output terminal of the first adc 143 and the output terminal of the second adc 144 are coupled to the digital circuit 145.

The first switch Sw16 and the second switch Sw18 are normally closed. The control terminals of the first switch Sw16 and the second switch Sw18 receive the wake-up signal (e.g., the control signal EN1 with high level), so that the first switch Sw16 and the second switch Sw18 are turned on in response to the wake-up signal (e.g., the control signal EN1 with high level).

When the first switch Sw16 is turned on, the first voltage division circuit 141 receives the positive output voltage VPP via the first switch Sw16 and generates the first divided voltage Vd3 using the positive output voltage VPP. In other words, the first divided voltage Vd3 is related to the positive output voltage VPP. In an exemplary embodiment, the positive output voltage VPP is proportional to the first divided voltage Vd 3. For example, the positive output voltage VPP is a third particular multiple of the first division voltage Vd 3.

The first analog-to-digital converter 143 generates a first digital signal SAR _ PO corresponding to the positive output voltage VPP according to the first division voltage Vd3 and the first reference voltage Vth _ p. In one embodiment, the first ADC 143 may be implemented as a progressive-Analog-to-Digital Converter (SAR ADC). Herein, the first adc 143 compares the first divided voltage Vd3 sampled with the initial first reference voltage Vth _ p with reference to a high-speed frequency, and corrects the first reference voltage Vth _ p according to the comparison result, so that the first reference voltage Vth _ p gradually approaches the first divided voltage Vd3, and further the value of the first divided voltage Vd3 can be detected in a short time and converted into a digital code (i.e., the first digital signal SAR _ PO).

When the second switch Sw18 is turned on, the second voltage division circuit 142 receives the negative output voltage VEE via the second switch Sw18 and generates a second divided voltage Vd4 using the negative output voltage VEE. In other words, the second division voltage Vd4 is related to the negative output voltage VEE. In an exemplary embodiment, the negative output voltage VEE is in a positive proportion to the second divided voltage Vd 4. For example, the negative output voltage VEE is a fourth specific multiple of the second divided voltage Vd 4.

The second adc 144 generates a second digital signal SAR _ NO corresponding to the negative output voltage VEE according to the second divided voltage Vd4 and the second reference voltage Vth _ n. In one embodiment, the second adc 144 can also be implemented as a progressive adc. Herein, the second adc 144 compares the sampled second divided voltage Vd4 with the initial second reference voltage Vth _ n with reference to a high-speed frequency, and corrects the second reference voltage Vth _ n according to the comparison result, so that the second reference voltage Vth _ n gradually approaches the second divided voltage Vd4, and further the value of the second divided voltage Vd4 can be detected in a short time and converted into digital code (i.e., the second digital signal SAR _ NO).

The digital circuit 145 controls the charge pump circuit 110 to temporarily supply power in a specific power supply mode according to the first digital signal SAR _ PO and the second digital signal SAR _ NO. In other words, the digital circuit 145 determines whether to restart the charge pump circuit 110 according to whether the first digital signal SAR _ PO and the second digital signal SAR _ NO reach the predetermined code. For example, when the first digital signal SAR _ PO and/or the second digital signal SAR _ NO exceeds the predetermined code, the digital circuit 145 outputs a disable signal (e.g., the low-level control signal EN2) to the charge pump circuit 110. When the charge pump circuit 110 is suspended from the selected power supply mode in response to (e.g., the low-level control signal EN2), the subsequent circuit (e.g., the amplifier circuit 20) of the charge pump circuit 110 can pump current to make the positive output voltage VPP and the negative output voltage VEE change slowly. On the contrary, when both the first digital signal SAR _ PO and the second digital signal SAR _ NO meet or do not exceed the predetermined code, the voltage detection circuit 130 does not output the disable signal (e.g., does not output the low-level control signal EN2 but instead outputs the high-level control signal EN2) to the charge pump circuit 110.

In other words, the operation of the voltage detection circuit 130 is equivalent to detecting whether the absolute value of either of the positive output voltage VPP and the negative output voltage VEE has exceeded a certain threshold (corresponding to a given code).

In some embodiments, the second terminal of the first voltage divider circuit 141 may be coupled to the ground GND via the third switch Sw 17. The third switch Sw17 is also normally off. When the voltage detection circuit 130 receives the wake-up signal (e.g., the control signal EN1 with high level), the first switch Sw16 and the third switch Sw17 are turned on in response to the wake-up signal (e.g., the control signal EN1 with high level), so that the first voltage divider circuit 141 divides the first divided voltage Vd3 between the positive output voltage VPP and 0V (i.e., the voltage of the ground GND). Similarly, the second terminal of the second voltage divider 142 may be coupled to the power voltage VDD via the fourth switch Sw 19. The fourth switch Sw19 is also normally off. When the voltage detection circuit 130 receives the wake-up signal (e.g., the high-level control signal EN1), the second switch Sw18 and the fourth switch Sw19 are turned on in response to the wake-up signal (e.g., the high-level control signal EN1), so that the second voltage division circuit 142 divides the second divided voltage Vd4 between the power voltage VDD and the negative output voltage VEE.

In some embodiments, the first voltage divider circuit 141 may be implemented by a serial circuit of a plurality of resistors R16, R17. Here, the junction between the resistors R16 and R17 is the voltage dividing point of the first voltage dividing circuit 141. Similarly, the second voltage divider 142 may be implemented by a serial circuit of a plurality of resistors R18 and R19. Here, the junction between the resistors R18 and R19 is the voltage dividing point of the second voltage dividing circuit 142. In some embodiments, the resistors R16, R17, R18 and R19 may be fixed-value resistors or variable-value resistors. The voltage detection circuit 130 can adjust the detection sensitivity by adjusting the resistances of the resistors R16, R17, R18, and R19.

In some embodiments, the voltage detection circuit 130 switches from the on state to the off state when the charge pump circuit 110 resumes the power supply operation in the selected power supply mode from the suspend power supply mode. For example, when the charge pump circuit 110 resumes the power supply suspended mode to the power supply operation in the selected power supply mode, the mode control circuit 111 stops outputting the wake-up signal (e.g., does not output the control signal EN1 with high level but instead outputs the control signal EN1 with low level) to the voltage detection circuit 130, so that the voltage detection circuit 130 returns to the off state. In other words, the voltage detection circuit 130 is only in the active state during the switching period of the selected power supply mode (i.e. in the power supply suspension mode), and is in the off state in the steady state, so as to reduce the extra power consumption. For example, normally (i.e., in the selected power mode), the voltage detection circuit 130 turns off all internal voltage detection components, such as all input stage switches (e.g., Sw12 to Sw14 or Sw16 to Sw19) and disables all working components (e.g., stops supplying power to 133 to 137 or 143 to 145), and maintains the output of the voltage detection circuit 130 (i.e., the control signal EN2) at a high level (e.g., only turns on the output stage switch (not shown) to turn on the output terminal of the voltage detection circuit 130 to the power voltage VDD). In the power-down mode, the voltage detection circuit 130 is driven to switch to the active state, i.e., all internal voltage detection components are turned on, e.g., all input stage switches are turned on and all active components are enabled, and the level of the control signal EN2 is determined by the operation of the output stage (e.g., the logic circuit 135 or the digital circuit 145) (e.g., the output stage switch coupled between the output terminal of the voltage detection circuit 130 and the power supply voltage VDD is turned off).

In summary, according to any embodiment of the voltage modulation circuit and the method thereof, when the switching of the selected power supply mode meets a specific condition, the charge pump circuit 110 is turned off temporarily (i.e., the selected power supply mode is changed to the specific power supply mode), so that the subsequent load (e.g., the amplifier circuit 20) draws current by itself to make the output voltage change slowly. Therefore, the original residual charge can not be recharged to the power supply, and can be effectively utilized without loss, thereby being beneficial to reducing long-time power consumption and eliminating heat accumulation. Moreover, the circuit architecture of the voltage detection circuit 130 used herein is very easy to implement, the resolution thereof does not need to be too high, and the required hardware area is very small. In some embodiments, the voltage detection circuit 130 is normally off, and is only activated when the selected power mode is switched to meet a specific condition, so that no additional power consumption is caused. In some embodiments, Pop Noise (Pop Noise) may also be avoided from being generated by an audio effect load 30 (e.g., a speaker or headphones) driven by the amplifier circuit 20.

Claims

1. A voltage modulation circuit, comprising:

a charge pump circuit, which performs a power supply operation in a selected power supply mode of a plurality of power supply modes having different power conversion rates according to a control signal, so as to convert a power supply voltage into at least one output voltage, and outputs a wake-up signal when the selected power supply mode is switched to meet a specific condition; and

a voltage detection circuit, coupled to the charge pump circuit, activated by the wake-up signal to detect the at least one output voltage, and suspending the power supply operation of the charge pump circuit according to a magnitude of the at least one output voltage.

2. The voltage modulation circuit according to claim 1, wherein a current is pumped from a post-stage circuit to the charge pump circuit while the charge pump circuit suspends the power supply operation.

3. The voltage modulation circuit according to claim 1, wherein the at least one output voltage includes a positive output voltage and a negative output voltage, and the voltage detection circuit includes:

a first switch, normally closed, responsive to the wake-up signal to conduct;

a first voltage divider circuit for receiving the positive output voltage via the first switch and generating a first divided voltage by using the positive output voltage;

a first comparator for comparing the first divided voltage with a first reference voltage to generate a first comparison result;

a second switch, normally closed, responsive to the wake-up signal to conduct;

a second voltage dividing circuit, receiving the negative output voltage through the second switch and generating a second divided voltage by using the negative output voltage;

a second comparator for comparing the second divided voltage with a second reference voltage to generate a second comparison result; and

a logic circuit for suspending the power supply operation of the charge pump circuit according to the first comparison result and the second comparison result.

4. The voltage modulation circuit of claim 3, wherein the logic circuit outputs a disable signal to enable the charge pump circuit to suspend the power supply operation when the first divided voltage is not lower than the first reference voltage and the second divided voltage is lower than the second reference voltage, and stops outputting the disable signal to enable the charge pump circuit to resume the power supply operation when the first divided voltage is lower than the first reference voltage or the second divided voltage is not lower than the second reference voltage, wherein the logic circuit is an OR gate.

5. The voltage modulation circuit of claim 3, wherein the logic circuit outputs a disable signal to enable the charge pump circuit to suspend the power supply operation when the first divided voltage is not lower than the first reference voltage or the second divided voltage is lower than the second reference voltage, and stops outputting the disable signal to enable the charge pump circuit to resume the power supply operation when the first divided voltage is lower than the first reference voltage and the second divided voltage is not lower than the second reference voltage, wherein the logic circuit is an AND gate.

6. The voltage modulation circuit according to claim 3, wherein the voltage detection circuit further comprises:

a first debounce circuit coupled between the first comparator and the logic circuit; and

a second debounce circuit coupled between the second comparator and the logic circuit.

7. The voltage modulation circuit of claim 1, wherein the at least one output voltage comprises a positive output voltage and a negative output voltage, the voltage detection circuit comprising:

a first switch, normally closed, responsive to the wake-up signal to conduct;

a first analog-to-digital converter for generating a first digital signal corresponding to the positive output voltage according to the first divided voltage and a first reference voltage;

a second switch, normally closed, responsive to the wake-up signal to conduct;

a second analog-to-digital converter for generating a second digital signal corresponding to the negative output voltage according to the second divided voltage and a second reference voltage; and

a digital circuit for suspending the power supply operation of the charge pump circuit according to the first digital signal and the second digital signal.

8. The voltage modulation circuit of claim 1, wherein the charge pump circuit comprises:

a mode control circuit, which generates a plurality of switch signals corresponding to the selected power supply mode according to the control signal and outputs the wake-up signal when the switching of the selected power supply mode conforms to the specific condition;

a first energy storage capacitor;

a second energy storage capacitor;

a first fly capacitor;

a second fly capacitor; and

and the switch circuit controls the electrical connection relation among the power supply voltage, the first flying capacitor, the second flying capacitor, the first energy storage capacitor, the second energy storage capacitor and the ground according to the plurality of switch signals.

9. The voltage modulation circuit according to claim 8, wherein the switch circuit keeps disconnecting from the power voltage and keeps the first flying capacitor, the second flying capacitor, the first energy-storage capacitor and the second energy-storage capacitor electrically connected to a post-stage circuit when the charge pump circuit suspends the power supply operation.

10. A voltage modulation method, comprising:

switching from one of a plurality of power supply modes with different power conversion rates to another according to a control signal to serve as a selected power supply mode;

a power supply circuit performs a power supply operation in the selected power supply mode so as to convert a power supply voltage into at least one output voltage for supplying power to a post-stage circuit;

outputting a wake-up signal when the switching of the selected power supply mode conforms to a specific condition;

starting a detection program of the at least one output voltage according to the wake-up signal; and

under the detection procedure, the power supply operation of the power supply circuit is suspended according to the magnitude of the at least one output voltage.