CN114171409A - Fan-out type packaging method and packaging structure - Google Patents

Fan-out type packaging method and packaging structure Download PDF

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Publication number
CN114171409A
CN114171409A CN202111495849.7A CN202111495849A CN114171409A CN 114171409 A CN114171409 A CN 114171409A CN 202111495849 A CN202111495849 A CN 202111495849A CN 114171409 A CN114171409 A CN 114171409A
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layer
chips
functional
density
chip
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杜茂华
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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Priority to CN202111495849.7A priority Critical patent/CN114171409A/en
Publication of CN114171409A publication Critical patent/CN114171409A/en
Priority to PCT/CN2022/137251 priority patent/WO2023104097A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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Abstract

The invention provides a fan-out type packaging method and a packaging structure, wherein the method comprises the following steps: fixing the back surfaces of the multiple groups of functional chips on a wafer carrying disc in a first array mode, and forming a first plastic packaging layer on the front surfaces of the multiple groups of functional chips, wherein the front surfaces of the multiple groups of functional chips are provided with conductive bumps; removing the wafer carrying disc, and forming a high-density interconnection wiring layer on the front surfaces of the plurality of groups of functional chips; cutting a plurality of groups of functional chips, and fixing one side formed with a high-density interconnection wiring layer on a panel carrier in a second array mode; securing a first surface of a plurality of first chips and a plurality of passive devices on a panel substrate; forming a second plastic packaging layer on one side of the plurality of groups of functional chips, which is far away from the high-density interconnection wiring layer, and on the second surfaces of the first chip and the passive device; and removing the panel carrier, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer. The packaging method can well meet the requirement of high-density interconnection, and has low cost and high yield.

Description

Fan-out type packaging method and packaging structure
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out type packaging method and a fan-out type packaging structure.
Background
As semiconductor technology has advanced, packaging technology has advanced toward high density/high integration. Currently, fan-out technology is becoming an important development direction for high density interconnects. The single chip and the multiple chips are connected by using the rewiring layer, so that the flexibility of packaging integration is greatly improved. Fanout technology has been applied in the fields of High Performance Computing (HPC) and cell phone processors.
Currently, there are two main development directions for fan-out technology, one is fan-out wafer level package (FOWLP) based on wafer technology, and the other is fan-out panel level package (FOPLP) based on panel technology. The wiring density of fan-out wafer level packaging can be higher, mass production with the line width of 2 microns is realized at present, but the yield is low, and the cost is high. Fan-out formula panel level encapsulation is because the output rate is high, and is with low costs, nevertheless because the panel size is big, and the fine rule width realizes that the degree of difficulty is big, but present volume production linewidth all is more than 5 um.
For a multi-chip system-in-package, a plurality of chips are contained in the middle, and the wiring density of each chip is different, but the wiring density is required to be different by adopting the same process at present, the strictest technical standard is required to be met, and the manufacturing cost is high.
In view of the above problems, it is necessary to provide a fan-out package method and a package structure that are reasonable in design and can effectively solve the above problems.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art and provides a fan-out type packaging method and a packaging structure.
In one aspect of the invention, a fan-out packaging method is provided, the method comprising:
providing a wafer carrying disc and a panel carrying sheet;
fixing the back surfaces of a plurality of groups of functional chips on the surface of the wafer carrying disc in a first array mode, and forming a first plastic package layer on the front surfaces of the plurality of groups of functional chips, wherein a plurality of conductive bumps are arranged on the front surfaces of the plurality of groups of functional chips;
separating the plurality of groups of functional chips from the wafer carrying disc, and forming a high-density interconnection wiring layer on the front surfaces of the plurality of groups of functional chips;
cutting the plurality of groups of functional chips, and fixing one side of the panel carrier, on which the high-density interconnection wiring layer is formed, on the surface of the panel carrier in a second array mode;
fixing a first surface of a plurality of first chips and a plurality of passive devices on a surface of the panel slide;
forming a second plastic packaging layer on one side of the plurality of groups of functional chips, which is far away from the high-density interconnection wiring layer, and on second surfaces of the plurality of first chips and the plurality of passive devices;
and separating the plurality of groups of functional chips, the plurality of first chips and the plurality of passive devices from the panel slide, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.
Optionally, before forming the high-density interconnection wiring layer on the front surfaces of the plurality of functional chips, the method further includes:
and separating the plurality of groups of functional chips from the wafer carrying disc, and grinding the front surfaces of the plurality of groups of functional chips to expose the conductive bumps.
Optionally, the forming a high-density interconnection wiring layer on the front surfaces of the multiple groups of functional chips includes:
forming a first dielectric layer on the first molding compound layer and the plurality of conductive bumps;
patterning the first dielectric layer to form a plurality of first openings;
forming a first metal interconnection layer on the surface of the patterned first dielectric layer, wherein the first metal interconnection layer is electrically connected with the conductive bump;
and patterning the first metal interconnection layer to form the high-density interconnection wiring layer.
Optionally, the forming a low-density interconnect wiring layer on the surface of the high-density interconnect wiring layer includes:
forming a second dielectric layer on a surface of the high-density interconnect wiring layer, the plurality of first chips, and first surfaces of the plurality of passive devices;
patterning the second dielectric layer to form a plurality of second openings;
forming a second metal interconnection layer on the surface of the patterned second dielectric layer;
and patterning the second metal interconnection layer to form the low-density interconnection wiring layer.
Optionally, after forming the low-density interconnect wiring layer, the method further includes:
forming a third dielectric layer on the surface of the patterned second metal interconnection layer;
patterning the third dielectric layer to form a plurality of third openings;
and planting balls at the third openings to form a plurality of solder balls.
Optionally, each set of functional chips includes at least two different types of chips.
The invention provides a fan-out type packaging structure, which comprises a functional chip set, a first chip, a passive device, a high-density interconnection wiring layer, a low-density interconnection wiring layer, a first plastic packaging layer and a second plastic packaging layer, wherein a conductive bump is arranged on the front surface of the functional chip in the functional chip set;
the high-density interconnection wiring layer is arranged on the first plastic package layer and the front surface of the functional chip in the functional chip group;
the low-density interconnect wiring layer is disposed over the high-density interconnect wiring layer and disposed on the first chip and a first surface of a passive device;
the first plastic packaging layer wraps the functional chip group;
the second plastic packaging layer wraps the functional chip group, the first chip and the passive device.
Optionally, the high-density interconnect wiring layer includes a first dielectric layer disposed on the conductive bump, and a first metal interconnect layer disposed on the first dielectric layer, wherein the first metal interconnect layer is electrically connected to the conductive bump.
Optionally, the low-density interconnect wiring layer includes a second dielectric layer disposed on the first metal interconnect layer, the first chip and the first surface of the passive device, and a second metal interconnect layer disposed on the second dielectric layer.
Optionally, the package structure further includes a third dielectric layer disposed on the second metal interconnection layer, and a plurality of solder balls disposed on the third dielectric layer.
Optionally, the first chip and the passive device are respectively disposed on two sides of the functional chipset.
Optionally, the functional chipset includes at least two different types of chips.
According to the fan-out type packaging method and the packaging structure, the multiple groups of functional chips are interconnected in a high density manner, so that the requirement of high-density interconnection can be well met; the first chip and the passive device are interconnected by adopting low density, so that the yield can be improved, and the manufacturing cost can be reduced. By integrating the wafer level fan-out technology and the panel level fan-out technology, different levels of interconnection are integrated in one package, compared with the traditional fan-out wafer level package, the fan-out packaging method can provide lower cost and higher yield under the condition of the same interconnection density, and compared with the traditional fan-out panel level package, the fan-out packaging method can provide higher interconnection density and meet the requirements of high-performance devices.
Drawings
FIG. 1 is a flow chart illustrating a fan-out packaging method according to an embodiment of the invention;
FIG. 2 is a schematic view of a chip placement area in a wafer carrier according to another embodiment of the present invention;
FIG. 3 is a schematic view of a second array B on a faceplate slide according to another embodiment of the present invention;
FIG. 4 is a schematic view of a first array A on a wafer carrier in accordance with another embodiment of the present invention;
fig. 5 to 19 are schematic views illustrating a packaging process of a fan-out package structure according to another embodiment of the invention.
Fig. 20 is a diagram illustrating a fan-out package structure according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, an aspect of the present invention provides a packaging method S100 for a fan-out package structure, where the packaging method S100 includes:
and S110, providing a wafer carrier disc and a panel carrier.
Specifically, as shown in fig. 2, 3 and 4, a wafer boat 110 and a faceplate slide 120 are provided. The main material of the wafer carrier 110 is glass, silicon wafer or metal. The main material of the panel carrier 120 is glass, metal or glass fiber resin. The materials of the wafer carrier plate 110 and the panel carrier 120 are not particularly limited in this embodiment, and may be selected as needed.
And S120, fixing the back surfaces of the multiple groups of functional chips on the surface of the wafer carrying disc in a first array mode, and forming a first plastic package layer on the front surfaces of the multiple groups of functional chips, wherein the front surfaces of the multiple groups of functional chips are provided with a plurality of conductive bumps.
It should be noted that each group of functional chips includes at least two different types of chips. As shown in fig. 5, in this embodiment, each group of functional chips includes a second chip 150 and a third chip 160, where the second chip 150 and the third chip 160 are different types of chips, and the second chip 150 and the third chip 160 are high performance chips, such as a processor, etc., although each group of functional chips may also include other functional chips, which is not limited in this embodiment. The front surfaces of the sets of functional chips are provided with a plurality of conductive bumps 161, that is, the front surfaces of the second chip 150 and the third chip 160 are provided with a plurality of conductive bumps 161. In this embodiment, the conductive bumps 161 are respectively disposed at two ends of the second chip 150 and the third chip 160, and the conductive bumps 161 are copper conductive bumps, and other metal materials may also be used.
Specifically, as shown in fig. 5, in the present embodiment, the back surfaces of the second chip 150 and the third chip 160 in the plurality of groups of functional chips are fixed on the surface of the wafer carrier 110 by the first chip adhesive 111, and the wafer level packaging technology is used to achieve the requirement of high-density interconnection. As shown in fig. 3, the attached functional chips form a first array a, which is a square array. As shown in fig. 6, the molding compound is used to mold the front surfaces of the plurality of groups of functional chips, that is, the front surfaces of the second chip 150 and the third chip 160 in the plurality of groups of functional chips form a first molding layer 170. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
S130, separating the plurality of groups of functional chips from the wafer carrying disc, and forming a high-density interconnection wiring layer on the front surfaces of the plurality of groups of functional chips.
Specifically, as shown in fig. 7, the groups of functional chips are separated from the wafer blade 110, i.e., the wafer blade 110 is removed. The separation method can adopt methods such as thermal separation, laser separation, ultraviolet light separation, mechanical separation and the like, which are all common temporary bonding separation methods at present, the embodiment of the separation method is not particularly limited, and the separation method can be selected according to actual needs.
As shown in fig. 8, after separating the back surfaces of the plurality of functional chips from the wafer carrier 110, the front surfaces of the plurality of first chips 130 are ground, that is, the front surfaces of the second chip 150 and the third chip 160 are ground to expose the conductive bumps 161 on the front surfaces of the second chip 150 and the third chip 160. Other processes may be adopted to expose the conductive bump 161, and the embodiment is not limited in particular.
Forming a high-density interconnection wiring layer on the front surfaces of the plurality of groups of functional chips, wherein the high-density interconnection wiring layer comprises:
first, a first dielectric layer is formed on the first molding compound layer and the conductive bumps.
Specifically, as shown in fig. 9, the first dielectric layer 151 is coated on the surfaces of the first molding layer 170 and the plurality of conductive bumps 161, the material of the first dielectric layer 151 is Polyimide (PI), Polybenzoxazole (PBO), or the like, the coating method is usually wafer spin coating, and the embodiment is not limited in particular. The first dielectric layer 151 protects the plurality of functional chips.
Then, the first dielectric layer is patterned to form a plurality of first openings.
As shown in fig. 9, the first dielectric layer 151 is patterned by a photolithography process to form a plurality of first openings 152.
And forming a first metal interconnection layer on the surface of the patterned first dielectric layer, wherein the first metal interconnection layer is electrically connected with the conductive bump.
Specifically, as shown in fig. 10, a first metal interconnection layer 153 is deposited on the surface of the patterned first dielectric layer 151. The deposition method may adopt electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the metal material of the first metal interconnection layer 153 is usually metal titanium and metal copper, and the deposition method and the metal material are not particularly limited in this embodiment. The first metal interconnection layer 153 is electrically connected to the conductive bump 161.
And finally, patterning the first metal interconnection layer to form the high-density interconnection wiring layer.
Specifically, as shown in fig. 10, the first metal interconnection layer 153 is patterned by a photolithography and etching process to form a high-density interconnection wiring layer. The etching process may be wet etching or dry etching, and this embodiment is not particularly limited.
In this embodiment, the plurality of groups of functional chips are different types of high performance chips, such as processor chips, and in a system-in-package design, generally, the wiring requirement of the high performance chips is high, so that the high-density interconnection wiring layer is formed by adopting fan-out wafer-level packaging of the plurality of groups of functional chips, which can provide higher interconnection density and meet the requirement of high performance devices.
And S140, cutting the plurality of groups of functional chips, and fixing one side formed with the high-density interconnection wiring layer on the surface of the panel carrier in a second array mode.
Specifically, a plurality of groups of functional chips are cut according to the area of the panel carrier 120 and fixed on the surface of the panel carrier 120 in the form of the second array B shown in fig. 4, and the panel-level packaging technology is used, so that the yield can be improved and the manufacturing cost can be reduced. In this embodiment, as shown in fig. 11, the side on which the high-density interconnection wiring layer is formed is fixed on the panel carrier 120 by the second patch adhesive 121, that is, the first metal interconnection layer 153 is attached to the second patch adhesive 121.
S150, fixing the first surfaces of the first chips and the passive devices on the surface of the panel slide.
It should be noted that, in the present embodiment, the first chip 130 is a low-performance chip, and may also be another type of chip, and the present embodiment is not particularly limited. The passive device 140 may be at least one of a resistor, a capacitor, an inductor, a converter, a fader, a matching network, a resonator, a filter, a mixer, a switch, and the like, and the embodiment is not particularly limited.
Specifically, as shown in fig. 12, a plurality of first chips 130 and a plurality of passive devices 140 are also fixed on the panel chip 120 by the second adhesive 121. Further, in the present embodiment, the first chip 130 and the passive device 140 are respectively disposed at both sides of each group of functional chips. The first chip 130 and the passive devices 140 may also be distributed in other manners, and this embodiment is not particularly limited.
And S160, forming a second plastic packaging layer on one side of the plurality of groups of functional chips, which is far away from the high-density interconnection wiring layer, and on second surfaces of the plurality of third chips and the plurality of passive devices.
Specifically, as shown in fig. 13, a plurality of sets of functional chips are mounted on the panel carrier 120 in the form of a second array B, and then a second molding layer is formed on a side of the plurality of sets of functional chips facing away from the high-density interconnection wiring layer and on second surfaces of the plurality of first chips 130 and the plurality of passive devices 140. That is, the second molding layer 180 encapsulates the plurality of first chips 130, the plurality of passive devices 140, the plurality of second chips 150, and the plurality of third chips 160. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
S170, separating the plurality of groups of functional chips, the plurality of first chips and the plurality of passive devices from the panel slide, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.
Specifically, as shown in fig. 14, the plurality of sets of functional chips, the plurality of first chips 130, and the plurality of passive devices 140 are separated 120 from the panel chip, that is, the panel chip 120 is removed. The separation method can adopt methods such as thermal separation, laser separation, ultraviolet light separation, mechanical separation and the like, which are all common temporary bonding separation methods at present, the embodiment of the separation method is not particularly limited, and the separation method can be selected according to actual needs.
Forming a low-density interconnect wiring layer on the high-density interconnect wiring layer, comprising:
first, a second dielectric layer is formed on the surface of the high-density interconnect wiring layer, the first chips, and the first surfaces of the passive devices.
Specifically, as shown in fig. 15, the second dielectric layer 131 is formed on the first metal interconnection layer 153, the first surfaces of the plurality of first chips 130, and the first surfaces of the plurality of passive devices 140. The second dielectric layer 131 protects the first metal interconnection layer 153. The material of the second dielectric layer 131 is a photo dielectric layer (PID) or an ajinomoto laminated film (ABF), and the embodiment is not limited in particular. The process of covering the first metal interconnection layer 153, the first surfaces of the first chips 130 and the first surfaces of the passive devices 140 with the second dielectric layer 131 may be a vacuum lamination or a printing process, and the embodiment is not particularly limited.
And secondly, patterning the second dielectric layer to form a plurality of second openings.
Specifically, as shown in fig. 15, the second dielectric layer 131 is patterned by using a photolithography process, and a plurality of second openings 132 are formed on the second dielectric layer 131.
And thirdly, forming a second metal interconnection layer on the surface of the patterned second dielectric layer.
Specifically, as shown in fig. 16, a second metal interconnection layer 133 is deposited on the surface of the patterned second dielectric layer 131. The deposition method may adopt electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the metal material of the second metal interconnection layer 133 is usually metal titanium and metal copper, and the deposition method and the metal material are not particularly limited in this embodiment.
And finally, patterning the second metal interconnection layer to form the low-density interconnection wiring layer.
Specifically, as shown in fig. 16, the second metal interconnection layer 133 is patterned by a photolithography and etching process to form a low-density interconnection wiring layer. The etching process may be wet etching or dry etching, and this embodiment is not particularly limited.
In this embodiment, the first chip is a low-performance chip, such as a power device, and in a system-in-package design, the wiring requirement of the low-performance chip is generally low, so that the fan-out panel-level package is adopted to form the low-density interconnection wiring layer by the plurality of first chips and the plurality of passive devices, so that the yield can be improved, and the manufacturing cost can be reduced.
Illustratively, the dielectric materials of the first dielectric layer 151 and the second dielectric layer 131 are different. The first dielectric layer 151 is made of Polyimide (PI), Polybenzoxazole (PBO), or the like, and the second dielectric layer 131 is made of a photo dielectric layer (PID), an ajinomoto laminated film (ABF), or the like. This is because the first dielectric layer 151 is fabricated on a wafer level process and the second dielectric layer 131 is fabricated on a panel level process. The optimal dielectric layer is selected according to different processes, and the materials of the two dielectric layers are close to each other, so that the problems of poor contact or incapability of realizing the process and the like can not occur.
Illustratively, after forming the low-density interconnect routing layer, the method further comprises:
firstly, a third dielectric layer is formed on the surface of the patterned second metal interconnection layer.
Specifically, as shown in fig. 17, a third dielectric layer 134 covers the surface of the patterned second metal interconnection layer 133, and a light-sensitive solder resist (PSR) or the like may be used as a material of the third dielectric layer 134, which is not limited in this embodiment. The process of covering the second metal interconnection layer 133 with the third dielectric layer 134 may be a vacuum lamination or printing process, and the embodiment of the process of covering the second metal interconnection layer 133 with the third dielectric layer 134 is not particularly limited.
And secondly, patterning the third dielectric layer to form a plurality of third openings.
Specifically, as shown in fig. 17, the third dielectric layer 134 is patterned through a photolithography process, and a plurality of third openings 135 are formed on the third dielectric layer 134.
And finally, carrying out ball planting at the third openings to form a plurality of solder balls.
Specifically, as shown in fig. 18, ball mounting is performed at the plurality of third openings 135 to form a plurality of solder balls 136, and the plurality of solder balls 136 are electrically connected to the outside.
Illustratively, as shown in fig. 19, after forming a plurality of solder balls 136, the plurality of groups of functional chips and the first chip 130 and the passive device 140 located at both sides of each group of functional chips are cut to form a single group of chip package structures. Each group of chip package structures includes the second chip 150 and the third chip 160 in the middle region, and the first chip 130 and the passive device 140 in the edge region.
It should be noted that, if the thickness of the formed second plastic package layer 180 is very thick, after the solder balls 136 are formed, the side of the second plastic package layer away from the plurality of groups of functional chips may be polished, so that the package thickness is reduced. Also can polish the side of the second plastic-sealed layer departing from the plurality of groups of functional chips after the second plastic-sealed layer 180 is formed, so that the packaging thickness is reduced. Finally, an optimal packaging structure is formed.
According to the fan-out type packaging method and the packaging structure, the multiple groups of functional chips are interconnected in a high density manner, so that the requirement of high-density interconnection can be well met; the first chip and the passive device are interconnected by adopting low density, so that the yield can be improved, and the manufacturing cost can be reduced. By integrating the wafer level fan-out technology and the panel level fan-out technology, different levels of interconnection are integrated in one package, compared with the traditional fan-out wafer level package, the fan-out packaging method can provide lower cost and higher yield under the condition of the same interconnection density, and compared with the traditional fan-out panel level package, the fan-out packaging method can provide higher interconnection density and meet the requirements of high-performance devices.
It should be noted that, in the given embodiment, the dielectric layer structure is 3 layers or 4 layers, and the invention can be applied to various layers, which can be adjusted according to the actual design requirement. The number of interconnection layers used in the wafer-level and panel-level processes can also be adjusted according to actual design requirements, for example, when the second interconnection layer also needs high-density interconnection (the panel-level process cannot be realized), the two interconnection layers can be manufactured by using the wafer-level process, and then the wafer-level and panel-level processes are carried out.
It should be further noted that, in the present invention, as shown in fig. 2, the middle area of the wafer carrier 110 is a chip arrangement area 112, the chip arrangement areas 112 are distributed in a first array a as shown in fig. 3, and the chip arrangement area 112 is a square structure, and the diagonal length thereof is equivalent to the diameter of the wafer carrier 110. A high density interconnect wiring layer is formed within the intermediate region by temporary attachment and wafer level rewiring. The chip arrangement region 112 where the high-density interconnection is completed is cut and integrally built on the panel chip 120 in the form of a second array B as shown in fig. 4.
As shown in fig. 4, the size of the currently-used panel carrier 120 is 510 × 515 mm, in this case, 4 chip layout areas 112 can be placed at the same time, and the subsequent process is completed by using the panel-level package interconnection technology, so that the production efficiency can reach 4 times that of the wafer-level package technology, and in the future, if the LCD panel technology is used, the production efficiency can be improved by 6-8 times, and the cost is greatly reduced.
As shown in fig. 2, since the area of the chip placement region 112 is smaller than the area of the wafer carrier 110, a certain area loss will occur. Considering that the chips are all rectangular or square in size, the main wear area is a blank area 113 in the figure, with a short side dimension of 28 mm. For samples with package sizes close to or larger than 28 mm, this area is an invalid area, but for samples with package sizes close to or smaller than 28 mm, the blank area 113 can also be used, so the design of the chip layout area 112 does not increase the cost of the wafer level package. The high-density interconnection is mainly applied to the fields of high-performance calculation and the like, and the packaging in the field is developing towards a large-size direction, so that the high-density interconnection has a remarkable cost reduction effect.
In a package design, the density of the interconnection layer close to the chip is high, while the density of the interconnection layer far from the chip is low, and the connection line width tends to expand step by step. By utilizing the characteristics, the packaging method of the fan-out type packaging structure provided by the invention integrates and uses the fan-out type wafer level packaging technology and the fan-out type panel level packaging technology to complete the fan-out type packaging manufacture, the wafer level packaging technology is used for the interconnection layer close to the chip, the high-density interconnection requirement can be well realized, and the panel level packaging technology is used for the interconnection layer far away from the chip, so that the yield can be improved, and the manufacturing cost can be reduced.
As shown in fig. 19, another aspect of the present invention provides a fan-out package structure 100, where the package structure 100 includes a functional chip set (not shown), a first chip 130, a passive device 140, a high-density interconnect wiring layer (not shown), a low-density interconnect wiring layer (not shown), a first molding compound layer 170, and a second molding compound layer 180, where a front surface of the functional chip in the functional chip set is provided with a conductive bump 161.
It should be noted that each functional chipset includes at least two different kinds of chips. As shown in fig. 18, in this embodiment, each functional chip set includes a second chip 150 and a third chip 160, the second chip 150 and the third chip 160 are different types of chips, and the second chip 150 and the third chip 160 are high performance chips, such as a processor, etc., although each group of functional chips may also include other functional chips, which is not limited in this embodiment. The front surface of the functional chip in the functional chipset is provided with a conductive bump 161, that is, a plurality of conductive bumps 161 are provided on the front surfaces of the second chip 150 and the third chip 160.
In this embodiment, the first chip 130 is a low-performance chip, and may also be another type of chip, and this embodiment is not limited in particular. The passive device 140 may be at least one of a resistor, a capacitor, an inductor, a converter, a fader, a matching network, a resonator, a filter, a mixer, a switch, and the like, and the embodiment is not particularly limited.
As shown in fig. 19, the high-density interconnect wiring layer is disposed on the first molding layer 170 and the front surface of the functional chip in the functional chipset. That is, the high-density interconnection wiring layer is disposed on the surface of the first molding layer 170 and the front surfaces of the second and third chips 150 and 160. Further, a high-density interconnect wiring layer is disposed on the surface of the first molding layer 170 and the conductive bump 161.
As shown in fig. 19, the low-density interconnect wiring layer is disposed over the high-density interconnect wiring layer, and the first chip 130 and the first surface of the passive device 140. In the present embodiment, the first chip 130 and the passive device 140 are respectively disposed on both sides of the functional chip set.
As shown in fig. 18, the first molding layer 170 wraps the functional chipset. That is, the first molding layer 170 wraps the plurality of second chips 150 and the plurality of third chips 160.
As shown in fig. 19, the second plastic package layer 180 encapsulates the functional chip set, the first chip 130, and the passive device 140. That is, the second molding layer 180 encapsulates the plurality of first chips 130, the plurality of passive devices 140, the plurality of second chips 150, and the plurality of third chips 160.
Illustratively, as shown in fig. 18, the high-density interconnect wiring layer includes a first dielectric layer 151 disposed on the conductive bump 161, and a first metal interconnect layer 153 disposed on the first dielectric layer 151. That is, the first dielectric layer 151 is disposed on the conductive bump 161 in each set of functional chips.
Illustratively, the low-density interconnect wiring layer includes a second dielectric layer 131 disposed on the first metal interconnect layer 153, the first chip 130 and the first surface of the passive device 140, and a second metal interconnect layer 133 disposed on the second dielectric layer 131.
Illustratively, the package structure further includes a third dielectric layer 134 and a plurality of solder balls 136, wherein the third dielectric layer 134 is disposed on the second metal interconnection layer 133, and the plurality of solder balls 136 are disposed on the third dielectric layer 134.
The fan-out type packaging structure provided by the invention has the advantages of low cost and high yield, and can well meet the requirement of high-density interconnection.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (12)

1. A fan-out packaging method, the method comprising:
providing a wafer carrying disc and a panel carrying sheet;
fixing the back surfaces of a plurality of groups of functional chips on the surface of the wafer carrying disc in a first array mode, and forming a first plastic package layer on the front surfaces of the plurality of groups of functional chips, wherein a plurality of conductive bumps are arranged on the front surfaces of the plurality of groups of functional chips;
separating the plurality of groups of functional chips from the wafer carrying disc, and forming a high-density interconnection wiring layer on the front surfaces of the plurality of groups of functional chips;
cutting the plurality of groups of functional chips, and fixing one side of the panel carrier, on which the high-density interconnection wiring layer is formed, on the surface of the panel carrier in a second array mode;
fixing a first surface of a plurality of first chips and a plurality of passive devices on a surface of the panel slide;
forming a second plastic packaging layer on one side of the plurality of groups of functional chips, which is far away from the high-density interconnection wiring layer, and on second surfaces of the plurality of first chips and the plurality of passive devices;
and separating the plurality of groups of functional chips, the plurality of first chips and the plurality of passive devices from the panel slide, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.
2. The method of claim 1, wherein before forming a high-density interconnect wiring layer on the front side of the plurality of functional chips, the method further comprises:
and separating the plurality of groups of functional chips from the wafer carrying disc, and grinding the front surfaces of the plurality of groups of functional chips to expose the conductive bumps.
3. The method of claim 2, wherein forming a high-density interconnect wiring layer on the front side of the plurality of functional chips comprises:
forming a first dielectric layer on the first molding compound layer and the plurality of conductive bumps;
patterning the first dielectric layer to form a plurality of first openings;
forming a first metal interconnection layer on the surface of the patterned first dielectric layer, wherein the first metal interconnection layer is electrically connected with the conductive bump;
and patterning the first metal interconnection layer to form the high-density interconnection wiring layer.
4. The method of claim 3, wherein said forming a low density interconnect routing layer on said high density interconnect routing layer surface comprises:
forming a second dielectric layer on a surface of the high-density interconnect wiring layer, the plurality of first chips, and first surfaces of the plurality of passive devices;
patterning the second dielectric layer to form a plurality of second openings;
forming a second metal interconnection layer on the surface of the patterned second dielectric layer;
and patterning the second metal interconnection layer to form the low-density interconnection wiring layer.
5. The method of claim 4, wherein after forming the low density interconnect routing layer, the method further comprises:
forming a third dielectric layer on the surface of the patterned second metal interconnection layer;
patterning the third dielectric layer to form a plurality of third openings;
and planting balls at the third openings to form a plurality of solder balls.
6. The method according to any one of claims 1 to 5, wherein each set of functional chips comprises at least two different types of chips.
7. A fan-out type packaging structure is characterized by comprising a functional chip set, a first chip, a passive device, a high-density interconnection wiring layer, a low-density interconnection wiring layer, a first plastic package layer and a second plastic package layer, wherein a conductive bump is arranged on the front surface of the functional chip in the functional chip set;
the high-density interconnection wiring layer is arranged on the first plastic package layer and the front surface of the functional chip in the functional chip group;
the low-density interconnect wiring layer is disposed over the high-density interconnect wiring layer and disposed on the first chip and a first surface of a passive device;
the first plastic packaging layer wraps the functional chip group;
the second plastic packaging layer wraps the functional chip group, the first chip and the passive device.
8. The package structure of claim 7, wherein the high-density interconnect routing layer comprises a first dielectric layer disposed on the conductive bump and a first metal interconnect layer disposed over the first dielectric layer, wherein the first metal interconnect layer is electrically connected to the conductive bump.
9. The package structure of claim 8, wherein the low-density interconnect routing layer comprises a second dielectric layer disposed over the first metal interconnect layer, the first chip, and the first surface of the passive device, and a second metal interconnect layer disposed over the second dielectric layer.
10. The package structure of claim 9, further comprising a third dielectric layer disposed over the second metal interconnect layer and a plurality of solder balls disposed over the third dielectric layer.
11. The package structure according to any one of claims 7 to 10, wherein the first chip and the passive device are respectively disposed on two sides of the functional chipset.
12. The package structure according to any of claims 7 to 10, wherein the functional chipset comprises at least two different types of chips.
CN202111495849.7A 2021-12-08 2021-12-08 Fan-out type packaging method and packaging structure Pending CN114171409A (en)

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PCT/CN2022/137251 WO2023104097A1 (en) 2021-12-08 2022-12-07 Fan-out packaging method and packaging structure thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104097A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104097A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure thereof

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