CN114167256B - Analog measurement device and method based on digital TDR technology - Google Patents
Analog measurement device and method based on digital TDR technology Download PDFInfo
- Publication number
- CN114167256B CN114167256B CN202111373933.1A CN202111373933A CN114167256B CN 114167256 B CN114167256 B CN 114167256B CN 202111373933 A CN202111373933 A CN 202111373933A CN 114167256 B CN114167256 B CN 114167256B
- Authority
- CN
- China
- Prior art keywords
- signal
- tdr
- channel
- measurement
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005259 measurement Methods 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000005516 engineering process Methods 0.000 title claims abstract description 25
- 238000012360 testing method Methods 0.000 claims abstract description 110
- 238000012937 correction Methods 0.000 claims abstract description 11
- 230000005540 biological transmission Effects 0.000 claims description 36
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 238000000691 measurement method Methods 0.000 claims description 13
- 230000000630 rising effect Effects 0.000 claims description 7
- 238000001914 filtration Methods 0.000 claims description 5
- 238000004458 analytical method Methods 0.000 claims description 4
- 230000002457 bidirectional effect Effects 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 10
- 238000002310 reflectometry Methods 0.000 description 5
- 239000013598 vector Substances 0.000 description 4
- 238000012795 verification Methods 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100428216 Caenorhabditis elegans vab-1 gene Proteins 0.000 description 1
- 230000001174 ascending effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000013215 result calculation Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
An analog measuring device and a measuring method based on a digital TDR technology are used for measuring and calculating delay information of N paths of channels and carrying out delay correction on measured data during formal measurement; the device comprises an FPGA module, a pin driver PE corresponding to the multipath channel, an RC filter circuit and an analog-digital converter ADC. The invention solves the problem of insufficient time synchronization precision of the pins of the digital integrated circuit test system by using the analog measurement low-cost digital TDR technology, can perform batch automatic test, can conveniently and fast recalibrate the measurement signals when the test environment changes, and can perform compensation correction, automatic precision adjustment, measurement aiming at any path model, and good universality.
Description
Technical Field
The invention relates to the field of automatic semiconductor test equipment (Automatic Test Equipment, ATE for short), in particular to an analog measurement device and a measurement method based on digital time domain reflectometry (Time Domain Reflectometry, TDR).
Background
With great advances in science and technology and wide application in society, the development of integrated circuit industry can be said to be very different. The chips used, both on a crystal scale and at an operational rate, have greatly increased, thereby presenting increasing challenges for the production and testing of integrated circuits.
Especially in the test field, as the running speed of the chip increases, the system clock frequency increases, allowing errors in the time parameters to be continuously reduced. In a low-speed test system, the vector period is often 50ns or 100ns, the test signal of the test channel reaches a sufficient steady state time, and the process of signal transmission and the transient process of signal establishment in the channel can be basically ignored. However, in high speed systems, the system clock often reaches above 100MHz, taking into account the time of arrival of the signal.
That is, the problem of pin time synchronization accuracy, i.e., the problem of time synchronization of the test vectors for each pin (pin) loaded onto the chip under test (Device Under Test, DUT), requires significant attention. Assuming that there are 2 pins with poor time synchronicity, 2 test signals that should arrive at them at the same time, the arrival times differ by 10ns, a large probability is not a problem for a system with a vector period of 100ns, but a problem is likely to occur for a system with a vector period of 10ns, and incorrect logic outputs are likely to occur on the DUT, resulting in DUT test failure. This is a problem that the pin time synchronization accuracy is insufficient, and the higher the system is, the higher the pin time synchronization accuracy is required.
The source of the asynchronous pin time is the different transmission paths of the test signals. It is well known that electrical signals are also one type of electromagnetic wave, having a specific velocity of propagation in a medium. The theoretical transmission rate is described by the following formula:
Wherein, the light speed in the vacuum of c 0, the relative dielectric constant of epsilon r and the relative magnetic permeability of mu r
The equation indicates that the propagation speed of the electrical signal in the medium is lower than the propagation speed of light in vacuum. For example, in some 50Ω coaxial cables the propagation speed of the electrical signal is about 2/3 times the speed of light. Accordingly, the propagation of the electrical signal in the medium also requires a corresponding time. Also, similar to acoustic waves, reflection occurs when impedance changes are encountered during transmission, which results in different transmission paths and different transmission times.
In the digital integrated circuit test system, because the wiring, the connector, the clamp and the like of the test board are different, each test channel has a path difference necessarily, so that the channel time delays are different.
Considering that these propagation delays are unavoidable, some manufacturers often concentrate a large number of signal generation, signal measurement and data processing circuits, etc. in the test head closest to the DUT, and the data of the DUT being tested is also processed at the first time in the test head. Nevertheless, the transmission delay and the delay variance of the test channel cannot be completely eliminated.
There are also manufacturers who use external calibration methods. The real arrival time difference of the pulse signals of all pins is directly measured on a Device Interface Board (DIB) by using external auxiliary measuring equipment, and the difference is corrected to a signal transmitting end of a test channel at one time. However, this measurement is time consuming and labor intensive, so these corrections are typically not altered once written to the system. If a user changes the DUT fixture or DIB according to the test requirements, new differences in transmission delay between channels will be introduced, and the limitation is obvious.
Therefore, high-end test system manufacturers are urgently required to solve the problem of pin time synchronization accuracy.
Disclosure of Invention
The invention aims to provide a low-cost digital TDR technology adopting analog measurement, which solves the problem of insufficient time synchronization precision of pins of a digital integrated circuit testing system.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
An analog measuring device based on digital TDR technology is used for measuring and calculating delay information (delay parameter) of N paths of channels and carrying out delay correction on measured data during formal measurement; the device comprises an FPGA module 1, N pin drivers PE 2 corresponding to the N paths of channels, an RC filter circuit 3 and an analog-digital converter ADC 4; wherein,
The FPGA module 1 is used for realizing the transmission and the reception of the N-channel test signals and the selection of data channels; the device comprises an N-path PWM generator 1-1, an N-path transmission signal selector 1-2, an N-path data transmission path 1-3, an N-path data receiving path 1-4 and a data path selector 1-5;
The PWM generator 1-1 is used for generating a TDR test pattern of each channel; the transmit signal selector 1-2 of each channel selects either a transmit normal test pattern or a TDR test pattern by enabling signal tdr_en;
The data transmission path 1-3 of each channel comprises a first programmable delay unit and a transmission logic resource unit, wherein the first programmable delay unit is used for carrying out delay synchronization on a normal test pattern of the channel during normal test, and the transmission logic resource unit is used for transmitting the TDR test pattern or the normal test pattern to a pin driver PE 2; wherein, the initialization value of the first programmable delay unit is 0;
Each pin driver PE 2 is configured to perform port level conversion on the TDR test pattern of the corresponding channel, and configure different level thresholds according to a level threshold decision rule; the pin driver PE 2 comprises a receiving channel end cmpl, a transmitting channel end data and a testing bidirectional channel end;
The data receiving path 1-4 of each channel comprises a receiving logic resource unit and a second programmable delay unit, wherein the logic resource unit is used for receiving the measurement signals of the corresponding channel input by the pin driver PE 2, and the second programmable delay unit is used for carrying out delay synchronization on the measurement signals of the corresponding channel; the second programmable delay is used for carrying out delay synchronization on the normally received test data of the channel during normal test;
The data path selector 1-5 gates one of the N paths by selecting a signal tdr_dc_sel, and transmits the measured TDR signal to an external measurement unit;
The RC filter circuit 3 performs low-pass filtering on the TDR signal after judgment and selection, and converts the duty ratio signal into an analog signal of direct-current voltage;
the ADC 4 performs analog-to-digital conversion on the analog signal of the dc voltage filtered by the RC filter 3 to obtain a digitized voltage value, and generates determination results of different duty ratios for the TDR reflection signal of the TDR test pattern, and cooperates with the time/voltage coefficient to obtain a measurement result of the corresponding channel.
Further, the FPGA module 1 further includes a parameter configuration unit PWM configured to configure the continuous step signal period parameter of the PWM generator 1-1, confirm the period and the duty cycle of the TDR test pattern, and set the threshold level of the pin driver PE 2.
In order to achieve the above object, a further technical solution of the present invention is as follows:
The measuring method of the analog measuring device based on the digital TDR technology comprises a measuring signal generating step for measuring and calculating delay information of N paths of channels and a testing step for carrying out delay correction on measuring data in the formal measurement, wherein the delay information generating step comprises the following steps:
Step S1: configuring parameters of an internal module of the FPGA 1, including setting parameters of a PWM generator 1-1, and confirming the period and the duty ratio of a TDR test pattern; setting a transmission signal selector 1-2, setting TDR_EN of a test channel to 1, and gating a TDR test pattern; setting a data path selector 1-5, selecting a required test path through TDR_DC_SEL;
Step S2: setting a threshold level of a pin driver PE 2, judging a received TDR signal, and transmitting a TDR signal result fed back by a connector to a data receiving channel 1-4 of the FPGA module 1 through a pin of the pin driver PE 2; then through the data path selector 1-5, the data is output to the external measuring unit in a gating way; wherein the external measurement unit may comprise an RC filter circuit 3 and an analog to digital converter ADC 4;
step S3: the signal is converted into a direct current level through an RC filter circuit 3, and digital signal conversion is completed at an analog-digital converter ADC 4; obtaining digital voltage corresponding to the TDR signal;
step S4: repeating the step S2, setting different threshold levels, and obtaining digital voltages corresponding to a plurality of groups of TDR signals of the current channel;
step S5: obtaining a measurement result of the current channel according to the corresponding TDR signal measurement method;
Step S6: repeating the steps S1-S5, and measuring measurement signals of all channels;
step S7: and taking the measurement results of all channels which are more than or equal to each other as time delay parameters for synchronization, and inputting the time delay parameters for synchronization into the first programmable time delay unit and the second programmable time delay unit so as to perform time delay correction on measurement data in the follow-up normal measurement.
Further, the step S2 specifically includes:
step S21: the PWM generator 1-1 continuously transmits a square wave signal S0 with a period of T0, wherein the high level width of the square wave signal S0 is Th;
Step S22: the square wave signal S0 is sent through a pin driver PE 2 and reaches a DUT pin end through a selected test channel, and as the DUT pin end is suspended, R is in an infinite state to form a TDR reflected signal, and a source signal is overlapped with the TDR reflected signal to form a signal S1;
Step S23: the signal S1 is subjected to a process of performing multi-threshold judgment by the pin driver PE 2 to form a signal S2, and the signal S2 generates a time difference Tv between two thresholds according to different comparison thresholds; wherein Tv comprises two parts of time, one is the channel delay Tdly and the other is the voltage rise time;
step S24: and (3) eliminating the influence of the voltage rise time by adopting a method for judging a plurality of threshold positions, and obtaining accurate channel delay Tdly.
Further, the multi-threshold judging process specifically includes:
Step S241: the pin driver PE2 uses 1/6 and 5/6 level thresholds respectively, the comparison threshold a is 1/6, and the comparison threshold b is 5/6; obtaining a threshold time difference Tv2 according to the method of the step S23;
step S242: the pin driver PE2 uses 2/6 and 4/6 level thresholds respectively, the comparison threshold a is 2/6, and the comparison threshold b is 4/6; obtaining a threshold time difference Tv1 according to the method of the step S23;
Step S243: setting the voltage rising time which is the same with the 1/6-5/6 level threshold and the 2/6-4/6 level threshold and the voltage rising time which is the same with the 3/6-4/6 level threshold and the 4/6-5/6 level threshold; tdly can be calculated using the following method:
Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
further, the step S24 further includes a step S25: and sequentially checking the time/voltage coefficient of each channel in the N channels.
Further, the step S25 specifically includes:
Step S251: setting a period of the check pattern as T0, and setting a decision threshold as one of 1/6, 2/6, 3/6, 4/6 and 5/6 level thresholds;
Step S252: setting the high level time as Th, and measuring the voltage value as V1 by the ADC 4;
Step S253: resetting the high level time to be Th+delta T, and measuring the voltage value to be V2 by the ADC 4;
Step S254: analysis results in ΔT corresponding to ΔV= (V2-V1), so ΔT/ΔV yields a coefficient k (ps/mv), i.e., a time/voltage coefficient.
From the above technical scheme, the invention has the following beneficial effects:
① . The method is simple and effective without depending on an external measurement environment, and has small workload; the automatic test device can perform batch automatic test, and can conveniently and fast recalibrate the measurement signals to compensate and correct when the test environment changes.
② . And an active probe is not needed, so that unnecessary interference factors are avoided being introduced, and the measurement accuracy is further improved.
③ . The method has the advantages of no range limitation, automatic precision adjustment, measurement aiming at any path model and good universality.
④ . The method has the advantages of low cost, good effect, and the precision is related to the clock of the test system, is independent of the absolute precision of analog acquisition, and can conveniently improve the measurement precision through clock frequency upgrading so as to meet the test requirement which is continuously changed.
Drawings
FIG. 1 is a schematic diagram of a TDR signal model
FIG. 2 is a schematic diagram showing functional blocks of an analog measurement device based on digital TDR technology according to an embodiment of the present invention
FIG. 3 is a schematic diagram of an analog measurement method based on digital TDR technology according to an embodiment of the invention
FIG. 4 is a schematic diagram of a TDR signal measurement method (using multi-threshold decision principle) according to an embodiment of the present invention
FIG. 5 is a schematic diagram of the time/voltage coefficient calibration principle according to an embodiment of the present invention
Detailed Description
The following describes embodiments of the present invention in further detail with reference to FIGS. 1-5.
It should be noted that the low-cost digital TDR technique of analog measurement adopted by the present invention is called a time domain reflectometry technique (Time Domain Reflectometry). TDR is a technique in which a gate determines the state of a system under test by evaluating transmitted and reflected signals in the time domain. The TDR time domain reflectometry technique is the main tool for measuring the characteristic impedance of transmission lines and works in a similar way to radar localization techniques.
Referring to fig. 1, fig. 1 is a schematic diagram of a TDR signal model. Assuming the impedance of the path under test is R, for step signals, as shown in fig. 1, there are three ideal models for TDR techniques:
When R is = infinity (open circuit), the energy of the end measuring point is totally reflected back, and is overlapped with the original signal to form an ascending step signal;
When r=r0 (impedance matching), the transmitted energy is just absorbed by the impedance R at the end, no energy is reflected back, and the signal is unchanged;
When r=0 (short circuit), the end measurement point will generate a reflection of negative energy, which is superimposed with the original signal as a falling step signal.
The low-cost digital TDR technology adopting analog measurement measures the time parameter of Tdly position when based on R= infinity, thereby obtaining the measurement signal of the measurement path.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a functional module of a TDR measurement circuit in the embodiment of the present invention. The analog measuring device based on the digital TDR technology is used for measuring and calculating delay information of N paths of channels before testing and carrying out delay correction on measured data during formal measurement.
As shown in fig. 2, the analog measurement device based on the digital TDR technology includes a programmable gate array FPGA1, a pin driver PE2 corresponding to N channels, an RC filter circuit 3, and an analog-to-digital converter ADC4.
In an embodiment of the present invention, FPGA module 1 (programmable gate array) is used to implement the transmission and reception of test signals and the selection of data paths. The FPGA1 module mainly can comprise a data path for realizing the transmission and the reception of the N-channel test signals; it includes an N-way PWM generator 1-1, an N-way transmission signal selector 1-2, an N-way data transmission path 1-3, an N-way data reception path 1-4, and a data path selector 1-5.
A PWM generator 1-1 for generating a TDR test pattern, i.e. a continuous step signal, for each channel, the signal period being programmable to adapt to different measurement environments or to the accuracy. The transmit signal selector 1-2 selects whether to transmit the normal test pattern or the TDR test pattern through tdr_en, and each channel can individually enable the PWM signal to the test signal output terminal.
The data transmission path 1-3 of each channel comprises a first programmable delay unit and a transmission logic resource unit, wherein the first programmable delay unit is used for carrying out delay synchronization on a normal test pattern of the channel during normal test, and the transmission logic resource unit is used for transmitting the TDR test pattern or the normal test pattern to a pin driver PE2; wherein, the initialization value of the first programmable delay unit is 0.
The data receiving paths 1-4 of each channel comprise a receiving logic resource unit and a second programmable delay unit, wherein the logic resource unit is used for receiving a peripheral sampling signal input through a pin driver PE2, and the second programmable delay unit is used for carrying out delay synchronization on the peripheral sampling signal; wherein, the initialization value of the second programmable delay unit is 0; when the step of generating the measurement signal for measuring and calculating the delay information of the N channels is completed, the value of the second programmable delay unit is a synchronous measurement signal, and the second programmable delay unit is used for carrying out delay synchronization on the normally received test data of the channel during normal test;
The data path selector 1-5 gates one of the N paths by selecting the signal tdr_dc_sel, and transmits the measured TDR signal to an external measurement unit.
Each pin driver PE 2 is configured to perform port level conversion on the TDR test pattern of the corresponding channel, configure different level thresholds according to a level threshold determination rule, perform level determination on a TDR reflection signal of the TDR test pattern, generate a digital logic signal, and return to the FPGA1 unit for post-processing.
The pin driver PE 2 is used for carrying out port level conversion on the TDR test patterns of the corresponding channels, configuring different level thresholds according to a level threshold judging rule, receiving signal level threshold judging and other functions; the pin driver PE 2 comprises a receiving channel end cmpl, a transmitting channel end data and a testing bidirectional channel end; port level conversion can be performed as required to complete the functions of tri-state output of the TDR test pattern and the like.
Specifically, the pin driver PE 2 completes conversion from a digital level signal to an analog level signal and control of tri-state output by configuring different level thresholds. After completion, the signal is outputted to the N-way transmission signal selector 1-2 inside the FPGA module 1 through the pin (CMPL) of the pin driver PE 2.
After the voltage is measured by the post-stage ADC4, the result calculation and the judgment result of different duty ratios on the TDR reflection signal can be carried out, so that the measurement result of the channel is obtained.
The RC filter circuit 3 (a resistive-capacitive filter circuit) has a main function of performing low-pass filtering on the TDR signal after being determined and selected, and converting the duty ratio signal into a dc voltage for the subsequent circuit to perform analog acquisition.
ADC 4 (analog-digital converter) performs low-pass filtering to TDR signal after decision selection, and converts duty ratio signal into DC voltage analog signal, i.e. RC filtered DC signal, and performs analog-digital conversion to obtain digitized voltage value, and enters into post-stage processing module to be converted into time delay result in cooperation with time/voltage coefficient.
The analog measurement method based on the digital TDR technology in the embodiment of the invention comprises the following steps:
Step S1: configuring parameters of an internal module of the FPGA 1, including setting parameters of a PWM generator 1-1, and confirming the period and the duty ratio of a TDR test pattern; setting a transmission signal selector 1-2, setting TDR_EN of the test channel to 1, and gating the TDR test pattern; the data path selector 1-5 is set to select the desired test path via TDR _ DC _ SEL.
Specifically, the internal module parameters may include setting a PWM generator 1-1 parameter, confirming a period and a duty cycle of the TDR test pattern; the set transmission signal selector 1-2 selects transmission of a normal test pattern or a TDR test pattern by the enable signal tdr_en, for example, by setting the enable signal tdr_en of the test channel to 1, strobing transmission of the TDR test pattern, or by setting the enable signal tdr_en of the test channel to 0, strobing transmission of the normal test pattern.
The data path selector 1-5 is set to select the desired test channel by means of the selection signal tdr_dc_sel, i.e. to gate one of the N channels by means of the selection signal tdr_dc_sel, and to transmit the measured TDR signal to the external measurement unit.
Step S2: setting a threshold level of a pin driver PE 2, judging a received TDR signal, and transmitting a TDR signal result fed back by a connector to a data receiving channel 1-4 of the FPGA module 1 through a pin of the pin driver PE 2; then through the data path selector 1-5, the data is output to the external measuring unit in a gating way; the external measurement unit may comprise, among other things, an RC filter circuit 3 and an analog-to-digital converter ADC 4.
Step S3: the signal is converted into a direct current level through an RC filter circuit 3, and digital signal conversion is completed at an analog-digital converter ADC 4; and obtaining the digital voltage corresponding to the TDR signal.
Step S4: and step S2, setting different threshold levels, and obtaining digital voltages corresponding to a plurality of groups of TDR signals of the current channel.
Step S5: obtaining a measurement result of the current channel according to the corresponding TDR signal measurement method;
Step S6: repeating the steps S1-S5, and measuring measurement signals of all channels;
step S7: and taking the measurement results of all channels which are more than or equal to each other as time delay parameters for synchronization, and inputting the time delay parameters for synchronization into the first programmable time delay unit and the second programmable time delay unit so as to perform time delay correction on measurement data in the follow-up normal measurement.
Example 1
In the embodiment of the invention, the key point of the technical scheme is that the TDR signal measuring method is specifically described as follows:
Referring to fig. 3, fig. 3 is a schematic diagram illustrating an analog measurement method based on the digital TDR technology according to an embodiment of the invention. As shown in fig. 3, which depicts the desired threshold position, signal decision schematic, and time domain relationship of the decision signal during TDR signal measurement.
The TDR signal measuring method is specifically implemented as follows:
Step S21: the PWM generator 1-1 continuously transmits a square wave signal S0 having a period T0, wherein the square wave signal S0 has a high level width Th.
Step S22: the square wave signal S0 is sent by a pin driver PE 2 and reaches a DUT pin end of the connector through a selected test channel, and as the DUT pin end is suspended, R is in an infinite state to form a TDR reflected signal, and a source signal is overlapped with the TDR reflected signal to form a signal S1;
step S23: the signal S1 is passed through the comparison unit CMP of the pin driver PE 2 to form a signal S2, and the signal S2 generates different determination results according to different comparison thresholds.
As shown in fig. 3, the signal generated by the comparison threshold a is recorded as S2a, the high level time is Ta, the signal generated by the comparison threshold b is recorded as S2b, and the high level time is Tb. The time difference between the two thresholds is defined as Tv:
Tv＝(Ta-Tb)/2
wherein Tv comprises two part times, one is the channel delay Tdly and the other is the voltage rise time.
Step S24: and (3) eliminating the influence of the voltage rise time by adopting a method for judging a plurality of threshold positions, and obtaining accurate channel delay Tdly.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a multi-threshold decision implementation flow in an embodiment of the invention.
As shown in fig. 4, the flow of the multi-threshold determination includes:
Step S241: the pin driver PE 2 uses 1/6 and 5/6 level thresholds respectively, the comparison threshold a is 1/6, and the comparison threshold b is 5/6; obtaining a threshold time difference Tv2 according to the method of the step S23;
step S242: the pin driver PE 2 uses 2/6 and 4/6 level threshold values respectively, the comparison threshold a is 2/6, and the comparison threshold b is 4/6; the threshold time difference Tv1 is obtained in accordance with the method of step S23.
As shown in fig. 4, by theoretical analysis, it is possible to obtain:
step S243: assume that the voltage rise time set by using the 1/6-5/6 level threshold and the 2/6-4/6 level threshold is the same, and the voltage rise time set by using the 3/6-4/6 level threshold and the 4/6-5/6 level threshold is the same; tdly can be calculated using the following method:
Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
thereby, an accurate channel measurement signal can be obtained. Note that Tdly should be 2 times the actual path delay since the TDR signal is superimposed by the reflected signal.
It should be noted that, in the above test procedure, the signal S2 is calculated based on the time parameter, and in step S23, the voltage value, not the time value, is actually obtained by the analog-digital converter ADC4 after the signal S2 passes through the external RC filter circuit (low-pass filter). Therefore, it is necessary to obtain the time/voltage coefficient of each channel, defined as k, in units of (ps/mv) through time/voltage conversion verification.
It is clear to a person skilled in the art that the voltage value is always error-prone during the measurement of the analog-to-digital converter ADC 4. In particular, signals sent by common pins of the FPGA1 module, in the test process, the technical scheme of the invention does not need to calibrate the high-level amplitude of the signals in practice, and only needs to obtain an accurate voltage-time relationship.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a time/voltage coefficient verification principle according to an embodiment of the invention. The implementation method for verifying the time/voltage coefficient is described by a certain channel in the N channels as follows:
step S251: setting a period of the check pattern as T0, and setting a decision threshold as a 5/6 level threshold;
Step S252: setting the high level time as Th, and measuring the voltage value as V1 by the ADC 4;
Step S253: resetting the high level time to be Th+delta T, and measuring the voltage value to be V2 by the ADC 4;
Step S254: analysis results in ΔT corresponding to ΔV= (V2-V1), so ΔT/ΔV yields a coefficient k (ps/mv), i.e., a time/voltage coefficient.
It should be noted that the time/voltage coefficient calibration needs to be based on one precondition: increasing Δt only changes the high-low level duty ratio and does not affect the rising and falling edges, so it is necessary to ensure that the rising and falling process is complete before and after the increase, i.e., enough rising and falling time is reserved. Also, it should be noted that the time/voltage coefficient calibration coefficients are only applicable to the current T0.
Next, after the time/voltage coefficient k is obtained, the voltage amount measured by the analog-to-digital converter ADC4 may be converted into the amount of time. The measurement signals Tdly of the N channels may be obtained according to the method used in step S4, respectively.
In the practical application process, in order to ensure the best accuracy, a large-range rough measurement is generally performed first, and then accurate measurement is performed according to the estimated measurement result.
Example 2
In the following, a preferred embodiment of the implementation method of the low-cost digital TDR technology using analog measurement according to the present invention is described, and the description is performed by using a channel, and the details are not repeated. In addition, in the practical application process, in order to ensure the best accuracy, a large-range rough measurement is generally performed first, and then accurate measurement is performed according to the estimated measurement result.
Specifically, the analog measurement method based on the digital TDR technology comprises the following specific implementation steps:
First, the wide range thick side. As shown in fig. 2, assuming that there are N channels (32 channels, 0 to 31 in the drawing), in measuring and calculating delay information of the N channels, the measurement channel tdr_en is set to 1 for each channel, and the TDR test pattern is gated. For example, setting TDR_DC_SEL to 0 is a test performed on strobe channel 0.
As shown in fig. 3, an N-way PWM generator 1-1 is configured, and t0=100ns and th=50ns are set; the pin driver PE 2 is configured, the decision level of the threshold a is set to be 1/6 x 3.3V (assuming that the high level of the PE output signal is 3.3V), the ADC measurement voltage is 1.848V (assuming that the high level of the pin output of the FPGA is also 3.3V), and the duty ratio of the calculated signal is 1.848/3.3=0.56.
That is, the high level time is 100×0.56=56 ns, and the high level time of the signal S2a can be roughly considered as 50ns+2×tdly, so that tdly=3 ns is roughly calculated, and an accurate measurement model of t0=20 ns can be used.
Second, the enable signal tdr_en is set to 0, and the transmission of the TDR test pattern is turned off. Modifying the PWM generator configuration, t0=20ns, th=10ns; the enable signal tdr_en is reset to 1 and the subsequent measurement is continued.
Thirdly, coefficient verification is performed, as shown in fig. 5, t0=20ns, th=10ns is measured, and the voltage V1 is measured by the adc. Step 2 is repeated, t0=20ns, th=15ns is set, and the analog-digital converter ADC4 measures the voltage V2. The calculation can obtain the time/voltage coefficient:
k=5×1000/(V2-V1) 1000=5/(V2-V1), the unit is ps/mv.
Fourth, repeating the second step, setting t0=20ns, th=10ns, and starting accurate measurement.
Fifth, as shown in fig. 3, a pin driver PE is configured to set a decision level of the decision threshold a to 1/6×3.3v, and the ADC measures the voltage Va. The pin driver PE is reconfigured, the decision level of the threshold b is set to be 5/6 x 3.3V, the measurement voltage of the ADC is set to be Vb, and the measurement voltage difference between two threshold signals is calculated to be Vab2= (Va-Vb)/2.
Sixth, repeating the fifth step, setting the decision level of the decision threshold a to be 2/6×3.3v, setting the decision level of the decision threshold b to be 4/6×3.3v, and calculating the measurement voltage difference between two signals with the decision threshold being set as Vab1.
Seventh, tdly=2×tv1-Tv2 as shown in fig. 3. Combining the coefficients k, tdly= (2 x Vab1-Vab 2) x 1000 x k can be calculated in ps. Thus, a twice delay parameter of channel 0, tdly/2, is obtained as the desired channel measurement.
Eighth, as shown in fig. 2, the tdr_dc_sel is set to 1 to 31, other test channels are gated, and the measurement results of N channels can be obtained by repeating the above first to seventh steps.
After the measurement signals of all the channels are tested, synchronous calibration is carried out on all the channels by combining the channel delay compensation technology, so that the time synchronization precision of pins can be effectively improved, and the accuracy of the subsequent test process is ensured.
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the present invention described in the specification and the drawings are included in the scope of the invention.
Claims (7)
1. An analog measuring device based on a digital TDR technology is used for measuring and calculating delay information of N paths of channels and carrying out delay correction on measured data during formal measurement; the device is characterized by comprising an FPGA module (1), N pin drivers PE (2) corresponding to the N paths of channels, an RC filter circuit (3) and an analog-digital converter ADC (4); wherein,
The FPGA module (1) is used for realizing the transmission, the reception and the data path selection of the N-channel test signals; the device comprises an N-path PWM generator (1-1), an N-path transmission signal selector (1-2), an N-path data transmission path (1-3), an N-path data receiving path (1-4) and a data path selector (1-5);
the PWM generator (1-1) is used for generating a TDR test pattern of each channel; the transmit signal selector (1-2) of each channel selects either a transmit normal test pattern or a TDR test pattern by enabling signal tdr_en;
The data transmission path (1-3) of each channel comprises a first programmable delay unit and a transmission logic resource unit, wherein the first programmable delay unit is used for carrying out delay synchronization on a normal test pattern of the channel during normal test, and the transmission logic resource unit is used for transmitting the TDR test pattern or the normal test pattern to a pin driver PE (2); wherein, the initialization value of the first programmable delay unit is 0;
Each pin driver PE (2) is used for carrying out port level conversion on the TDR test pattern of the corresponding channel, and different level thresholds are configured according to a level threshold judging rule; the pin driver PE (2) comprises a receiving channel end cmpl, a transmitting channel end data and a testing bidirectional channel end;
The data receiving path (1-4) of each channel comprises a receiving logic resource unit and a second programmable delay unit, wherein the logic resource unit is used for receiving the measurement signals of the corresponding channel input by the pin driver PE (2), and the second programmable delay unit is used for carrying out delay synchronization on the measurement signals of the corresponding channel; the second programmable delay is used for carrying out delay synchronization on the normally received test data of the channel during normal test;
the data path selector (1-5) gates one of the N paths by selecting a signal TDR_DC_SEL, and transmits the measured TDR signal to an external measuring unit;
the RC filter circuit (3) carries out low-pass filtering on the TDR signal after judgment and selection and converts the duty ratio signal into an analog quantity signal of direct current voltage;
The analog-digital converter ADC (4) is used for carrying out analog-digital conversion on the analog quantity signal of the direct current voltage after the filtering of the RC filter circuit (3) to obtain a digitized voltage value, generating judgment results of different duty ratios on the TDR reflection signal of the TDR test pattern, and matching with time/voltage coefficients to obtain a measurement signal of a corresponding channel.
2. Analog measurement device based on digital TDR technology according to claim 1, characterized in that the FPGA module (1) further comprises a parameter configuration unit PWM configuring the PWM generator (1-1) continuous step signal period parameters, validating the period and duty cycle of the TDR test pattern, and setting the threshold level of the pin driver PE (2).
3. A measurement method using the digital TDR technology based analog measurement device of claim 1, comprising a measurement signal generation step for measuring and calculating delay information of N channels and a test step for performing delay correction on measurement data at the time of formal measurement, the delay information generation step comprising:
Step S1: configuring parameters of an internal module of the FPGA (1), including setting parameters of a PWM generator (1-1), and confirming the period and the duty ratio of a TDR test pattern; setting a transmission signal selector (1-2), setting TDR_EN of the test channel to 1, and gating the TDR test pattern; setting a data path selector (1-5) for selecting a desired test channel by TDR_DC_SEL;
Step S2: setting a threshold level of a pin driver PE (2), judging a received TDR signal, and transmitting a TDR signal result fed back by a connector to a data receiving channel (1-4) of the FPGA module 1 through a pin of the pin driver PE (2); then through the data path selector (1-5), the data is output to the external measuring unit in a gating way; the external measuring unit comprises an RC filter circuit (3) and an analog-digital converter ADC (4);
step S3: the signal is converted into a direct current level through an RC filter circuit (3), and digital signal conversion is completed at an analog-digital converter ADC (4); obtaining digital voltage corresponding to the TDR signal;
step S4: repeating the step S2, setting different threshold levels, and obtaining digital voltages corresponding to a plurality of groups of TDR signals of the current channel;
step S5: obtaining a measurement result of the current channel according to the corresponding TDR signal measurement method;
Step S6: repeating the steps S1-S5, and measuring measurement signals of all channels;
step S7: and taking the measurement results of all channels which are more than or equal to each other as time delay parameters for synchronization, and inputting the time delay parameters for synchronization into the first programmable time delay unit and the second programmable time delay unit so as to perform time delay correction on measurement data in the follow-up normal measurement.
4. The analog measurement method based on digital TDR technology according to claim 3, wherein the step S2 specifically comprises:
Step S21: the PWM generator (1-1) continuously transmits a square wave signal S0 with a period of T0, wherein the high level width of the square wave signal S0 is Th;
Step S22: the square wave signal S0 is sent by a pin driver PE (2) and reaches a DUT pin end through a selected test channel, and as the DUT pin end is suspended, R is in an infinite state to form a TDR reflected signal, and a source signal is overlapped with the TDR reflected signal to form a signal S1;
Step S23: the signal S1 is subjected to a process of performing multi-threshold judgment by a pin driver PE (2) to form a signal S2, and the signal S2 generates a time difference Tv between two thresholds according to different comparison thresholds; wherein Tv comprises two parts of time, one is the channel delay Tdly and the other is the voltage rise time;
step S24: and (3) eliminating the influence of the voltage rise time by adopting a method for judging a plurality of threshold positions, and obtaining accurate channel delay Tdly.
5. The analog measurement method based on digital TDR technology according to claim 4, wherein the flow of the multi-threshold decision specifically includes:
step S241: the pin driver PE (2) uses 1/6 and 5/6 level thresholds respectively, the comparison threshold a is 1/6, and the comparison threshold b is 5/6; obtaining a threshold time difference Tv2 according to the method of the step S23;
step S242: the pin driver PE (2) uses 2/6 and 4/6 level thresholds respectively, the comparison threshold a is 2/6, and the comparison threshold b is 4/6; obtaining a threshold time difference Tv1 according to the method of the step S23;
Step S243: setting the voltage rising time which is the same with the 1/6-5/6 level threshold and the 2/6-4/6 level threshold and the voltage rising time which is the same with the 3/6-4/6 level threshold and the 4/6-5/6 level threshold; tdly can be calculated using the following method:
Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
6. the method for analog measurement based on digital TDR technology according to claim 4, wherein the step S24 further comprises the step S25 of: and sequentially checking the time/voltage coefficient of each channel in the N channels.
7. The analog measurement method based on digital TDR technology according to claim 6, wherein the step S25 specifically includes:
Step S251: setting a period of the check pattern as T0, and setting a decision threshold as one of 1/6, 2/6, 3/6, 4/6 and 5/6 level thresholds;
step S252: setting the high level time as Th, and measuring the voltage value as V1 by an analog-digital converter ADC (4);
step S253: resetting the high level time to be Th+delta T, and measuring the voltage value to be V2 by an analog-digital converter ADC (4);
Step S254: analysis results in ΔT corresponding to ΔV= (V2-V1), so ΔT/ΔV yields a coefficient k (ps/mv), i.e., a time/voltage coefficient.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111373933.1A CN114167256B (en) | 2021-11-19 | 2021-11-19 | Analog measurement device and method based on digital TDR technology |
| PCT/CN2021/143606 WO2023087510A1 (en) | 2021-11-19 | 2021-12-31 | Analog measurement apparatus and measurement method based on digital tdr technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111373933.1A CN114167256B (en) | 2021-11-19 | 2021-11-19 | Analog measurement device and method based on digital TDR technology |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114167256A CN114167256A (en) | 2022-03-11 |
| CN114167256B true CN114167256B (en) | 2024-05-07 |
Family
ID=80479738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111373933.1A Active CN114167256B (en) | 2021-11-19 | 2021-11-19 | Analog measurement device and method based on digital TDR technology |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114167256B (en) |
| WO (1) | WO2023087510A1 (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5721933A (en) * | 1994-12-22 | 1998-02-24 | Texas Instruments Incorporated | Power management supply interface circuitry, systems and methods |
| US6622107B1 (en) * | 2000-08-25 | 2003-09-16 | Nptest Llc | Edge placement and jitter measurement for electronic elements |
| CN101460813A (en) * | 2005-03-31 | 2009-06-17 | 泰拉丁公司 | Calibrating automatic test equipment |
| CN104819685A (en) * | 2015-04-29 | 2015-08-05 | 长安大学 | Landslide monitoring device based on TDR technology and landslide monitoring method thereof |
| CN105842610A (en) * | 2016-03-31 | 2016-08-10 | 复旦大学 | FPGA circuit transmission delay rest system and method based on TDC |
| CN106103485A (en) * | 2014-01-24 | 2016-11-09 | 达纳-法伯癌症研究公司 | Antibody molecule of PD 1 and application thereof |
| CN107003336A (en) * | 2014-12-19 | 2017-08-01 | 泰拉丁公司 | Control is per pin measuring unit |
| CN110708047A (en) * | 2019-08-29 | 2020-01-17 | 上海御渡半导体科技有限公司 | Structure and method for measuring precision of high-speed comparator based on TDC chip |
| TW202102869A (en) * | 2019-04-16 | 2021-01-16 | 美商塞雷特有限責任公司 | Device interface board compliance testing using impedance response profiling |
| CN112260890A (en) * | 2020-09-28 | 2021-01-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital array time delay measuring method |
| CN113128148A (en) * | 2021-04-15 | 2021-07-16 | 杭州加速科技有限公司 | Trigger signal synchronization system and method based on delay chain and semiconductor test equipment |
| CN113466670A (en) * | 2021-09-03 | 2021-10-01 | 绅克半导体科技(苏州)有限公司 | Time delay measuring circuit, AC calibration device and IC measuring device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7138820B2 (en) * | 2004-04-30 | 2006-11-21 | Xilinx, Inc. | System monitor in a programmable logic device |
| CN101783665B (en) * | 2009-12-31 | 2012-11-21 | 广东正业科技股份有限公司 | Programmable stepping time-delay time base and sampling system |
| US8390300B2 (en) * | 2010-01-29 | 2013-03-05 | Teledyne Lecroy, Inc. | Time domain reflectometry in a coherent interleaved sampling timebase |
| CN107576890A (en) * | 2017-08-18 | 2018-01-12 | 北京睿信丰科技有限公司 | A kind of time domain distance-finding method and device |
| CN110060556A (en) * | 2019-05-05 | 2019-07-26 | 朱世国 | Light velocity measurement experiment instructional device and measurement method in a kind of optical fiber |
| CN111934760B (en) * | 2020-08-14 | 2021-12-28 | 南方电网科学研究院有限责任公司 | Signal processing transmission delay characteristic detection device and method and terminal equipment |
| CN112180220B (en) * | 2020-08-31 | 2022-09-20 | 山东信通电子股份有限公司 | Time domain reflection signal data acquisition method and device |
-
2021
- 2021-11-19 CN CN202111373933.1A patent/CN114167256B/en active Active
- 2021-12-31 WO PCT/CN2021/143606 patent/WO2023087510A1/en unknown
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5721933A (en) * | 1994-12-22 | 1998-02-24 | Texas Instruments Incorporated | Power management supply interface circuitry, systems and methods |
| US6622107B1 (en) * | 2000-08-25 | 2003-09-16 | Nptest Llc | Edge placement and jitter measurement for electronic elements |
| CN101460813A (en) * | 2005-03-31 | 2009-06-17 | 泰拉丁公司 | Calibrating automatic test equipment |
| CN106103485A (en) * | 2014-01-24 | 2016-11-09 | 达纳-法伯癌症研究公司 | Antibody molecule of PD 1 and application thereof |
| CN107003336A (en) * | 2014-12-19 | 2017-08-01 | 泰拉丁公司 | Control is per pin measuring unit |
| CN104819685A (en) * | 2015-04-29 | 2015-08-05 | 长安大学 | Landslide monitoring device based on TDR technology and landslide monitoring method thereof |
| CN105842610A (en) * | 2016-03-31 | 2016-08-10 | 复旦大学 | FPGA circuit transmission delay rest system and method based on TDC |
| TW202102869A (en) * | 2019-04-16 | 2021-01-16 | 美商塞雷特有限責任公司 | Device interface board compliance testing using impedance response profiling |
| CN110708047A (en) * | 2019-08-29 | 2020-01-17 | 上海御渡半导体科技有限公司 | Structure and method for measuring precision of high-speed comparator based on TDC chip |
| CN112260890A (en) * | 2020-09-28 | 2021-01-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital array time delay measuring method |
| CN113128148A (en) * | 2021-04-15 | 2021-07-16 | 杭州加速科技有限公司 | Trigger signal synchronization system and method based on delay chain and semiconductor test equipment |
| CN113466670A (en) * | 2021-09-03 | 2021-10-01 | 绅克半导体科技(苏州)有限公司 | Time delay measuring circuit, AC calibration device and IC measuring device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114167256A (en) | 2022-03-11 |
| WO2023087510A1 (en) | 2023-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109324248B (en) | Integrated vector network analyzer for data domain analysis and testing method thereof | |
| JP5279724B2 (en) | Test apparatus and calibration method | |
| US6816987B1 (en) | Apparatus and method for built-in self-test of a data communications system | |
| CN109406884B (en) | Vector network analyzer with digital interface | |
| CN109407033B (en) | Calibration device of transient calibration instrument of direct current transformer | |
| JP2003098222A (en) | Board for inspection, inspection device and inspection method for semiconductor device | |
| CN110579753A (en) | depth sensor calibration system and method | |
| US20130151185A1 (en) | Semiconductor device | |
| KR101329594B1 (en) | Calibration device | |
| CN111555801A (en) | Optical signal sampling device and method for optical time domain reflectometer and optical time domain reflectometer | |
| TWI451108B (en) | Device and method for performing timing analysis | |
| CN114167256B (en) | Analog measurement device and method based on digital TDR technology | |
| JP2009042230A (en) | Testing device | |
| CN104536282A (en) | Time-digital converter and time measuring device and method | |
| US6931349B2 (en) | Jitter measuring system in high speed data output device and total jitter measuring method | |
| US7801205B2 (en) | Jitter injection circuit, electronics device, and test apparatus | |
| KR101123826B1 (en) | Testing apparatus and transmitting apparatus | |
| US6381722B1 (en) | Method and apparatus for testing high speed input paths | |
| CN209858719U (en) | Calibration device of transient calibration instrument of direct current transformer | |
| WO2007090467A1 (en) | Detecting a transmission behavior by sampling a reflection signal | |
| US10079701B1 (en) | Three-valued signal generation device and three-valued signal generation method | |
| CN111381104A (en) | Method and device for measuring impedance of transmission channel | |
| CN112306112A (en) | Rotary table/swing table with high-frequency angle measuring mechanism and angle measuring method | |
| US9083348B1 (en) | Method and apparatus for tuning delay | |
| CN111521925B (en) | System level test system and method for 4M 1553 bus transceiver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |