CN114162778A - Wafer-level packaging structure and preparation method thereof, and activation method of getter layer - Google Patents
Wafer-level packaging structure and preparation method thereof, and activation method of getter layer Download PDFInfo
- Publication number
- CN114162778A CN114162778A CN202111493790.8A CN202111493790A CN114162778A CN 114162778 A CN114162778 A CN 114162778A CN 202111493790 A CN202111493790 A CN 202111493790A CN 114162778 A CN114162778 A CN 114162778A
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer
- insulating layer
- getter
- deep cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0035—Packages or encapsulation for maintaining a controlled atmosphere inside of the chamber containing the MEMS
- B81B7/0038—Packages or encapsulation for maintaining a controlled atmosphere inside of the chamber containing the MEMS using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00277—Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS
- B81C1/00285—Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Micromachines (AREA)
Abstract
The invention discloses a wafer-level packaging structure which comprises a first wafer and a second wafer, wherein the second wafer is fixedly connected with the first wafer through a bonding layer, a cavity for accommodating an MEMS is formed, a bulge is arranged on the bottom surface of the first wafer, so that a deep cavity structure is formed on the bottom surface of the first wafer, the bulge and the deep cavity structure are in transition connection through an inclined side edge, metal activation layers are arranged in the bulge, the inclined side edge and the deep cavity structure, the metal activation layers are arranged in the deep cavity structure in a discontinuous mode, and a getter layer, a first insulating layer and a second insulating layer are arranged on the metal activation layers at intervals. The bonding layer is positioned on the first insulating layer, so that the getter layer is positioned in the cavity, the active electrode can be arranged between the first insulating layer and the second insulating layer, the getter layer is electrically activated through conduction of the metal active layer, and adverse effects of a traditional thermal activation mode on a wafer device are avoided.
Description
Technical Field
The invention relates to the technical field of MEMS (micro-electromechanical systems) devices, in particular to a wafer-level packaging structure, a preparation method thereof and an activation method of a getter layer.
Background
With the continuous progress of science and technology and the continuous development of society in recent years, the MEMS (micro electro mechanical system) is greatly developed and correspondingly, the MEMS sensor is also greatly developed and is widely applied to the fields of automobiles, security, biomedicine, electric power, intelligent buildings, forest fire prevention, smart phones, Internet of things and the like.
At present, a wafer level Package technology is generally adopted in the manufacturing of the MEMS sensor, and Wafer Level Package (WLP) is an advanced packaging technology for completing packaging and testing on a silicon wafer by processes such as thin film, photolithography, electroplating, dry-wet etching and the like according to a process similar to that of a front stage of a semiconductor, and finally cutting to manufacture a single packaged finished product. Compared with the traditional metal package or ceramic package, the wafer level package can greatly reduce the size of the packaged device, and meets the requirement of miniaturization chips in mobile equipment at present. Meanwhile, a metal or ceramic tube shell is not needed, and the cost of the device can be effectively reduced. The wafer level vacuum packaging technology is mainly characterized in that after a certain semiconductor process is carried out on a device layer wafer and a cap layer wafer, a bonding packaging process is carried out in a high vacuum closed cavity, and a high vacuum and high tightness cavity structure is formed after packaging. However, after the bonding package is completed, the vacuum degree inside the device is usually reduced due to a certain degree of vacuum leakage and residual gas on the original cavity wall, and the vacuum state inside the device is generally maintained by depositing a thin film getter inside the device.
However, in the prior art, the getter is activated by thermal activation, which easily has a large thermal influence on a sensitive device chip: excessive temperatures may degrade the performance of the device chip; and too low a temperature may not activate the getter completely, thereby affecting the degree of vacuum. Therefore, how to avoid the influence on the sensor structure when the getter is activated is an urgent problem to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a wafer-level packaging structure, a preparation method thereof and an activation method of a getter.
The invention provides a wafer-level packaging structure, which comprises a first wafer and a second wafer, wherein the bottom surface of the first wafer is provided with a bulge so as to form a deep cavity structure on the bottom surface of the first wafer, the bulge is in transitional connection with the deep cavity structure through an inclined side edge, the inclined side edge inclines from top to bottom and inclines from an inner ring to an outer ring, a metal activation layer extending to the inclined side edge and the bulge is paved in the deep cavity structure, the metal activation layer is discontinuously arranged in the deep cavity structure, a first insulating layer, a second insulating layer and a getter layer are arranged on the metal activation layer, the first insulating layer and the second insulating layer are positioned on the bulge, a bonding layer is arranged on the first insulating layer, the first wafer and the second wafer are fixedly connected through the bonding layer and form a cavity, and the getter layer is positioned in the cavity, the second insulating layer is located outside the cavity, and the first insulating layer and the second insulating layer are arranged at intervals.
Further, the acute included angle between the inclined side edge and the deep cavity structure is within the range of 30-60 degrees.
Further, the thickness of the metal activation layer is set between 200nm and 2000 nm.
Further, the thickness of the first insulating layer and the second insulating layer is between 0.2 μm and 2 μm.
The invention also provides a preparation method of the wafer level packaging structure, which comprises the following steps:
s1: taking an SOI silicon chip containing a silicon supporting layer and a silicon dioxide oxidation layer positioned in the silicon supporting layer as a first wafer, cleaning the SOI silicon chip, and plating a thin film protective layer on the top surface and the bottom surface of the SOI silicon chip;
s2: etching the central area of the bottom surface of the SOI silicon chip until the silicon dioxide oxide layer is etched, so as to form bulges on the outer edges of two sides of the bottom surface of the SOI silicon chip and form a trapezoidal deep cavity structure in the central area of the SOI silicon chip;
s3: removing the silicon dioxide oxide layer in the deep cavity structure by adopting a wet etching process, and etching and removing the thin film protective layers on the top surface and the bottom surface of the SOI silicon wafer;
s4: plating a metal active layer on the bottom surface of the SOI silicon chip, and performing a patterning process to etch the metal active layer at the central position of the deep cavity structure;
s5: plating an insulating layer on the metal activation layer, performing a patterning process, etching the insulating layer in the deep cavity structure, and partially etching the insulating layer outside the deep cavity structure to form a first insulating layer and a second insulating layer, so that pad points are formed between the first insulating layer and the second insulating layer;
s6: evaporating a getter layer on the metal activation layer in the deep cavity structure;
s7: and bonding the first insulating layer and the second wafer together by welding.
Further, the thin film getter has an alloy structure consisting of Zr, Co, Re and Zn metals.
Further, the thin film protective layer comprises a SiNx protective layer with the thickness of 100nm-300nm and a Ti and/or Pt protective layer with the thickness of 50nm-200 nm.
Further, the first insulating layer and the second insulating layer are any one of a SiNx insulating layer and a SiO2 insulating layer.
Further, the metal active layer is any one of an Al active layer, a Ti active layer and an Au active layer.
The invention also provides an activation method of the getter layer of the wafer-level packaging structure, wherein an activation electrode is arranged between the first insulating layer and the second insulating layer, and the getter layer is electrically activated by the current of the activation electrode; or, the wafer-level packaging structure is placed in a high-temperature environment, and the getter layer is activated in a thermal activation mode.
In a first aspect, an embodiment of the present invention provides a wafer level package structure, where a protrusion is disposed on a bottom surface of a first wafer, so that the bottom surface of the first wafer forms a deep cavity structure, a metal active layer is laid on the deep cavity structure, an inclined side edge, and the protrusion, the metal active layer is discontinuously disposed in the deep cavity structure, and a first insulating layer and a second insulating layer are disposed on the metal active layer at intervals, and the bonding layer is disposed on the first insulating layer to be fixedly connected to a second wafer, a vacuum cavity is formed between the first wafer and the second wafer, where the second insulating layer is located outside the cavity, and a getter layer is disposed on the metal active layer and located in the cavity. When the getter layer needs to be activated to adsorb air in the cavity, the positive and negative activated electrodes are arranged between the first insulating layer and the second insulating layer, current is transmitted to the getter layer through the metal activated layer, electric energy is converted into heat energy when the current flows through the getter layer so as to activate the getter, namely, the getter can be specifically and only heated through the activated electrodes so as to be activated, so that adverse effects on the structure of a wafer device caused by a traditional thermal activation mode are avoided; and the getter can be activated for multiple times by arranging the activation electrode so as to ensure the vacuum degree in the MEMS sensor.
In a second aspect of the present invention, a method for manufacturing the wafer level package structure is provided, in which a metal active layer is buried inside a cavity on a surface of a first wafer (i.e., a cap wafer) by using techniques such as metal film deposition, insulating layer deposition, and photolithography. The structure design and the process flow of the electro-activation process are simplified, the stability and the reliability of the process are improved, and the process sequence, the cost and the process period are reduced; the process has good compatibility, does not have the process problems of getter pollution, large parasitic capacitance and the like, and ensures that the device has the effects of two activation modes of electric activation and thermal activation at the same time; in addition, the insulating layer structure is subjected to a patterning process to form a complete electric activation path, and the metal activation layer also contributes to the deposition adsorption of the getter and increases the adhesion of the getter to the first wafer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a wafer level package structure according to an embodiment of the invention;
fig. 2 is a flowchart of a method for fabricating the wafer level package structure of fig. 1.
1-first wafer, 2-second wafer, 3-metal active layer, 4-first insulating layer, 5-second insulating layer, 6-getter layer, 7-bonding layer, 8-cavity, 9-bump, 10-inclined side edge.
Detailed Description
The embodiment of the invention provides a wafer-level packaging structure, a preparation method thereof and an activation method of a getter, so that the wafer-level packaging structure has two modes of electric activation and thermal activation; the preparation process has the advantages of good compatibility, simple getter activation mode, low cost, stable performance and the like.
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention designs a wafer cap buried type packaging structure which can adopt two activation modes of electric activation and thermal activation, and solves the problems that the electric activation of a device layer has influence on the wiring of the whole device wafer, the process is incompatible and the like. The method is characterized in that a trapezoidal slope structure is formed by processes of customized silicon wafer dry etching, customized silicon wafer wet etching and the like, a metal film is used as a deposition substrate of a getter and an electrically activated lead, an efficient and stable wafer-level vacuum packaging structure and a getter activation method are formed by protection of an insulating layer, and long-term stable work of a high-vacuum electronic device is guaranteed.
Referring to fig. 1, fig. 1 is a wafer level package structure according to an embodiment of the present invention, including a first wafer 1 and a second wafer 2 fixed to the first wafer 1, wherein a bottom surface of the first wafer 1 is provided with a protrusion 9, the protrusion 9 enables the bottom surface of the first wafer 1 to form a deep cavity structure, the protrusion 9 and the deep cavity structure are in inclined transition connection through an inclined side edge 10, and the inclined side edge 10 is arranged from top to bottom and inclined from an inner ring to an outer ring. In the present embodiment, the metal active layer 3 is disposed on the bottom surface of the protrusion 9, the inclined side edge 10, and a part of the surface of the deep cavity structure, that is, the metal active layer 3 is disposed within the deep cavity structure at an interval, wherein the first insulating layer 4 and the second insulating layer 5 are disposed on the metal active layer 3 on the bottom surface of the protrusion 9, and the bonding layer 7 is disposed on the first insulating layer 4, and the first wafer 1 and the second wafer 2 are bonded and fixed together through the bonding layer 7. Furthermore, the first wafer 1 and the second wafer 2 are bonded and fixed together by a soldering method, that is, the bonding layer 7 is a solder layer containing tin, and the bonding and fixing method is simple and easy to operate.
When the getter layer 6 needs to be activated, an electrode is placed in a gap between the first insulating layer 4 and the second insulating layer 5, and current is guided to the getter layer 6 through a circuit formed by the metal activation layer 3, so that the getter layer 6 is electrically heated, and the getter is activated to ensure the vacuum property in the cavity 8. The structure can increase the activation times and maintain the stable high vacuum degree in the device, thereby prolonging the stable excellent performance and the service life of the device under the high vacuum condition. Of course, the wafer level package structure of the present invention may also be heated at a high temperature to thermally activate the getter, so that the wafer level package structure has the effects of two activation modes, i.e., electrical activation and thermal activation.
Wherein, the acute included angle between the inclined side edge 10 and the top surface of the deep cavity structure is within the range of 30-60 degrees, if the acute included angle between the inclined side edge 10 and the top surface of the deep cavity structure is less than 30 degrees, after the first wafer 1 and the second wafer 2 are bonded and fixed together, the height of the formed cavity 8 is low, which is not beneficial to the placement of the MEMS sensor; if the acute angle between the inclined side edge 10 and the top surface of the deep cavity structure is greater than 60 °, the inclined side edge 10 is too steep, which is not favorable for the integrity of the circuit formed by the metal active layer 3. In order to ensure that the metal active layer 3 can form a complete electric active path, the thickness of the metal active layer 3 is between 200nm and 2000 nm; in order to protect the metal active layer 3 exposed to the external environment, the first insulating layer 4 and the second insulating layer 5 have a thickness of 0.2 μm to 2 μm. In the embodiment, the inclined side edge 10 forms an acute angle of 54.7 ° with the bottom surface of the first wafer 1.
As shown in fig. 2, which is a flowchart of a method for manufacturing a wafer level package structure, the present invention further provides an embodiment of a method for manufacturing the wafer level package structure, which includes the following steps:
s1: cleaning a customized SOI silicon chip serving as a first wafer (the SOI silicon chip comprises a silicon supporting layer and a silicon dioxide oxidation layer, wherein the silicon dioxide oxidation layer is positioned in the silicon supporting layer, the thickness of the silicon supporting layer is 500 mu m, and the thickness of the silicon dioxide oxidation layer is 1 mu m), and plating a thin film protective layer on the top surface and the bottom surface of the SOI silicon chip, wherein the thin film protective layer comprises a SiNx protective layer with the thickness of 100nm-300nm and a Ti and/or Pt protective layer with the thickness of 50nm-200 nm;
s2: photoetching and patterning the central area of the bottom surface of the SOI silicon wafer, exposing a thin film protective layer to be dry-etched, removing the thin film protective layer, carrying out a wet etching process on the SOI silicon wafer by using any one solution of KOH, TMAH and NaOH with the concentration of 1-80 wt%, and etching until a silicon dioxide oxide layer is automatically finished to form a trapezoidal deep cavity structure;
s3: cleaning an SOI silicon chip, soaking the silicon chip in HF solution with the concentration of 1% -49% for 10-120s to remove a silicon dioxide oxidation layer in a deep cavity structure, coating photoresist in the trapezoidal deep cavity structure by using a glue spraying process to serve as a protective layer, etching and removing a thin film protective layer on the SOI silicon chip, and removing the photoresist protective layer in the deep cavity structure;
s4: sputtering or evaporating any one of an Al active layer, a Ti active layer and an Au active layer with the thickness of 200nm-2000nm on the bottom surface of the SOI silicon wafer as a metal active layer by using a glue spraying process, removing the metal active layer at the central position in the deep cavity structure by using a lift off stripping process, and cleaning the SOI silicon wafer after the stripping process is finished;
s5: depositing and growing an insulating layer with the thickness of 0.2-2 mu m on the metal active layer, wherein the insulating layer is any one of a SiNx insulating layer and a SiO2 insulating layer, then carrying out patterning process on the insulating layer, etching off the insulating layer in the deep cavity structure, and partially etching the insulating layer outside the deep cavity structure to form a first insulating layer and a second insulating layer which are spaced, and forming an electrically active pad point between the first insulating layer and the second insulating layer;
s6: coating a getter layer on the bottom surface of the SOI silicon wafer by adopting a film evaporation process of glue spraying, exposure, development and coating, removing part of the getter layer by utilizing a photoetching stripping process, and only leaving the getter layer on the metal activation layer in the deep cavity structure;
s7: and welding and fixing the first insulating layer and the second wafer together through a tin-containing bonding layer to form the high-vacuum stable wafer-level packaging structure.
Specifically, the getter layer is generally an alloy structure composed of several metals such as Zr, Co, Re, Zn, etc. by disposing the getter layer on the metal active layer, the later electrical activation process is facilitated. In the preparation method, the deep cavity structure with the trapezoid structure is arranged on the lower surface of the SOI silicon wafer, that is, the protrusions 9 and the inclined side edges 10 are formed on the outer edges of the two sides of the bottom surface of the first wafer 1, and the inclined side edges 10 have a certain angle design, so that the metal active layer in the step S4 can completely cover the inclined side edges 10 to form a complete electrical path.
The invention also comprises an activation method of the getter in the wafer level packaging structure, which comprises the following steps: according to the wafer-level packaging structure obtained by the preparation method, the active electrode is arranged at the pad point, the active electrode is electrified, current flows to the getter layer along the metal active layer, and the getter layer is heated by the current so as to activate the getter layer.
The method for activating the getter of the wafer level packaging structure in another embodiment of the invention comprises the following steps: and (3) placing the wafer-level packaging structure obtained by the preparation method in a high-temperature environment, and activating the getter layer by a thermal activation method.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A wafer level packaging structure is characterized by comprising a first wafer and a second wafer, wherein a protrusion is arranged on the bottom surface of the first wafer, so that a deep cavity structure is formed on the bottom surface of the first wafer, the protrusion is in transitional connection with the deep cavity structure through an inclined side edge, the inclined side edge inclines from top to bottom and from an inner ring to an outer ring, a metal activation layer extending to the inclined side edge and the protrusion is laid in the deep cavity structure, the metal activation layer is discontinuously arranged in the deep cavity structure, a first insulation layer, a second insulation layer and a getter layer are arranged on the metal activation layer, the first insulation layer and the second insulation layer are located on the protrusion, a bonding layer is arranged on the first insulation layer, the first wafer and the second wafer are fixedly connected through the bonding layer and form a cavity, and the getter layer is located in the cavity, the second insulating layer is located outside the cavity, and the first insulating layer and the second insulating layer are arranged at intervals.
2. The wafer level package structure of claim 1, wherein the inclined side edge forms an acute angle with the deep cavity structure in a range of 30-60 °.
3. The wafer-level package structure of claim 1, wherein the thickness of the metal active layer is set between 200nm-2000 nm.
4. The wafer-level package structure of claim 1, wherein the thickness of the first and second insulating layers is between 0.2 μm and 2 μm.
5. A method for preparing a wafer level package structure as claimed in claims 1 to 4, comprising the steps of:
s1: taking an SOI silicon chip containing a silicon supporting layer and a silicon dioxide oxidation layer positioned in the silicon supporting layer as a first wafer, cleaning the SOI silicon chip, and plating a thin film protective layer on the top surface and the bottom surface of the SOI silicon chip;
s2: etching the central area of the bottom surface of the SOI silicon chip until the silicon dioxide oxide layer is etched, so as to form a bulge on the bottom surface of the SOI silicon chip and form a trapezoidal deep cavity structure in the central area of the SOI silicon chip;
s3: removing the silicon dioxide oxide layer in the deep cavity structure by adopting a wet etching process, and etching and removing the thin film protective layers on the top surface and the bottom surface of the SOI silicon wafer;
s4: plating a metal active layer on the bottom surface of the SOI silicon chip, and performing a patterning process to etch the metal active layer at the central position of the deep cavity structure;
s5: plating an insulating layer on the metal activation layer, performing a patterning process, etching the insulating layer in the deep cavity structure, and partially etching the insulating layer outside the deep cavity structure to form a first insulating layer and a second insulating layer, so that pad points are formed between the first insulating layer and the second insulating layer;
s6: evaporating a getter layer on the metal activation layer in the deep cavity structure;
s7: and bonding the first insulating layer and the second wafer together by welding.
6. The method for manufacturing the wafer level packaging structure according to claim 5, wherein the thin film getter is an alloy structure composed of Zr, Co, Re and Zn metals.
7. The method for manufacturing the wafer level packaging structure of claim 5, wherein the thin film protection layer comprises a SiNx protection layer with a thickness of 100nm-300nm, and a Ti and/or Pt protection layer with a thickness of 50nm-200 nm.
8. The method for manufacturing a wafer level package structure as claimed in claim 5, wherein the first and second insulating layers are any one of SiNx insulating layers and SiO2 insulating layers.
9. The method for manufacturing a wafer-level package structure according to claim 5, wherein the metal active layer is any one of an Al active layer, a Ti active layer and an Au active layer.
10. An activation method for activating a getter layer of a wafer level package structure as claimed in claims 1 to 4, wherein an activation electrode is placed between the first and second insulating layers, the getter layer being electrically activated by an electric current of the activation electrode; or, the wafer-level packaging structure is placed in a high-temperature environment, and the getter layer is activated in a thermal activation mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111493790.8A CN114162778A (en) | 2021-12-08 | 2021-12-08 | Wafer-level packaging structure and preparation method thereof, and activation method of getter layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111493790.8A CN114162778A (en) | 2021-12-08 | 2021-12-08 | Wafer-level packaging structure and preparation method thereof, and activation method of getter layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114162778A true CN114162778A (en) | 2022-03-11 |
Family
ID=80484458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111493790.8A Pending CN114162778A (en) | 2021-12-08 | 2021-12-08 | Wafer-level packaging structure and preparation method thereof, and activation method of getter layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114162778A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024067713A1 (en) * | 2022-09-29 | 2024-04-04 | 杭州海康微影传感科技有限公司 | Wafer-level packaging structure, manufacturing method therefor, and sensor |
-
2021
- 2021-12-08 CN CN202111493790.8A patent/CN114162778A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024067713A1 (en) * | 2022-09-29 | 2024-04-04 | 杭州海康微影传感科技有限公司 | Wafer-level packaging structure, manufacturing method therefor, and sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9681234B2 (en) | MEMS microphone structure and method of manufacturing the same | |
| EP2727136B1 (en) | Process for a sealed mems device with a portion exposed to the environment | |
| US11101491B2 (en) | Semiconductor structures having a micro-battery and methods for making the same | |
| TW201106433A (en) | Microelectronic device, method for fabricating microelectronic device, and MEMS package and method for fabricating the same | |
| TW200845324A (en) | Electronic device packages and methods of formation | |
| US8525277B2 (en) | MEMS device | |
| JP2001244360A (en) | Semiconductor device and manufacturing method, therefor circuit board and electronic apparatus | |
| CN111170265A (en) | MEMS device and method of manufacturing the same | |
| TW201307183A (en) | Metal thin shield on electrical device | |
| JP2005327711A (en) | Acceleration switch | |
| CN114162778A (en) | Wafer-level packaging structure and preparation method thereof, and activation method of getter layer | |
| JP2007222956A (en) | Mems device and manufacturing method of mems device | |
| JP5417851B2 (en) | MEMS device and manufacturing method thereof | |
| TWI295081B (en) | Method for wafer level package and fabricating cap structures | |
| JP2009289838A (en) | Method of manufacturing sensor device | |
| JP2011083881A (en) | Manufacturing method for mems device, and mems device | |
| JP2010030020A (en) | Electronic device | |
| JP2009178778A (en) | Micro electromechanical device | |
| US7919842B2 (en) | Structure and method for sealing cavity of micro-electro-mechanical device | |
| US20160176705A1 (en) | Systems and methods for forming mems assemblies incorporating getters | |
| CN111170268A (en) | MEMS device and method of manufacturing the same | |
| CN109411549A (en) | Opto chip encapsulating structure and packaging method | |
| CN110902643A (en) | MEMS sensor and preparation method thereof | |
| TW201508930A (en) | Sensor and method of manufacturing the same | |
| TW201203510A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |