CN114140450A - Fusion defogging circuit based on parallel gray scale linear stretching and difference value guide filtering - Google Patents

Abstract

The invention discloses a fusion defogging circuit based on parallel gray scale linear stretching and difference value guide filtering, wherein an input RAM module stores image data and transmits the image data to a difference value module, a shift register array and a gray scale linear stretching module; the difference module converts the image data into channel difference image data, the shift register array shifts and registers the image data and the channel difference image data, the buffer caches the channel difference image data, the difference value is guided to the filtering module to smooth noise and protect edges to obtain mild image data, and the high-boost filtering module sharpens the mild image data to obtain sharpened image data; the parallel gray linear stretching module performs graying and linear stretching to obtain high-contrast image data; the fusion module fuses the sharpened image data and the high-contrast image data according to weight and transmits the defogged image data to the output RAM module. The invention can improve the performance of the fusion defogging accelerator, accelerate the processing speed and improve the defogging effect.

Description

Fusion defogging circuit based on parallel gray scale linear stretching and difference value guide filtering

Technical Field

The invention belongs to the technical field of video image defogging processing, and can be applied to video image defogging circuits based on a visual system, such as an automatic driving automobile, an intelligent monitoring system, aviation survey and the like.

Background

Computer vision applications have covered aspects of life, and multimedia has become an important way for people to obtain and share information. Cameras of various mobile devices are the main way for capturing information in multimedia, however, due to the influence of atmospheric elements such as fog, haze, smoke, dust, rain, snow and the like, visibility is low outdoors and the quality of captured images is poor. Therefore, images degraded by these weather influences are not suitable for various practical applications such as the field of aviation, the field of video surveillance, the field of intelligent transportation, the field of tracking systems, and the like. Most outdoor video monitoring fields need accurate, real-time and clear feature extraction, and under the weather conditions of fog and haze, a visual algorithm may be influenced to cause the deviation of detection and analysis, so that the monitoring of important information is influenced. The intelligent transportation field has higher requirements for driving, if the intelligent driving system cannot correctly judge the scene visibility in fog and haze weather, the decision-making performance of a driver is reduced, and traffic safety accidents can be caused. Tracking systems such as radar systems, weather forecasts, etc. may cause positioning errors, information transmission errors, etc. if image videos cannot be tracked in real time for information analysis.

In order to solve the problem of images affected by haze weather, many methods have been proposed, and the image restoration based on depth information, which was proposed by Oakley et al at the earliest, restores the environmental contrast by predicting the light path in a scene through a gaussian function, and does not need to predict various types of information of weather. Kopf et al uses scene texture information to derive corresponding depth information. He et al propose a dark channel prior based law. Yu et al propose night defogging using channel difference values in combination with ambient illumination map and transmission map estimation. Cai et al first attempted to construct an end-to-end defogging network using CNN to map an input single foggy image to a transmittance map. Singh et al propose to use simple linear stretching and white balance adjusted results to fuse to obtain a defogged image. Thepad et al have extensively analyzed the color attenuation theory and image edge protection technique, and have obtained a defogged image from fusing the images after color restoration and gradient calculation. Ma et al propose a new idea of fused image selection. The first input image is a simple linear stretch and the second input image is a high enhancement filter algorithm using guided filtering. However, the defogging algorithm only stays in the aspect of software modeling, and in order to apply linear stretching and guiding filtering to an actual scene in a fusion manner, Du et al optimize the algorithm in a better hardware mode, so that resources are saved and the working efficiency is improved. However, the hardware method still consumes time in the first input image, the second input image only considers the preserved edge, and the scene illumination and the color effect of the second input image still need to be improved. The methods have complicated processing process and overlong processing time, neglect the original color sense and environmental illumination of the image, and cannot meet the requirement of real-time high-quality defogging.

Disclosure of Invention

The invention provides a fusion defogging circuit based on parallel gray scale linear stretching and difference value guide filtering to overcome the defects of the prior art, so that the performance of a fusion defogging accelerator can be improved, the processing speed is accelerated, the defogging effect is improved, and the requirement of real-time high-quality defogging is met as far as possible.

In order to achieve the purpose of the invention, the technical scheme adopted by the invention is as follows:

the invention relates to a fusion defogging circuit based on parallel gray scale linear stretching and difference value guide filtering, which is characterized by comprising the following components in parts by weight: the device comprises an input RAM module, a difference module, a shift register array, a buffer, a difference guiding filtering module, a high boosting filtering module, a parallel gray linear stretching module, a fusion module and an output RAM module;

the input RAM module stores RGB image data I with length multiplied by width multiplied by Y and bit width W, and respectively transmits the RGB image data I to the difference module, the shift register array and the parallel gray scale linear stretching module; wherein X, Y and W are positive integers;

the difference module carries out maximum value and minimum value filtering processing on pixel points in the RGB image data I in the window according to a box type filtering window to respectively obtain the maximum value and the minimum value in R, G, B three channels in each window, and respectively calculates the difference between the maximum value and the minimum value in R, G, B three channels in each window to obtain the image block difference value of each window, and the image block difference value is transmitted to the shift register array and the buffer after forming channel difference image data P;

the shift register array comprises two register groups formed by connecting n-1 shift registers in series, wherein n is the side length of a box type filtering window, and the two register groups respectively carry out shift register operation on RGB image data I and channel difference image data P according to the box type filtering window and transmit the RGB image data I and the channel difference image data P to a difference value guide filtering module; wherein n is a positive integer;

the difference guiding filtering module receives the RGB image data I and the difference image data P according to a box type filtering window, carries out smooth noise and edge protection processing, obtains mild image data Q and then transmits the mild image data Q to the high boosting filtering module;

the buffer caches the received difference image data P according to a box-type filtering window, and transmits the difference image data P to a high boosting filtering module after being aligned with the gentle image data Q;

the high-lift filter-pressing module caches the received difference image data P according to a box-type filter window, and obtains sharpened image data G after sharpening and enhancing the received difference image data P and the mild image data Q, and transmits the sharpened image data G to the fusion module;

the parallel gray scale linear stretching module splits the received RGB image data I into two symmetrical partial image data, and respectively carries out gray scale fusion conversion to obtain two corresponding single-channel gray scale image data; comparing the two single-channel gray data and screening out the maximum value and the minimum value of each channel gray data; according to the maximum value and the minimum value, after linear stretching processing is carried out on the two gray level image data, high contrast image data are obtained and transmitted to a fusion module;

and the fusion module fuses the received sharpened image data G and the high-contrast image data L according to the proportional weight to obtain a final defogged image and transmits the final defogged image to the output RAM module.

The fusion defogging circuit based on the parallel gray scale linear stretching and the difference value guide filtering is also characterized in that the parallel gray scale linear stretching module comprises: the system comprises two gray level conversion modules, two gray level RAM modules, a comparison screening module, two division modules and a buffer, and data processing is carried out according to the following processes:

the first gray scale conversion module and the second gray scale conversion module respectively read half of RGB image data I from the input RAM, respectively perform shifting, adding or subtracting calculation on R, G, B three-channel pixel values in the half of RGB image data I, and then add the calculated R, G, B three-channel values to obtain two gray scale image data I_gray1And I_gray2And correspondingly storing the data into a first gray RAM module and a second gray RAM module;

the comparison screening module respectively reads first gray scale image data I from the first gray scale RAM module and the second gray scale RAM module_gray1And second gray scale image data I_gray2And correspondingly screening out the first maximum value I_max1And a first minimum value I_min1And a second maximum value I_max2And a second minimum value I_min2Meanwhile, the comparison screening module respectively provides a read enabling signal and an address for the first gray level RAM module and the second gray level RAM module, so that the first gray level image data I is read periodically_gray1And second gray scale image data I_gray2For calculating dividend number sets B₁And B₂And divisor number set C;

the first division module and the second division module respectively read the dividend B according to periods₁And a divisor C anddividend B₂Dividing the data by a divisor C to obtain first high-contrast data L₁And second high contrast data L₂；

The buffer buffers the high contrast data L through a second buffer₂So that the second high contrast data L₂At the first high contrast data L₁To the end of (c).

The comparison screening module comprises two comparison sub-modules and a score module;

the first comparison submodule reads first gray image data I of the ith pixel point from the first gray conversion module according to period_{gray1_i}And as the current maximum value, the current maximum value and the first gray image data I of the (I + 1) th pixel point read in the next period are used_{gray1_i+1}Comparing the first gray image data I with the comparator, and selecting the larger value as the current maximum value_gray1Comparing each pixel point in the image to obtain a final first maximum value I_max1；

Meanwhile, the first comparison submodule compares the gray level image data I of the ith pixel point_{gray1_i}As the current minimum value, the current minimum value and the gray image data I of the (I + 1) th pixel point read in the next period are taken as_{gray1_i+1}Comparing the first gray image data I with the comparator, and selecting the smaller value as the current minimum value_gray1Comparing each pixel point in the image to obtain a first minimum value I_min1；

Similarly, the second comparison module reads the second gray scale image data I of the ith pixel point from the second gray scale conversion module according to the period_{gray2_i}And performing the same maximum and minimum comparison operation to obtain a second maximum value I_max2And a second minimum value I_min2；

The fraction module receives two maximum values I_max1、I_max2And two minimum values I_min1、I_min2And two maximum values I_max1、I_max2Comparing to obtain the final maximum value I_max(ii) a Two minimum values I_min1、I_min2Comparing to obtain the final minimum value I_min；

Meanwhile, the fraction module respectively provides a read enable signal and an address for the first gray level RAM module and the second gray level RAM module, so that the first gray level image data I is correspondingly read_gray1And second gray scale image data I_gray2And the first gray image data I_gray1With a final minimum value I_minPerforming difference processing to obtain dividend set B₁Second gray scale image data I_gray2With a final minimum value I_minPerforming difference processing to obtain dividend set B₂The final maximum value I_maxAnd the minimum value I_minAnd performing difference calculation processing to obtain a divisor set C.

Compared with the prior art, the beneficial technical effects of the invention are as follows:

1. the invention provides a parallel framework based on gray level linear stretching, an original image is divided into two parts, and the hardware framework is optimized through parallel graying and linear stretching processing. Compared with the traditional serial mode, the method saves about 83% of period, reduces 50% of period compared with the traditional parallel mode and a common gray scale linear stretching framework, saves more resource consumption compared with the parallel mode, optimizes the saturation and contrast of the image in such a shorter time, and greatly improves the linear stretching efficiency;

2. the invention provides a method for realizing comparison screening hardware of a rapid parallel structure, which is different from the traditional direct comparison screening mode, and the method ensures that the screening time and the traversal time are both reduced by 50 percent by performing parallel screening on halved data and traversing half data simultaneously, thereby greatly improving the computing speed;

3. according to the invention, the channel difference graph is used as a guide graph of guide filtering, the defogging effect is better improved, and the fusion speed is improved by 25% compared with that of the traditional structure on the basis of shorter time of parallel gray scale linear stretching;

drawings

FIG. 1 is a diagram of the overall hardware architecture of a fused defogging circuit employed in the present invention;

FIG. 2 is a schematic diagram of a channel difference module of the present invention;

FIG. 3 is a circuit diagram of a difference-oriented filtering module according to the present invention;

FIG. 4 is a circuit diagram of a parallel gray scale linear stretching module employed in the present invention;

FIG. 5 is a circuit diagram of a comparison screening module employed in the present invention;

FIG. 6 is a graph illustrating the comparison of parallel gray scale linear stretching time according to the present invention.

Detailed Description

In this embodiment, a fused defogging circuit based on parallel gray scale linear stretching and difference value guide filtering, as shown in fig. 1, includes: the device comprises an input RAM module, a difference module, a shift register array, a buffer, a difference guiding filtering module, a high boosting filtering module, a parallel gray linear stretching module, a fusion module and an output RAM module;

RGB image data I with length multiplied by width multiplied by X and bit width W is stored in the input RAM module and respectively transmitted to the difference module, the shift register array and the parallel gray scale linear stretching module; wherein X, Y and W are positive integers; in this embodiment, X is 480, Y is 270, W is 24bit, and the unit is a pixel;

as shown in fig. 2, the difference module performs maximum and minimum filtering processing on pixel points in the RGB image data I within a window according to a box-type filtering window to obtain a maximum and a minimum in R, G, B three channels in each window, and performs difference between the maximum and the minimum in R, G, B three channels in each window according to formula (1) to obtain an image block difference of each window, and forms channel difference image data P, and then transmits the channel difference image data P to the shift register array and the buffer;

in the formula (1), wherein I_mFor three channel values of pixel point R, G, B in image data in window

For each windowThe maximum value of the port in the RGB three channels,

the minimum value in the RGB three channels for each window.

The shift register array comprises two register groups which are formed by connecting n-1-7 shift registers in series, wherein n-8 is the side length of a box type filtering window, and the two register groups respectively carry out shift register operation on RGB image data I and channel difference image data P according to the box type filtering window and transmit the RGB image data I and the channel difference image data P to a difference value guide filtering module; wherein n is a positive integer;

the difference-oriented filtering module receives the RGB image data I and the difference image data P according to the box-type filtering window and performs smoothing noise and edge protection processing, as shown in fig. 3, by passing through a multiplier to obtain a product I_m·P_mImage data I and difference image data P and product I_m·P_mObtaining the mean value by three box-type filtering respectively

And

where ω is the size of the square filter window centered on pixel k, m is a certain pixel in the square filter window, the mean

Obtained by a multiplier

Simultaneous difference image data P and mean

Obtained by a squaring module

And

square ofValue of

The mean value of the square is obtained by box filtering

To mean value

Product of and

taking the difference as dividend, pair

And

the difference is calculated as a divisor, the dividend and the divisor are transmitted to a variance normalization module to be calculated according to the formula (2) to obtain a coefficient set a_kAverage value of

Buffer to and coefficient a_kMultiplication and buffered mean

The observation results in a coefficient set b_kThe smooth image data Q is obtained through calculation according to the formula (3) and then transmitted to the high boosting filtering module;

the buffer caches the received difference image data P according to the box-type filtering window, aligns the difference image data P with the gentle image data Q and then transmits the difference image data P to the high-boost filtering module;

the high-lift filter-pressing module caches the received difference image data P according to a box-type filter window, sharpens and enhances the difference image data P and the gentle image data Q, calculates the sharp image data G according to the proportion weight as shown in formula (4), and transmits the sharp image data G to the fusion module;

G＝(I-Q)×α+I (4)

and introducing a high boosting filter parameter alpha into the obtained guide filtering result image Q, sharpening the guide filtering result image in the formula (4), wherein the parameter alpha determines the sharpening degree, the larger the alpha value is, the larger the sharpening degree is, but the corresponding noise is also increased, and I is RGB image data.

The parallel gray scale linear stretching module splits the received RGB image data I into two symmetrical partial image data, as shown in FIG. 4, and performs gray scale fusion conversion respectively to obtain two corresponding single-channel gray scale image data; as shown in fig. 5, comparing two single-channel gray data and screening out the maximum value and the minimum value of each channel gray data; according to the maximum value and the minimum value, after linear stretching processing is carried out on the two gray level image data, high contrast image data are obtained and transmitted to a fusion module;

and the fusion module fuses the received sharpened image data G and the high-contrast image data L according to the proportional weight to obtain a final defogged image and transmits the final defogged image to the output RAM module. And (5) fusing the two input images according to the proportion of the weight lambda to 1-lambda, and combining the most significant characteristics of the two input images to obtain final defogged image data F and transmitting the final defogged image data F to the output RAM module according to the fused result.

F＝λ×L+(1-λ)×G (5)

In a specific implementation, the parallel gray scale linear stretching module comprises: the system comprises two gray level conversion modules, two gray level RAM modules, a comparison screening module, two division modules and a buffer, and data processing is carried out according to the following processes:

the first gray scale conversion module and the second gray scale conversion module respectively read half of the RGB image data I from the input RAM, and respectively shift and add the R, G, B three-channel pixel values in the half of the RGB image data IOr subtraction calculation, and adding the calculated R, G, B three channels to obtain two gray image data I_gray1And I_gray2And correspondingly storing the data into a first gray RAM module and a second gray RAM module; the RGB color image is converted into a gray scale image by the expression (6), and since the expression includes a decimal and involves multiplication and addition, and considering that the multiplication and addition of the decimal complicates a circuit and affects circuit performance in a hardware implementation, the expression (6) is processed by expanding the decimal by a shift method, converting the decimal into integer multiplication, reducing the decimal after calculation, and multiplying all of 0.299, 0.587, and 0.114 by 256, which is the 8 th power of 2, to make the integers 76, 150, and 30, respectively. Then the whole formula is shifted to the right by 8 bits, so that the coefficient just expanded is reduced back, as shown in formula (7); since the equation (7) includes multiplication, it takes a lot of time if a multiplier is needed for serial implementation. The parallelization process needs three multipliers, which consumes a lot of resources, so the method of converting the multiplication coefficients into shift and addition is considered, which can reduce the consumption of resources and improve the calculation speed, as shown in equation (8):

Gray＝R×0.299+G×0.587+B×0.114 (6)

Gray＝(R×76+G×150+B×30)＞＞8 (7)

Gray＝((R＜＜5+R＜＜3-R＜＜1)+(G＜＜6+G＜＜3+G＜＜1+G)+(B＜＜4-B))＜＜2 (8)

the comparison screening module respectively reads first gray scale image data I from the first gray scale RAM module and the second gray scale RAM module_gray1And second gray scale image data I_gray2And correspondingly screening out the first maximum value I_max1And a first minimum value I_min1And a second maximum value I_max2And a second minimum value I_min2Meanwhile, the comparison screening module respectively provides a read enabling signal and an address for the first gray level RAM module and the second gray level RAM module, so that the first gray level image data I is read periodically_gray1And second gray scale image data I_gray2For calculating dividend number sets B₁And B₂And divisor number set C;

the first division module and the second division module are respectively based onPeriodic reading of dividend B₁A sum divisor C and a dividend B₂Dividing the data by a divisor C to obtain first high-contrast data L₁And second high contrast data L₂；

The buffer buffers the high contrast data L through a second buffer₂So that the second high contrast data L₂At the first high contrast data L₁To the end of (c). After the gray single-channel maximum value and the gray single-channel minimum value are screened out, traversing the whole gray picture, and carrying out difference and division operation on each pixel and the maximum value and the minimum value to obtain high-contrast data L as shown in formula (9):

in the formula (9), I^GrayFor the value of each pixel of the grayscale picture,

is the minimum value of the values of the pixel points in the gray scale of the whole picture,

the maximum value of the values of the pixel points in the gray scale of the whole picture.

The fusion defogging circuit is characterized in that the comparison screening module comprises two comparison sub-modules and a fraction module;

the first comparison submodule reads first gray image data I of the ith pixel point from the first gray conversion module according to period_{gray1_i}And as the current maximum value, the current maximum value and the first gray image data I of the (I + 1) th pixel point read in the next period are used_{gray1_i+1}Comparing the first gray image data I with the comparator, and selecting the larger value as the current maximum value_gray1Comparing each pixel point in the image to obtain a final first maximum value I_max1；

Meanwhile, the first comparison submodule compares the gray of the ith pixel pointDegree image data I_{gray1_i}As the current minimum value, the current minimum value and the gray image data I of the (I + 1) th pixel point read in the next period are taken as_{gray1_i+1}Comparing the first gray image data I with the comparator, and selecting the smaller value as the current minimum value_gray1Comparing each pixel point in the image to obtain a first minimum value I_min1；

Similarly, the second comparison module reads the second gray scale image data I of the ith pixel point from the second gray scale conversion module according to the period_{gray2_i}And performing the same maximum and minimum comparison operation to obtain a second maximum value I_max2And a second minimum value I_min2；

The fraction module receives two maximum values I_max1、I_max2And two minimum values I_min1、I_min2And two maximum values I_max1、I_max2Comparing to obtain the final maximum value I_max(ii) a Two minimum values I_min1、I_min2Comparing to obtain the final minimum value I_min；

Meanwhile, the fraction module respectively provides a read enable signal and an address for the first gray level RAM module and the second gray level RAM module, so that the first gray level image data I is correspondingly read_gray1And second gray scale image data I_gray2And the first gray image data I_gray1With a final minimum value I_minPerforming difference processing to obtain dividend set B₁Second gray scale image data I_gray2With a final minimum value I_minPerforming difference processing to obtain dividend set B₂The final maximum value I_maxAnd the minimum value I_minAnd performing difference calculation processing to obtain a divisor set C. The final output is the result of the linear stretching, as shown in fig. 5.

As shown in fig. 6, a conventional serial structure and an improved parallel gray scale linear stretching structure are compared, a conventional serialization needs to traverse each channel to calculate a linear stretching value of each pixel value, that is, to traverse RGB channels successively, a large amount of time is consumed, the improved linear stretching shortens the linear stretching time, the gray scale calculation and the gray scale channel comparison adopt parallel calculation, and the contrast stretching is simultaneously completed on the halved images in the whole process, so that only half of the image traversing time is needed, all other modules in the same way only need to process half of the images, the original Ta + Tb + Tc time is shortened to Ta + (Tb + Tc)/2, the whole contrast stretching time is shortened by nearly 50%, and the processing speed is obviously improved.

Claims (3)

1. A fusion defogging circuit based on parallel gray scale linear stretching and difference value guide filtering is characterized by comprising: the device comprises an input RAM module, a difference module, a shift register array, a buffer, a difference guiding filtering module, a high boosting filtering module, a parallel gray linear stretching module, a fusion module and an output RAM module;

the input RAM module stores RGB image data I with length multiplied by width multiplied by Y and bit width W, and respectively transmits the RGB image data I to the difference module, the shift register array and the parallel gray scale linear stretching module; wherein X, Y and W are positive integers;

the difference module carries out maximum value and minimum value filtering processing on pixel points in the RGB image data I in the window according to a box type filtering window to respectively obtain the maximum value and the minimum value in R, G, B three channels in each window, and respectively calculates the difference between the maximum value and the minimum value in R, G, B three channels in each window to obtain the image block difference value of each window, and the image block difference value is transmitted to the shift register array and the buffer after forming channel difference image data P;

the shift register array comprises two register groups formed by connecting n-1 shift registers in series, wherein n is the side length of a box type filtering window, and the two register groups respectively carry out shift register operation on RGB image data I and channel difference image data P according to the box type filtering window and transmit the RGB image data I and the channel difference image data P to a difference value guide filtering module; wherein n is a positive integer;

the difference guiding filtering module receives the RGB image data I and the difference image data P according to a box type filtering window, carries out smooth noise and edge protection processing, obtains mild image data Q and then transmits the mild image data Q to the high boosting filtering module;

the buffer caches the received difference image data P according to a box-type filtering window, and transmits the difference image data P to a high boosting filtering module after being aligned with the gentle image data Q;

the high-lift filter-pressing module caches the received difference image data P according to a box-type filter window, and obtains sharpened image data G after sharpening and enhancing the received difference image data P and the mild image data Q, and transmits the sharpened image data G to the fusion module;

the parallel gray scale linear stretching module splits the received RGB image data I into two symmetrical partial image data, and respectively carries out gray scale fusion conversion to obtain two corresponding single-channel gray scale image data; comparing the two single-channel gray data and screening out the maximum value and the minimum value of each channel gray data; according to the maximum value and the minimum value, after linear stretching processing is carried out on the two gray level image data, high contrast image data are obtained and transmitted to a fusion module;

and the fusion module fuses the received sharpened image data G and the high-contrast image data L according to the proportional weight to obtain a final defogged image and transmits the final defogged image to the output RAM module.

2. The fused defogging circuit according to claim 1, wherein said parallel gray scale linear stretching module comprises: the system comprises two gray level conversion modules, two gray level RAM modules, a comparison screening module, two division modules and a buffer, and data processing is carried out according to the following processes:

the first gray scale conversion module and the second gray scale conversion module respectively read half of RGB image data I from the input RAM, respectively perform shifting, adding or subtracting calculation on R, G, B three-channel pixel values in the half of RGB image data I, and then add the calculated R, G, B three-channel values to obtain two gray scale image data I_gray1And I_gray2And correspondingly storing the data into a first gray RAM module and a second gray RAM module;

the comparison and screening module selects a first gray RAM module and a second gray RAM moduleRespectively reading the first gray image data I_gray1And second gray scale image data I_gray2And correspondingly screening out the first maximum value I_max1And a first minimum value I_min1And a second maximum value I_max2And a second minimum value I_min2Meanwhile, the comparison screening module respectively provides a read enabling signal and an address for the first gray level RAM module and the second gray level RAM module, so that the first gray level image data I is read periodically_gray1And second gray scale image data I_gray2For calculating dividend number sets B₁And B₂And divisor number set C;

the first division module and the second division module respectively read the dividend B according to periods₁A sum divisor C and a dividend B₂Dividing the data by a divisor C to obtain first high-contrast data L₁And second high contrast data L₂；

The buffer buffers the high contrast data L through a second buffer₂So that the second high contrast data L₂At the first high contrast data L₁To the end of (c).

3. The fused defogging circuit based on the parallel gray scale linear stretching and the difference value guide filtering as claimed in claim 2, wherein said comparison screening module comprises two comparison sub-modules and a fraction module;

the first comparison submodule reads first gray image data I of the ith pixel point from the first gray conversion module according to period_{gray1_i}And as the current maximum value, the current maximum value and the first gray image data I of the (I + 1) th pixel point read in the next period are used_{gray1_i+1}Comparing the first gray image data I with the comparator, and selecting the larger value as the current maximum value_gray1Comparing each pixel point in the image to obtain a final first maximum value I_max1；

Meanwhile, the first comparison submodule compares the gray level image data I of the ith pixel point_{gray1_i}As the current minimum value, the current minimum value and the gray image number of the (i + 1) th pixel point read in the next period are usedAccording to I_{gray1_i+1}Comparing the first gray image data I with the comparator, and selecting the smaller value as the current minimum value_gray1Comparing each pixel point in the image to obtain a first minimum value I_min1；

Similarly, the second comparison module reads the second gray scale image data I of the ith pixel point from the second gray scale conversion module according to the period_{gray2_i}And performing the same maximum and minimum comparison operation to obtain a second maximum value I_max2And a second minimum value I_min2；

The fraction module receives two maximum values I_max1、I_max2And two minimum values I_min1、I_min2And two maximum values I_max1、I_max2Comparing to obtain the final maximum value I_max(ii) a Two minimum values I_min1、I_min2Comparing to obtain the final minimum value I_min；

Meanwhile, the fraction module respectively provides a read enable signal and an address for the first gray level RAM module and the second gray level RAM module, so that the first gray level image data I is correspondingly read_gray1And second gray scale image data I_gray2And the first gray image data I_gray1With a final minimum value I_minPerforming difference processing to obtain dividend set B₁Second gray scale image data I_gray2With a final minimum value I_minPerforming difference processing to obtain dividend set B₂The final maximum value I_maxAnd the minimum value I_minAnd performing difference calculation processing to obtain a divisor set C.

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