CN114137881B - Chip awakening device, method and medium thereof - Google Patents
Chip awakening device, method and medium thereof Download PDFInfo
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- CN114137881B CN114137881B CN202111450321.8A CN202111450321A CN114137881B CN 114137881 B CN114137881 B CN 114137881B CN 202111450321 A CN202111450321 A CN 202111450321A CN 114137881 B CN114137881 B CN 114137881B
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- 230000000903 blocking effect Effects 0.000 claims description 11
- 238000004590 computer program Methods 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 11
- 230000002618 waking effect Effects 0.000 claims description 3
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
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Abstract
The application discloses a chip awakening device, a method and a medium, and provides a chip awakening device aiming at the problem of GPIO resource waste caused by the current use of latches to realize the awakening of chips by multiple awakening sources, comprising the following steps: the device comprises a controller, an external wake-up source, a level holding circuit, a wake-up circuit and a detection circuit; the level holding circuit is connected with an external wake-up source and is used for holding a level signal; the wake-up circuit is connected with each level holding circuit and the wake-up end of the controller, and a level signal input by an external wake-up source can be input to the wake-up end through the wake-up circuit so as to wake up the controller; the detection circuit is connected with the corresponding level holding circuit, the enabling end of the controller and the corresponding detection end, and is used for detecting to determine the external wake-up source of the wake-up controller when the enabling end is in an allowed state after the controller is waken up, so that the circuit can be controlled by only one enabling end, and GPIO resources of a chip are saved.
Description
Technical Field
The present disclosure relates to the field of low power consumption chip wake-up, and in particular, to a chip wake-up device, method and medium thereof.
Background
At present, in the development of application products of the internet of things, a plurality of wake-up requirements are usually required, for example, a plurality of cases or a plurality of external interrupt triggers are used as external wake-up sources, but because the bottom resources of a low-power chip required to be used by the internet of things are limited, only one general purpose input/output port (General Purpose Input Output, GPIO) capable of directly providing a wake-up function is provided, other GPIOs indirectly provide the wake-up function in the form of being connected with the GPIO capable of directly waking up the chip, and the number of the other GPIOs is limited and insufficient to support the excessive external wake-up sources, each external wake-up source is usually connected with one GPIO capable of supporting the wake-up function at present, the state of the GPIO is saved through a latch, and after the chip is woken up, the chip is processed to identify the chip which is woken up by the external wake-up source.
The latch usually used at present stores the GPIO state to wake up the chip, so that the external wake-up source can be identified to wake up the chip, and the function of waking up the chip by multiple wake-up sources is realized.
Therefore, a chip wake-up device is needed by those skilled in the art, so as to solve the problem of GPIO resource waste caused by wake-up of chips with multiple external wake-up sources by using latches.
Disclosure of Invention
The purpose of the application is to provide a chip wake-up device, a chip wake-up method and a medium thereof, which solve the problem of GPIO resource waste caused by wake-up chips with a plurality of external wake-up sources by using latches at present.
In order to solve the above technical problem, the present application provides a chip wake-up device, including: the device comprises a controller, an external wake-up source, a level holding circuit, a wake-up circuit and a detection circuit; the level keeping circuit is connected with the external wake-up sources and is used for keeping the level signals when the external wake-up sources input the level signals, wherein each external wake-up source corresponds to one level keeping circuit; the wake-up circuit is connected with each level holding circuit and the wake-up end of the controller, and when an external wake-up source inputs a level signal, the level signal is input to the wake-up end through the wake-up circuit to wake up the controller; the detection circuit is connected with the corresponding level holding circuit, the enabling end of the controller and the corresponding detection end, and is used for detecting to determine an external wake-up source of the wake-up controller when the controller is waken up and the enabling end is in an allowed state.
Preferably, the external wake-up source is a push-button switch, and the level-keeping circuit includes: a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a first transistor; the first end of the first resistor is connected with the positive electrode of the power supply and the first end of the first transistor, and the second end of the first resistor is connected with the first end of the first capacitor, the second end of the first transistor and the first end of the key switch; the second end of the first capacitor is connected with the second end of the key switch, the second end of the second capacitor and the second end of the third resistor, and is grounded; the first end of the second resistor is connected with the third end of the first transistor, and the second end of the second resistor is connected with the first end of the second capacitor and the first end of the third resistor.
Preferably, the wake-up circuit comprises: a fourth resistor, a third capacitor and a diode; the first end of the fourth resistor is connected with the positive electrode of the power supply, and the second end of the fourth resistor is connected with the first end of the third capacitor and the wake-up end; the second end of the third capacitor is grounded; the key switches are connected with the awakening ends through the diodes, wherein each key switch corresponds to one diode respectively, the first ends of the key switches are connected with the cathodes of the corresponding diodes, and the anodes of the diodes are connected with the awakening ends.
Preferably, the detection circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second transistor, and a third transistor; the first end of the fifth resistor is connected with the first end of the second transistor and the first end of the third resistor in the level holding circuit, and the second end of the fifth resistor is connected with the second end of the second transistor and the first end of the sixth resistor; the second end of the sixth resistor is connected with the third end of the third transistor; the third end of the second transistor is connected with the first end of the seventh resistor; the second end of the seventh resistor is connected with the first end of the third transistor, the second end of the eighth resistor and the second end of the third resistor of the level holding circuit; the first end of the eighth resistor is connected with the second end of the third transistor and the second end of the ninth resistor; the first terminal of the ninth resistor is connected to the enable terminal.
Preferably, the first transistor is a field effect transistor.
Preferably, the second transistor and the third transistor are transistors.
In order to solve the above technical problem, the present application further provides a chip wake-up method, which is applied to the chip wake-up device, including: when a wake-up signal is received, the enabling end is set to be in a blocking state; when APP operation is detected, setting an enabling end to be in an allowed state; and detecting by a detection circuit to determine the external wake-up source.
In order to solve the above technical problem, the present application further provides a chip wake-up device, including: the blocking module is used for setting the enabling end to be in a blocking state when the wake-up signal is received; the permission module is used for setting the enabling terminal to be in a permission state when detecting that the APP is operated; the detection module is used for detecting through the detection circuit and determining an external awakening source at the time.
In order to solve the above technical problem, the present application further provides a chip wake-up device, including: a memory for storing a computer program; and the processor is used for realizing the steps of the chip awakening method when executing the computer program.
In order to solve the above technical problem, the present application further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the chip wake-up method described above.
According to the chip awakening device, the holding circuit is used for holding the level signals input by the external awakening source, after the chip is awakened by the awakening circuit, the held level signals can be detected through the detection circuit, and as each external awakening source corresponds to the holding circuit, the detection circuit and the detection end of the controller one by one, the controller can detect the external awakening source which is awakened this time, and as the control detection circuit only needs one enabling end, namely only occupies one GPIO for controlling the external circuit, the GPIO resources of the chip are saved, the saved GPIO is used for detecting more external awakening sources, so that under the condition that the total GPIO resources of the chip are unchanged, more external awakening sources can be externally connected, and the detection of the external awakening sources is realized.
The chip wake-up method, the chip wake-up device and the computer readable storage medium correspond to the chip wake-up device and have the same effects.
Drawings
For a clearer description of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a chip wake-up device provided by the invention;
FIG. 2 is a circuit diagram of a level hold circuit and a detection circuit provided by the present invention;
FIG. 3 is a circuit diagram of a wake-up circuit according to the present invention;
FIG. 4 is a block diagram of another wake-up device for chips according to the present invention;
fig. 5 is a block diagram of another chip wake-up device according to the present invention.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments herein without making any inventive effort are intended to fall within the scope of the present application.
The core of the application is to provide a chip wake-up device, a chip wake-up method and a chip wake-up medium.
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description.
In the actual partial application scenes, the chip has higher requirement on the continuous working time, so that the chip with lower power consumption needs to be selected, meanwhile, the chip needs to enter a dormant state when not working, the power consumption is reduced to the greatest extent, and the chip needs to be controlled and can be awakened in time. The low power consumption chip meeting the above requirements generally has only a single wake-up end due to the limitation of the bottom resource, and only one external wake-up source 12 is connected, so that the multiple external wake-up sources 12 cannot be judged to wake up from the external wake-up source 12 when the external wake-up source 12 inputs a wake-up signal, and the multiple wake-up requirements are not satisfied, so that the external latch is generally used at present, the level signal input by the external wake-up source 12 for wake-up is stored, and after the chip is wake-up, the external wake-up source 12 of the wake-up chip can be known by detecting which external wake-up source 12 has the level signal corresponding to GPIO. However, no matter what type or model of latch is used, besides being connected to the only wake-up end of the chip, at least two GPIOs are needed to realize the control of the latch by the chip, so that the unnecessary GPIOs resources are wasted, and therefore, the application provides a chip wake-up device, as shown in fig. 1, comprising: a controller 11, an external wake-up source 12, a level holding circuit 13, a wake-up circuit 14 and a detection circuit 15;
the level holding circuit 13 is connected with the external wake-up sources 12 and is used for holding the level signals when the external wake-up sources 12 input the level signals, wherein each external wake-up source 12 corresponds to one level holding circuit 13; the wake-up circuit 14 is connected with each level holding circuit 13 and the wake-up end of the controller 11, and when the external wake-up source 12 inputs a level signal, the level signal is input to the wake-up end through the wake-up circuit 14 to wake up the controller 11; the detection circuit 15 is connected to the corresponding level holding circuit 13 and the enabling end of the controller 11, and the corresponding detection end, and is configured to detect when the enabling end is in the enabled state after the controller 11 is woken up, so as to determine the external wake-up source 12 of the wake-up controller 11.
It should be noted that, the type and number of the external wake-up sources 12 are not limited in this application, the external wake-up sources 12 may be a key switch S1, an external interrupt trigger, or the like, and may be one or more, but note that the external wake-up sources 12 are in one-to-one correspondence with the holding circuit and the detection end of the controller 11, so when determining the number of external wake-up sources 12, it is necessary to combine the multiple wake-up source wake-up requirements and the number of other GPIOs except the wake-up end of the controller 11 to comprehensively consider.
To further illustrate how a chip wake-up device provided in the present application is detected, a detailed description will be given below.
The low power consumption chip has 4 GPIO, namely GPIO1, GPIO2, GPIO3 and GPIO4, wherein the only GPIO with wake-up function is GPIO1, so that the wake-up end in the device is GPIO1; the enabling terminal can be arbitrarily selected from the three remaining GPIOs, and the remaining GPIOs 3 and GPIOs 4 are regarded as GPIOs 2 in this example, so as to serve as two detecting terminals, respectively corresponding to two external wake-up sources 12, GPIOs 3 corresponds to external wake-up source a, GPIOs 4 corresponds to external wake-up source B, and each external wake-up source 12 and GPIOs are connected through an independent level holding circuit 13 and a detecting circuit 15; when one of the two external wake-up sources 12 inputs a level signal, the wake-up end receives the wake-up signal, the chip is waken up, at this time, the enabling end is in a blocking state, when the chip detects that an application program (APP) starts to run, the enabling end is set in an enabling state, and whether the chip is the external wake-up source a or the external wake-up source B is obtained by detecting whether the level signal is input at the GPIO3 or the GPIO 4.
It will be readily appreciated that when an external wake-up source 12 needs to be extended, a new hold circuit and detection circuit 15 may be added, and one wake-up circuit 14 may be shared.
To further explain a chip wake-up device provided in the present application, a specific implementation manner of the level holding circuit 13 will be described in detail, as shown in fig. 2, the external wake-up source 12 is a key switch S1, and the level holding circuit 13 includes: the first resistor R1, the second resistor R2, the third resistor R3, the first capacitor C1, the second capacitor C2 and the first transistor Q1;
a first end of the first resistor R1 is connected with a power supply positive electrode (VCC) and a first end of the first transistor Q1, and a second end of the first resistor R1 is connected with a first end of the first capacitor C1, a second end of the first transistor Q1 and a first end of the key switch S1; the second end of the first capacitor C1 is connected with the second end of the key switch S1, the second end of the second capacitor C2 and the second end of the third resistor R3, and is Grounded (GND); the first end of the second resistor R2 is connected to the third end of the first transistor Q1, and the second end of the second resistor R2 is connected to the first end of the second capacitor C2 and the first end of the third resistor R3.
It should be noted that the network reference KEY1 in fig. 2 is shown connected to the wake-up circuit 14, and the embodiment is not limited to the specific form of the first transistor Q1, and may be a field effect transistor, a thyristor or a triode, but provides a preferred embodiment: the first transistor Q1 is a field effect transistor.
The advantage of the first transistor Q1 being a field effect transistor is that: the field effect transistor has the advantages of small noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, wide safe working area and the like.
Correspondingly, when the first transistor Q1 is a field effect transistor, the first end of the first transistor Q1 is a source electrode of the field effect transistor, the second end of the first transistor Q1 is a gate electrode of the field effect transistor, and the third end of the first transistor Q1 is a drain electrode of the field effect transistor.
It is to be understood that, in the present embodiment, the level holding circuit 13 is only the level holding circuit 13 corresponding to one external wake-up source 12, and the level holding circuits 13 corresponding to other external wake-up sources 12 are not different from those of the present embodiment, so that the description of the present embodiment is omitted herein.
For further explanation of the chip wake-up device provided in the present application, the embodiment further describes a specific implementation manner of the wake-up circuit 14, as shown in fig. 3, where the wake-up circuit 14 includes: a fourth resistor R4, a third capacitor C3 and a diode;
the first end of the fourth resistor R4 is connected with the positive electrode of the power supply, and the second end of the fourth resistor R4 is connected with the first end and the wake-up end of the third capacitor C3; the second end of the third capacitor C3 is grounded; the key switches S1 are connected with the awakening ends through diodes, wherein each key switch S1 corresponds to one diode respectively, the first ends of the key switches S1 are connected with the cathodes of the corresponding diodes, and the anodes of the diodes are connected with the awakening ends.
It should be noted that, in fig. 3, the network reference INT PIN indicates that the wake-up terminal of the controller 11 is connected, while the network reference KEY1 indicates that the wake-up terminal is connected to the level-keeping circuit 13, and the KEY2 indicates that the wake-up circuit 13 is connected to another level-keeping circuit 13, and the circuit diagram of the wake-up circuit 14 shown in fig. 3 is only externally connected to two level-keeping circuits 13, that is, the corresponding implementation background is that the external wake-up source 12 is two, so that the corresponding diodes are also two, namely the first diode D1 and the second diode D2, and if a new external wake-up source 12 needs to be added, only the corresponding level-keeping circuit 13 needs to be expanded and the same connection relationship as described above is adopted.
In addition, the embodiment is not limited to the specific form of the second transistor Q2, and may be a field effect transistor, a thyristor, or a triode, but provides a preferred embodiment: the second transistor Q2 is a transistor.
Correspondingly, when the second transistor Q2 is a triode, the first end of the second transistor Q2 is an emitter of the triode, the second end of the second transistor Q2 is a base of the triode, and the third end of the second transistor Q2 is a collector of the triode.
In order to further explain a chip wake-up device provided in the present application, this embodiment further describes a specific implementation manner of the detection circuit 15, as shown in fig. 2, the detection circuit 15 includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a second transistor Q2, and a third transistor Q3;
a first end of the fifth resistor R5 is connected to a first end of the second transistor Q2 and a first end of the third resistor R3 in the level holding circuit 13, and a second end of the fifth resistor R5 is connected to a second end of the second transistor Q2 and a first end of the sixth resistor R6; a second end of the sixth resistor R6 is connected to a third end of the third transistor Q3; the third end of the second transistor Q2 is connected with the first end of the seventh resistor R7; the second terminal of the seventh resistor R7 is connected to the first terminal of the third transistor Q3, the second terminal of the eighth resistor R8, and the second terminal of the third resistor R3 of the level holding circuit 13; a first end of the eighth resistor R8 is connected to the second end of the third transistor Q3 and the second end of the ninth resistor R9; the first terminal of the ninth resistor R9 is connected to the enable terminal.
It should be noted that the network reference KEY1 PIN in fig. 2 indicates a detection terminal connection corresponding to the detection circuit 15, and the network reference CTRL indicates an enable terminal connection with the controller 11.
The advantage of the second transistor Q2 and the third transistor Q3 being transistors is that: the triode has high switching speed and low cost, and can improve the efficiency of the circuit.
As can be seen from the foregoing, in the chip wake-up device provided by the present application, each detection end corresponds to one external wake-up source 12, and the level holding circuit 13 can hold the level signal input by the external wake-up source 12, when the chip is wake-up, the external wake-up sources 12 of the chip wake-up at this time can be judged by detecting whether all the detection ends have level signals, so that the wake-up of multiple external wake-up sources 12 of the chip at the single wake-up end is realized, and meanwhile, since the control detection circuit 15 only needs one enabling end to control, compared with the method of the latch used at present, the GPIO resource of the chip is further saved, so that more external wake-up sources 12 wake-up the chip under the premise that the GPIO resource of the chip is limited.
In the foregoing embodiments, a detailed description is given of a chip wake-up device, and the application further provides a chip wake-up method, which is applied to the chip wake-up device, including:
s101: when a wake-up signal is received, the enable end is set to a blocking state.
S102: when APP operation is detected, the enable end is set to an enable state.
S103: the detection circuit 15 detects the external wake-up source 12 at this time.
In the embedded operating system, when the chip is awakened from the sleep mode, a BootLoader (BootLoader) needs to be started to initialize the hardware device and establish a memory space map, so that the software and hardware environment of the system is brought to a proper state to prepare a correct environment for finally calling the kernel of the operating system, but because the BootLoader has level fluctuation, a certain influence is generated on a circuit connected with the BootLoader at the moment, when the chip is awakened, an enabling end is set to be in a blocking state, a detection circuit 15 and other circuits are not influenced by the BootLoader, and when the chip starts to run an application, the BootLoader is explained to be ended, and the enabling end is set to be in an allowing state at the moment, so that the chip can determine the external awakening source 12 of the chip through the detection circuit 15.
The chip wake-up method provided by the embodiment corresponds to the chip wake-up device, and can avoid the influence of level fluctuation generated when the chip is in a BootLoader state on a circuit besides the beneficial effects corresponding to the device, thereby further improving the stability and reliability of the chip wake-up device.
Similarly, the application also provides an embodiment of the chip wake-up device corresponding to the method. It should be noted that the present application describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.
Based on the functional module, as shown in fig. 4, the present application provides a chip wake-up device, including:
the blocking module 21 is configured to set the enabling terminal to a blocking state when the wake-up signal is received.
An enable module 22 is configured to set the enable terminal to an enable state when the APP operation is detected.
The detection module 23 is configured to determine the external wake-up source 12 by detecting by the detection circuit 15.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
Fig. 5 is a block diagram of a chip wake-up device according to another embodiment of the present application, and as shown in fig. 5, the chip wake-up device includes: a memory 30 for storing a computer program;
a processor 31 for implementing the steps of a chip wake-up method according to the above embodiment when executing a computer program.
The chip wake-up device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 31 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 31 may be implemented in hardware in at least one of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 31 may also comprise a main processor, which is a processor for processing data in an awake state, also called central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 31 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content required to be displayed by the display screen. In some embodiments, the processor 31 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.
Memory 30 may include one or more computer-readable storage media, which may be non-transitory. Memory 30 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 30 is at least used for storing a computer program 301, where the computer program, when loaded and executed by the processor 31, is capable of implementing the relevant steps of a chip wake-up method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 30 may further include an operating system 302, data 303, and the like, where the storage manner may be transient storage or permanent storage. The operating system 302 may include Windows, unix, linux, among other things. The data 303 may include, but is not limited to, a chip wake-up method, and the like.
In some embodiments, a chip wake-up device may further include a display 32, an input/output interface 33, a communication interface 34, a power supply 35, and a communication bus 36.
Those skilled in the art will appreciate that the configuration shown in fig. 5 is not limiting of a chip wake-up device and may include more or fewer components than shown.
The chip wake-up device provided by the embodiment of the application comprises a memory and a processor, wherein the processor can realize the following method when executing a program stored in the memory: a chip wake-up method.
Finally, the present application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. With such understanding, the technical solution of the present application, or a part contributing to the prior art or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, performing all or part of the steps of the method described in the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above describes a chip wake-up device, a method and a medium thereof. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A chip wake-up device, comprising: the device comprises a controller, an external wake-up source, a level holding circuit, a wake-up circuit and a detection circuit;
the level keeping circuit is connected with the external wake-up sources and is used for keeping the level signals when the external wake-up sources input the level signals, wherein each external wake-up source corresponds to one level keeping circuit; the wake-up circuit is connected with each level holding circuit and the wake-up end of the controller, and when the external wake-up source inputs the level signal, the level signal is input to the wake-up end through the wake-up circuit so as to wake up the controller; the detection circuit is connected with the corresponding level holding circuit, the corresponding enabling end of the controller and the corresponding detection end, and is used for detecting to determine the external wake-up source for waking up the controller when the controller is waken up and the enabling end is in an allowed state.
2. The chip wake-up device of claim 1, wherein the external wake-up source is a key switch, and the level-holding circuit comprises: a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a first transistor;
the first end of the first resistor is connected with the positive electrode of the power supply and the first end of the first transistor, and the second end of the first resistor is connected with the first end of the first capacitor, the second end of the first transistor and the first end of the key switch; the second end of the first capacitor is connected with the second end of the key switch, the second end of the second capacitor and the second end of the third resistor and is grounded; the first end of the second resistor is connected with the third end of the first transistor, and the second end of the second resistor is connected with the first end of the second capacitor and the first end of the third resistor.
3. The chip wake-up device of claim 2, wherein the wake-up circuit comprises: a fourth resistor, a third capacitor and a diode;
the first end of the fourth resistor is connected with the positive electrode of the power supply, and the second end of the fourth resistor is connected with the first end of the third capacitor and the wake-up end; the second end of the third capacitor is grounded; the key switches are connected with the awakening ends through the diodes, wherein each key switch corresponds to one diode respectively, the first end of each key switch is connected with the cathode of the corresponding diode, and the anode of each diode is connected with the awakening end.
4. The chip wake-up device of claim 3, wherein the detection circuit comprises: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second transistor, and a third transistor;
a first end of the fifth resistor is connected with a first end of the second transistor and a first end of the third resistor in the level holding circuit, and a second end of the fifth resistor is connected with a second end of the second transistor and a first end of the sixth resistor; a second end of the sixth resistor is connected with a third end of the third transistor; a third end of the second transistor is connected with the first end of the seventh resistor; a second terminal of the seventh resistor is connected to a first terminal of the third transistor, a second terminal of the eighth resistor, and a second terminal of the third resistor of the level holding circuit; the first end of the eighth resistor is connected with the second end of the third transistor and the second end of the ninth resistor; the first end of the ninth resistor is connected with the enabling end.
5. The chip wake-up device of claim 2, wherein the first transistor is a field effect transistor.
6. The chip wake-up device of claim 4, wherein the second transistor and the third transistor are transistors.
7. A chip wake-up method, characterized by being applied to the chip wake-up device of any one of claims 1 to 6, comprising:
when a wake-up signal is received, the enabling end is set to be in a blocking state;
when APP operation is detected, setting the enabling end to be in an allowed state;
and detecting by a detection circuit to determine the external wake-up source.
8. A chip wake-up device, comprising:
the blocking module is used for setting the enabling end to be in a blocking state when the wake-up signal is received;
the permission module is used for setting the enabling end to be in a permission state when detecting that the APP is operated;
the detection module is used for detecting through the detection circuit and determining an external awakening source at the time.
9. A chip wake-up device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the chip wake-up method of claim 7 when executing said computer program.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the chip wake-up method according to claim 7.
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