CN114137660A - Preparation method and structure of hybrid integrated light quantum chip - Google Patents
Preparation method and structure of hybrid integrated light quantum chip Download PDFInfo
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- CN114137660A CN114137660A CN202111437447.1A CN202111437447A CN114137660A CN 114137660 A CN114137660 A CN 114137660A CN 202111437447 A CN202111437447 A CN 202111437447A CN 114137660 A CN114137660 A CN 114137660A
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- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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Abstract
The embodiment of the application discloses a preparation method and a structure of a hybrid integrated optical quantum chip, wherein the preparation method comprises the steps of obtaining a structure to be etched and a structure to be transferred, the structure to be etched comprises a quantum dot layer, the structure to be transferred comprises a region to be transferred, and then the structure to be etched is etched, so that a waveguide structure is formed on the quantum dot layer, and then the waveguide structure is picked up by a polymer and transferred to the region to be transferred of the structure to be transferred, and the optical quantum chip is obtained. Based on the application, the polymer is used for picking up the waveguide structure and is transferred to the region to be transferred of the structure to be transferred, so that the light quantum chip is obtained, the coupling efficiency can be improved, and the size of the chip is reduced.
Description
Technical Field
The invention relates to the technical field of quantum application, in particular to a preparation method and a structure of a hybrid integrated light quantum chip.
Background
Silicon carbide (SiC) is a mature semiconductor material and has the advantages of wide forbidden band, high refractive index, wide transparent window and the like. For example, 4H type SiC has a forbidden band width of 3.26eV, a refractive index of 2.64 for SiC, which corresponds to light having a wavelength of 890nm, and a width of a SiC transparent window of 0.37 to 5.6 μm, and multiphoton absorption can be avoided. Meanwhile, SiC is a Semiconductor material compatible with a Complementary Metal Oxide Semiconductor (CMOS), is expected to realize monolithic integration of electronic devices by a low-cost CMOS photonics technology, and has stronger competitiveness than lithium niobate photonics. Unlike silicon nitride, SiC can exhibit higher order nonlinear effects, and thus SiC can be used for low loss, ultrafast, and wide bandwidth data transmission.
Quantum Dots (QDs) generally refer to semiconductor nanocrystals with radii smaller than or close to the exciton bohr radius, with unique fluorescence nano-effects. The quantum dots have wide and continuous distribution of excitation spectrum, narrow and symmetrical emission spectrum, strong fluorescence intensity, slow bleaching rate and high sensitivity, can regulate and control the luminescence wavelength by changing the particle size and composition, and have wide application prospect in the aspects of luminescent materials, photocatalysis, photosensitive sensors, fluorescent probe labeling and the like. The III-V family quantum dots have excellent near infrared spectrum fluorescence emission properties and high light-emitting brightness properties, and have important value in the research of solid-state emission devices of single photon and entangled photon pairs.
In the preparation process of a light quantum chip, the key point is to couple a passive silicon carbide chip and an active quantum dot photon emitter in a single chip, and the main coupling mode is free space coupling at present, however, the method cannot meet the requirements of chip miniaturization installation and maximum coupling efficiency.
Disclosure of Invention
The embodiment of the application provides a preparation method and a structure of a hybrid integrated light quantum chip, which can improve the coupling efficiency and reduce the volume of the chip.
The embodiment of the application provides a preparation method of a hybrid integrated optical quantum chip, which comprises the following steps:
obtaining a structure to be etched and a structure to be transferred; the structure to be etched comprises a quantum dot layer; the structure to be transferred comprises a region to be transferred;
etching the structure to be etched to form a waveguide structure on the quantum dot layer;
and picking up the waveguide structure by using the polymer, and transferring the waveguide structure to a region to be transferred of the structure to be transferred to obtain the light quantum chip.
Further, the region to be transferred includes a silicon carbide photonic circuit.
Further, the waveguide structure is picked up by using a polymer and transferred to a region to be transferred of the structure to be transferred, so as to obtain the optical quantum chip, which comprises:
the method comprises the steps of picking up a waveguide structure by utilizing polydimethylsiloxane or polyvinyl alcohol, aligning the waveguide structure with a region to be transferred of the structure to be transferred under a microscope, and bonding the waveguide structure with the region to be transferred based on Van der Waals force to obtain the light quantum chip.
Furthermore, the quantum dot layer comprises a first gallium arsenide layer, an indium gallium arsenide layer arranged on the first gallium arsenide layer and a second gallium arsenide layer arranged on the indium gallium arsenide layer; or;
the quantum dot layer comprises a first indium phosphide layer, an indium arsenide layer arranged on the first indium phosphide layer and a second indium phosphide layer arranged on the indium arsenide layer; or;
the quantum dot layer comprises a first AlGaAs layer, a GaAs layer arranged on the first AlGaAs layer and a second AlGaAs layer arranged on the GaAs layer.
Further, the structure to be transferred includes:
the substrate is made of silicon.
Further, the structure to be transferred includes:
the lower cladding is arranged on the substrate, and the region to be transferred is arranged on the lower cladding;
the material of the lower cladding is silicon oxide.
The method further comprises the following steps:
preparing a region to be transferred, comprising:
and exposing and etching the structure to be etched in the region to be transferred by utilizing electron beam exposure, inductively coupled plasma etching or reactive ion etching to obtain the region to be transferred comprising the silicon carbide photon loop in the region to be transferred.
Further, the etching process is performed on the structure to be etched, so that the waveguide structure is formed on the quantum dot layer, and the method comprises the following steps:
and exposing and etching the structure to be etched by utilizing electron beam exposure, inductive coupling plasma etching or reactive ion etching, so that the waveguide structure is formed on the quantum dot layer.
Further, the structure to be etched includes:
a substrate;
and a sacrificial layer disposed on the substrate, the quantum dot layer being disposed on the sacrificial layer.
Further, after the etching process is performed on the structure to be etched, the method further includes:
and corroding the structure to be etched, and removing the sacrificial layer to obtain the waveguide structure.
Correspondingly, the embodiment of the application provides a structure of a hybrid integrated optical quantum chip, which comprises:
a substrate, a first electrode and a second electrode,
a lower cladding layer disposed on the substrate;
the region to be transferred is arranged on the lower cladding; the region to be transferred is a silicon carbide photonic circuit;
the quantum dot film is arranged on the area to be transferred; the quantum dot film comprises a first gallium arsenide layer, an indium gallium arsenide layer arranged on the first gallium arsenide layer and a second gallium arsenide layer arranged on the indium gallium arsenide layer; or;
the quantum dot film comprises a first indium phosphide layer, an indium arsenide layer arranged on the first indium phosphide layer and a second indium phosphide layer arranged on the indium arsenide layer; or;
the quantum dot layer comprises a first AlGaAs layer, a GaAs layer arranged on the first AlGaAs layer and a second AlGaAs layer arranged on the GaAs layer.
The embodiment of the application has the following beneficial effects:
the preparation method of the hybrid integrated optical quantum chip disclosed by the embodiment of the application comprises the steps of obtaining a structure to be etched and a structure to be transferred, wherein the structure to be etched comprises a quantum dot layer, the structure to be transferred comprises a region to be transferred, and then the structure to be etched is etched, so that a waveguide structure is formed on the quantum dot layer, and then the waveguide structure is picked up by a polymer and transferred to the region to be transferred of the structure to be transferred, so that the optical quantum chip is obtained. Based on the application, the polymer is used for picking up the waveguide structure and is transferred to the region to be transferred of the structure to be transferred, so that the light quantum chip is obtained, the coupling efficiency can be improved, and the size of the chip is reduced.
Drawings
In order to more clearly illustrate the technical solutions and advantages of the embodiments of the present application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a hybrid integrated optical quantum chip according to an embodiment of the present application;
fig. 2 is a schematic diagram of a method for manufacturing a hybrid integrated optical quantum chip according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a hybrid integrated optical quantum chip provided in an embodiment of the present application;
fig. 4 is a second-order correlation test chart of a pulsed light excitation quantum dot for an optical quantum chip according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings. It should be apparent that the described embodiment is only one embodiment of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
An "embodiment" as referred to herein relates to a particular feature, structure, or characteristic that may be included in at least one implementation of the present application. In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", and the like refer to orientations or positional relationships based on those shown in the drawings, and are used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the device/system or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application. The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than described or illustrated herein. Furthermore, the terms "comprising," "having," and "being," as well as any variations thereof, are intended to cover non-exclusive inclusions.
The following describes a specific embodiment of a method for manufacturing a hybrid integrated optical quantum chip, fig. 1 is a schematic flow chart of a method for manufacturing a hybrid integrated optical quantum chip provided in an embodiment of the present application, and fig. 2 is a schematic diagram of a method for manufacturing a hybrid integrated optical quantum chip provided in an embodiment of the present application. The order of steps recited in the embodiments is only one of many possible orders of execution and does not represent the only order of execution, and in actual execution, the steps may be performed sequentially or in parallel as in the embodiments or methods shown in the figures (e.g., in the context of parallel processors or multi-threaded processing). Specifically, as shown in fig. 1 and 2, the preparation method may include:
s101: obtaining a structure to be etched and a structure to be transferred; the structure to be etched comprises a quantum dot layer; the structure to be transferred includes a region to be transferred.
In the embodiment of the application, the structure to be etched may include a substrate, a sacrificial layer, and a quantum dot layer, wherein the sacrificial layer may be disposed on the substrate, and the quantum dot layer may be disposed on the sacrificial layer.
In an alternative embodiment, the quantum dot layer may include a first gallium arsenide layer GaAs, an indium gallium arsenide layer InGaAs disposed on the first gallium arsenide layer, and a second gallium arsenide layer GaAs disposed on the indium gallium arsenide layer. That is, the InGaAs layer may be embedded in the GaAs layer. The quantum dot layer may include a first indium phosphide layer InP, an indium arsenide layer InAs disposed on the first indium phosphide layer, and a second indium phosphide layer InP disposed on the indium arsenide layer. That is, the InAs layer may be embedded in the InP layer. The quantum dot layer may include a first aluminum gallium arsenide layer AlGaAs, a gallium arsenide layer GaAs disposed on the first aluminum gallium arsenide layer, and a second aluminum gallium arsenide layer AlGaAs disposed on the gallium arsenide layer. That is, the GaAs layer may be embedded in the AlGaAs layer, alternatively, the GaAs layer may be less than 10nm thick, and the quantum dot layer may be within the interval [50nm,500nm ] thick. The quantum dot layer may have other structures, and the embodiments of the present application are not particularly limited.
In an alternative embodiment, the material of the substrate may be gallium arsenide GaAs or indium phosphide InP, and the material of the substrate may also be other materials, which is not specifically limited in the examples of the present application.
In an alternative embodiment, the material of the sacrificial layer may be AlGaAs and the material of the sacrificial layer may be InGaAs. The material of the sacrificial layer may also be other materials, and the embodiment of the present application is not particularly limited.
In an embodiment of the present application, the structure to be transferred may include a substrate, a lower cladding layer, and a region to be transferred, where the lower cladding layer may be disposed on the substrate, and the region to be transferred may be disposed on the lower cladding layer.
In an alternative mode, the region to be transferred may include a silicon carbide SiC photonic circuit, and the region to be transferred may also include lithium niobate LiNbO3The photon loop, the region to be transferred can also comprise silicon nitride Si3N4A photonic loop. The region to be transferred may also include a photonic circuit made of other materials, and the embodiment of the present application is not particularly limited.
In an alternative manner, the material of the substrate may be silicon, and the material of the substrate may also be other materials, which are not specifically limited in this embodiment. The material of the lower cladding layer may be silicon oxide, and may also be other materials with low refractive index relative to the region to be transferred, and the embodiment of the present application is not particularly limited.
Optionally, the structure to be transferred may include a silicon layer, a silicon dioxide layer disposed on the silicon layer, and a silicon carbide layer disposed on the silicon dioxide layer, and since silicon carbide has a third-order nonlinear effect, the modulation and response rate of the finally obtained optical quantum chip may be improved.
S103: and etching the structure to be etched to form the waveguide structure on the quantum dot layer.
In the embodiment of the application, the structure to be etched can be exposed and etched in the modes of electron beam exposure and inductively coupled plasma etching, so that the waveguide structure is formed on the quantum dot layer.
In an alternative embodiment, the structure to be etched may be exposed and etched by using electron beam exposure and reactive ion etching, so that the waveguide structure is formed in the quantum dot layer. When the quantum dot layer comprises a first gallium arsenide layer GaAs, an indium gallium arsenide layer InGaAs arranged on the first gallium arsenide layer and a second gallium arsenide layer GaAs arranged on the indium gallium arsenide layer, a GaAs waveguide structure containing InGaAs quantum dots can be prepared.
In the embodiment of the application, the structure to be etched can be exposed and etched based on electron beam exposure, inductive coupling ion etching or reactive ion etching, after the quantum dot layer forms the waveguide structure, the structure to be etched can be corroded, the sacrificial layer is removed, and the waveguide structure is obtained. Optionally, the etching treatment may be performed on the structure to be etched by using a chemical wet etching method, so as to remove the sacrificial layer and complete suspension of the GaAs waveguide structure.
S105: and picking up the waveguide structure by using the polymer, and transferring the waveguide structure to a region to be transferred of the structure to be transferred to obtain the light quantum chip.
In the embodiment of the application, a waveguide structure can be picked up by using polydimethylsiloxane or polyvinyl alcohol, the waveguide structure is aligned with a region to be transferred of the structure to be transferred under a microscope, and the waveguide structure is bonded with the region to be transferred based on van der waals force, so that the optical quantum chip is obtained. Optionally, the waveguide structure can be taken down from the gallium arsenide substrate by utilizing high polymers such as polydimethylsiloxane PDMS or polyvinyl alcohol PVA with certain viscosity, after the alignment of the waveguide structure and the silicon carbide photonic circuit is realized under a high power microscope, the high polymers are slowly lifted, the waveguide structure is released, the bonding of the waveguide structure and the photonic circuit of the 4H-SiCOI is completed through Van der Waals force, and the hybrid integration of a high-performance quantum light source and a reliable photon forming circuit on a single chip can be realized.
By adopting the preparation method of the hybrid integrated optical quantum chip provided by the embodiment of the application, the transfer bonding from the GaAs waveguide structure to the photonic loop of the 4H-SiCOI is realized by using the polymer, the coupling efficiency can be improved, and the volume of the chip can be reduced.
The embodiment of the present application further provides a structure of a hybrid integrated optical quantum chip, fig. 3 is a schematic structural diagram of the hybrid integrated optical quantum chip provided in the embodiment of the present application, and as shown in fig. 3, the hybrid integrated optical quantum chip may include:
a substrate (100) is provided on which,
a lower cladding layer 200, the lower cladding layer 200 may be disposed on the substrate 100;
a region to be transferred 300, the region to be transferred 300 may be disposed on the lower cladding layer 200; the material of the region to be transferred 300 may be silicon carbide.
In an alternative embodiment, the quantum dot layer may include a first gallium arsenide layer GaAs, an indium gallium arsenide layer InGaAs disposed on the first gallium arsenide layer, and a second gallium arsenide layer GaAs disposed on the indium gallium arsenide layer. That is, the InGaAs layer may be embedded in the GaAs layer. The quantum dot layer may include a first indium phosphide layer InP, an indium arsenide layer InAs disposed on the first indium phosphide layer, and a second indium phosphide layer InP disposed on the indium arsenide layer. That is, the InAs layer may be embedded in the InP layer. The quantum dot layer may include a first aluminum gallium arsenide layer AlGaAs, a gallium arsenide layer GaAs disposed on the first aluminum gallium arsenide layer, and a second aluminum gallium arsenide layer AlGaAs disposed on the gallium arsenide layer. That is, the GaAs layer may be embedded in the AlGaAs layer, alternatively, the GaAs layer may be less than 10nm thick, and the quantum dot layer may be within the interval [50nm,500nm ] thick. The quantum dot layer may have other structures, and the embodiments of the present application are not particularly limited.
Fig. 4 is a second-order correlation test chart of a pulsed light excitation quantum dot for an optical quantum chip according to an embodiment of the present disclosure. Based on fig. 4, it can be obtained that the quantum dots can be excited as needed by controlling the delay time.
By adopting the hybrid integrated optical quantum chip provided by the embodiment of the application, the modulation and response rate of the finally obtained optical quantum chip can be improved based on the Kerr effect of the silicon carbide, so that the hybrid integrated optical quantum chip is suitable for ultra-fast and wide-bandwidth data transmission.
The preparation method comprises the steps of obtaining a structure to be etched and a structure to be transferred, wherein the structure to be etched comprises a quantum dot layer, the structure to be transferred comprises a region to be transferred, the structure to be etched is etched to form a waveguide structure on the quantum dot layer, and then the waveguide structure is picked up by a polymer and transferred to the region to be transferred of the structure to be transferred to obtain the optical quantum chip. Based on the application, the polymer is used for picking up the waveguide structure and is transferred to the region to be transferred of the structure to be transferred, so that the light quantum chip is obtained, the coupling efficiency can be improved, and the size of the chip is reduced.
In the present invention, unless otherwise expressly stated or limited, the terms "connected" and "connected" are to be construed broadly, e.g., as meaning either a fixed connection or a removable connection, or an integral part; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
It should be noted that: the foregoing sequence of the embodiments of the present application is for description only and does not represent the superiority and inferiority of the embodiments, and the specific embodiments are described in the specification, and other embodiments are also within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in the order of execution in different embodiments and achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown or connected to enable the desired results to be achieved, and in some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment is described with emphasis on differences from other embodiments. In particular, for the structural embodiment, since it is based on the method embodiment, the description is simple, and the relevant points can be referred to the partial description of the method embodiment.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (11)
1. A preparation method of a hybrid integrated light quantum chip is characterized by comprising the following steps:
obtaining a structure to be etched and a structure to be transferred; the structure to be etched comprises a quantum dot layer; the structure to be transferred comprises a region to be transferred;
etching the structure to be etched to form a waveguide structure on the quantum dot layer;
and picking up the waveguide structure by using a polymer, and transferring the waveguide structure to the region to be transferred of the structure to be transferred to obtain the light quantum chip.
2. The method of claim 1, wherein the region to be transferred comprises a silicon carbide photonic circuit.
3. The method according to claim 1, wherein the picking up the waveguide structure by using a polymer and transferring the waveguide structure onto the region to be transferred of the structure to be transferred to obtain a light quantum chip, comprises:
the waveguide structure is picked up by utilizing polydimethylsiloxane or polyvinyl alcohol, the waveguide structure is aligned with the region to be transferred of the structure to be transferred under a microscope, and the waveguide structure is bonded with the region to be transferred based on Van der Waals force, so that the optical quantum chip is obtained.
4. The method of claim 1,
the quantum dot layer comprises a first gallium arsenide layer, an indium gallium arsenide layer arranged on the first gallium arsenide layer and a second gallium arsenide layer arranged on the indium gallium arsenide layer; or;
the quantum dot layer comprises a first indium phosphide layer, an indium arsenide layer arranged on the first indium phosphide layer and a second indium phosphide layer arranged on the indium arsenide layer; or;
the quantum dot layer comprises a first AlGaAs layer, a GaAs layer arranged on the first AlGaAs layer and a second AlGaAs layer arranged on the GaAs layer.
5. The method according to claim 1, wherein the structure to be transferred comprises:
the substrate is made of silicon.
6. The method according to claim 5, wherein the structure to be transferred comprises:
a lower cladding layer disposed on the substrate, the region to be transferred being disposed on the lower cladding layer;
the material of the lower cladding is silicon oxide.
7. The method of claim 2, further comprising:
preparing a region to be transferred, comprising:
and exposing and etching the structure to be etched by utilizing electron beam exposure, inductively coupled plasma etching or reactive ion etching to obtain a region to be transferred comprising the silicon carbide photonic loop.
8. The method of claim 1, wherein the etching the structure to be etched to form a waveguide structure on the quantum dot layer comprises:
and exposing and etching the structure to be etched by using electron beam exposure, inductively coupled plasma etching or reactive ion etching, so that the waveguide structure is formed on the quantum dot layer.
9. The method of claim 1, wherein the structure to be etched comprises:
a substrate;
a sacrificial layer disposed on the substrate, the quantum dot layer disposed on the sacrificial layer.
10. The method according to claim 9, wherein after the etching process is performed on the structure to be etched, the method further comprises:
and corroding the structure to be etched, and removing the sacrificial layer to obtain the waveguide structure.
11. A structure of a hybrid integrated optical quantum chip, comprising:
a substrate, a first electrode and a second electrode,
a lower cladding layer disposed on the substrate;
a region to be transferred disposed on the lower cladding; the region to be transferred comprises a silicon carbide photonic circuit;
the quantum dot thin film is arranged on the region to be transferred; the quantum dot film comprises a first gallium arsenide layer, an indium gallium arsenide layer arranged on the first gallium arsenide layer and a second gallium arsenide layer arranged on the indium gallium arsenide layer; or;
the quantum dot film comprises a first indium phosphide layer, an indium arsenide layer arranged on the first indium phosphide layer and a second indium phosphide layer arranged on the indium arsenide layer; or;
the quantum dot layer comprises a first AlGaAs layer, a GaAs layer arranged on the first AlGaAs layer and a second AlGaAs layer arranged on the GaAs layer.
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