CN114125461B - Universal video coding conversion circuit and universal video coding device - Google Patents
Universal video coding conversion circuit and universal video coding device Download PDFInfo
- Publication number
- CN114125461B CN114125461B CN202111435475.XA CN202111435475A CN114125461B CN 114125461 B CN114125461 B CN 114125461B CN 202111435475 A CN202111435475 A CN 202111435475A CN 114125461 B CN114125461 B CN 114125461B
- Authority
- CN
- China
- Prior art keywords
- point
- computing unit
- odd
- selection signal
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Discrete Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Complex Calculations (AREA)
Abstract
The application discloses general video coding transform circuit and general video coding equipment, transform circuit includes: eight-point odd-line computing unit, sixteen-point odd-line computing unit, thirty-two-point odd-line computing unit, sixty-four-point odd-line computing unit, four-point odd-line cosine computing unit, four-point even-line cosine computing unit, transformation type selecting end, point selecting end, input end and output end; and multiplexing the eight-point odd-line computing unit, the sixteen-point odd-line computing unit, the thirty-two-point odd-line computing unit, the sixty-four-point odd-line computing unit, the four-point odd-line cosine computing unit and the four-point even-line cosine computing unit according to the transformation type selection signal input by the transformation type selection end and the point selection signal input by the point selection end. The circuit can realize the general video coding transformation, and has simple design, easy realization and low research and development cost.
Description
Technical Field
The present invention relates to the field of video encoding and decoding technologies, and in particular, to a general video encoding and transforming circuit and a general video encoding device.
Background
A generic video coding device (Versatile Video Coding, VVC), also known as h.266, is a new generation video codec standard determined by the joint video expert group following advanced video coding (Advanced Video Coding, AVC) and efficient video coding (High Efficiency Video Coding, HEVC). Advanced video coding is also called h.264, and high-efficiency video coding is also called h.265. Similar to the previous standard, VVC adopts a hybrid coding framework based on a block structure, and incorporates intra-and inter-frame prediction, variation coding, entropy coding, and other modules. In addition to the DCT-II transform in HEVC, VVC allows the maximum size of the transform to be 64x64, and introduces two new transform modes DST-VII and DCT-VIII. That is, the transformation circuit of the VVC needs to support 4-point, 8-point, 16-point, 32-point, 64-point DCT-II transformation, 4-point, 8-point, 16-point, 32-point DCT-VIII transformation, and 4-point, 8-point, 16-point, 32-point DST-VII transformation. Wherein DCT is discrete cosine transform (Discrete Cosine Transform), DCT-II is second type discrete cosine transform, DCT-VIII is eighth type discrete cosine transform, and DST-VII is seventh type discrete sine transform (Discrete sine Transform).
VVC is a new standard that is evolving and is constantly improving, and because of differences in transform size and type, previous work on HEVC transforms cannot be directly applied to VVC transforms. Some researches are made on the basis of the existing HEVC (high efficiency video coding) transformation, for example, in the existing general video coding equipment design scheme, a 4-32-point DCT-II transformation module of the existing HEVC is not modified, a 4-32-point DCT-VIII transformation module, a 4-32-point DST-VII transformation module and a 64-point DCT-II transformation module are directly added, but the circuit area of a general video coding equipment is greatly increased due to the design; or, the existing 4-32 point DCT-II conversion module of HEVC is not modified, only 64 point DCT-II conversion modules are added, and the 4-32 point DCT-VIII and 4-32 point DST-VII are multiplexed to 64 point DCT-II conversion modules, but the design scheme has large design difficulty and high research and development cost.
Disclosure of Invention
In view of the above, the present application proposes a general video coding conversion circuit and a general video coding apparatus.
The embodiment of the application provides a general video coding conversion circuit, which comprises:
eight-point odd-line computing unit, sixteen-point odd-line computing unit, thirty-two-point odd-line computing unit, sixty-four-point odd-line computing unit, four-point odd-line cosine computing unit, four-point even-line cosine computing unit, transformation type selecting end, point selecting end, input end for inputting residual matrix and transformation coefficient matrix and output end for outputting video coding result;
the transformation type selection end is used for inputting a transformation type selection signal, and the point selection end is used for inputting a point selection signal so that the eight-point odd-line computing unit, the sixteen-point odd-line computing unit, the thirty-two-point odd-line computing unit, the sixty-four-point odd-line computing unit, the four-point odd-line cosine computing unit and the four-point even-line cosine computing unit are multiplexed in the video coding transformation computing according to the transformation type selection signal and the point selection signal.
The general video coding conversion circuit according to the embodiment of the present application, the eight-point odd-line computing unit, the sixteen-point odd-line computing unit, the thirty-two-point odd-line computing unit and the sixty-four-point odd-line computing unit each include a plurality of four-point odd-line computing units, each four-point odd-line computing unit includes a plurality of selectors, and one end of each selector is configured to receive the conversion type selection signal.
According to the universal video coding conversion circuit, the eight-point odd-line computing units comprise 4 four-point odd-line computing units, the sixteen-point odd-line computing units comprise 8 four-point odd-line computing units, the thirty-two-point odd-line computing units comprise 16 four-point odd-line computing units, and the sixty-four-point odd-line computing units comprise 32 four-point odd-line computing units.
The general video coding conversion circuit according to the embodiment of the present application, the four-point odd-line computing unit further includes: a plurality of first subtractors, a plurality of first multipliers and a plurality of first adders;
each first subtracter is used for performing first subtraction operation on two residual elements of the residual matrix and inputting the result of the first subtraction operation to a corresponding selector;
each first multiplier is used for performing a first multiplication operation on a selection result output by the corresponding selector and a coefficient value of the transformation coefficient matrix;
each first adder is configured to perform a first addition operation on multiplication results of the two first multiplication operations.
The universal video coding conversion circuit according to the embodiment of the application, the four-point odd-numbered line computing unit comprises 2 first subtractors, 4 selectors, 4 first multipliers and 2 first adders.
The universal video coding conversion circuit according to the embodiment of the application, the four-point odd-numbered line computing unit comprises 4 first subtractors, 4 selectors, 4 first multipliers and 2 first adders.
The universal video coding conversion circuit of the embodiment of the application, wherein the four-point even-numbered row cosine calculating unit comprises 2 second adders, 2 second multipliers, 1 third adder and 1 second subtracter;
each second adder is used for performing second addition operation on two residual elements of the residual matrix;
each second multiplier is configured to perform a second multiplication operation on a result of the second addition operation output by the corresponding second adder and a coefficient value of the transform coefficient matrix;
the third adder is used for performing third addition operation on multiplication results of the two second multiplication operations;
the second subtracter is used for performing a second subtraction operation on multiplication results of the two second multiplication operations.
The universal video coding conversion circuit of the embodiment of the application, the four-point odd-numbered line cosine calculating unit comprises a plurality of fourth adders, a plurality of third multipliers and a plurality of third subtractors;
each third subtracter is used for performing third subtraction operation on two residual error elements of the residual error matrix;
each third multiplier is configured to perform a third multiplication operation on a result of the third subtraction operation output by the corresponding third subtractor and a coefficient value of the transform coefficient matrix;
each fourth adder is configured to perform a fourth addition operation on the multiplication result of the two third multiplication operations.
The general video coding conversion circuit according to the embodiment of the present application, wherein the conversion type selection signal includes at least one of a DCT-II type selection signal, a DST-VII type selection signal, and a DCT-VIII type selection signal;
the dot number selection signal includes at least one of a four-dot selection signal, an eight-dot selection signal, a sixteen-dot selection signal, a thirty-two-dot selection signal, and a sixty-four-dot selection signal.
The embodiment of the application also comprises a universal video coding device which comprises the universal video coding conversion circuit.
The video coding method comprises an eight-point odd-line computing unit, a sixteen-point odd-line computing unit, a thirty-two-point odd-line computing unit, a sixty-four-point odd-line computing unit, a four-point odd-line cosine computing unit, a four-point even-line cosine computing unit, a transformation type selecting end, a point selecting end, an input end for inputting a residual error matrix and a transformation coefficient matrix and an output end for outputting video coding results; the transformation type selection end is used for inputting a transformation type selection signal, and the point selection end is used for inputting a point selection signal so as to realize multiplexing of an eight-point odd-line calculation unit, a sixteen-point odd-line calculation unit, a thirty-two-point odd-line calculation unit, a sixty-four-point odd-line calculation unit, a four-point odd-line cosine calculation unit and a four-point even-line cosine calculation unit according to the transformation type selection signal and the point selection signal. The universal video coding circuit provided by the application can realize universal video coding transformation, and has the advantages of simple circuit design, easy realization and low research and development cost.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are required for the embodiments will be briefly described, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope of the present invention. Like elements are numbered alike in the various figures.
Fig. 1 shows a schematic structural diagram of a general video coding conversion circuit according to an embodiment of the present application;
fig. 2 shows a schematic structural diagram of a four-point odd-numbered row calculation unit according to an embodiment of the present application;
fig. 3 shows a schematic structural diagram of another four-point odd-numbered row calculation unit according to an embodiment of the present application;
fig. 4 shows a schematic structural diagram of a four-point even-numbered row cosine calculating unit according to an embodiment of the present application;
fig. 5 shows a schematic structural diagram of a four-point odd-numbered row cosine calculating unit according to an embodiment of the present application;
fig. 6 shows a schematic structural diagram of another four-point odd-numbered row cosine calculating unit according to an embodiment of the present application;
fig. 7 shows a schematic structural diagram of an eight-point even-numbered row cosine calculating unit according to an embodiment of the present application;
fig. 8 shows a schematic structural diagram of an eight-point odd-numbered row calculation unit according to an embodiment of the present application;
fig. 9 shows a schematic structural diagram of another eight-point odd-numbered row calculating unit according to the embodiment of the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
The terms "comprises," "comprising," "including," or any other variation thereof, are intended to cover a specific feature, number, step, operation, element, component, or combination of the foregoing, which may be used in various embodiments of the present invention, and are not intended to first exclude the presence of or increase the likelihood of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the invention belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is the same as the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in connection with the various embodiments of the invention.
The input of the general video coding conversion circuit is a residual matrix, and the residual matrix is obtained by subtracting predicted values from original YUV pixels, because most images contain more flat areas with slow content conversion, the image energy can be converted into relatively concentrated distribution of a conversion domain from the dispersed distribution of the spatial domain through conversion coding calculation: the low frequency components in the transformed coefficients are concentrated in the upper left corner of the block and the high frequency components are concentrated in the lower right corner of the block. Therefore, the purpose of further removing the space redundancy can be achieved through the subsequent quantization and entropy coding processes.
From the introduction of the background art, HEVC video coding calculations include 4-point DCT-II, 8-point DCT-II, 16-point DCT-II, and 32-point DCT-II. The VVC video coding includes 64-point DCT-II and 4-point DCT-VIII, 8-point DCT-VIII, 16-point DCT-VIII, 32-point DCT-VIII, 4-point DST-VII, 8-point DST-VII, 16-point DST-VII, and 32-point DST-VII in addition to all the calculations in the HEVC video coding.
In general, the transformation circuit of the VVC needs to support 4-point, 8-point, 16-point, 32-point, 64-point DCT-II, 4-point, 8-point, 16-point, 32-point DCT-VIII, and DST-VII. Wherein the DCT is a discrete cosine transform (Discrete Cosine Transform), the second type discrete cosine transform (DCT-II) is different from the eighth type discrete cosine transform (DCT-VIII) in the corresponding transform coefficient matrix, and the DST is a discrete sine transform (Discrete sine Transform). The one-dimensional DCT-II computation of VVC is exactly the same as HEVC except for the addition of 64-point transforms.
Specifically, the present application obtains a four-point EVEN-number row cosine computing unit (EVEN 4), a four-point ODD-number row cosine computing unit (ODD 4), an eight-point ODD-number row cosine computing unit (ODD 8), a sixteen-point ODD-number row cosine computing unit (ODD 16), a thirty-two-point ODD-number row cosine computing unit (ODD 32), and a sixty-four-point ODD-number row cosine computing unit (ODD 64) according to a symmetric disassembly matrix multiplication operation of the DCT-II transform coefficient matrix.
According to the inclusion characteristics of the DCT-II transform coefficient matrix, an eight-point EVEN row cosine calculation unit (EVEN 8) can be implemented by EVEN4+ODD4, a sixteen-point EVEN row cosine calculation unit (EVEN 16) can be implemented by EVEN8+ODD8, a thirty-two-point EVEN row cosine calculation unit (EVEN 32) can be implemented by EVEN16+ODD16, and a sixty-four-point EVEN row cosine calculation unit (EVEN 64) can be implemented by EVEN 32+ODD32.
Referring to fig. 1, the present application shows a general video coding conversion circuit including: eight-point odd-line computing unit, sixteen-point odd-line computing unit, thirty-two-point odd-line computing unit, sixty-four-point odd-line computing unit, four-point even-line cosine computing unit, four-point odd-line cosine computing unit, transformation type selecting end, point selecting end, input end for inputting residual matrix and transformation coefficient matrix and output end for outputting video coding result.
The video coding method comprises the steps of inputting a transformation type selection signal by a transformation type selection end, and enabling an eight-point odd-line computing unit, a sixteen-point odd-line computing unit, a thirty-two-point odd-line computing unit, a sixty-four-point odd-line computing unit, a four-point odd-line cosine computing unit and a four-point even-line cosine computing unit to be multiplexed in video coding transformation computation according to the transformation type selection signal and the point selection signal.
The general video coding circuit provided by the application can realize VVC video coding transformation, namely, a transformation type selection signal input by a transformation type selection end of the general video coding circuit can be at least one of DCT-II type selection signal, DST-VII type selection signal and DCT-VIII type selection signal, and a point selection signal input by a point selection end of the general video coding circuit can be at least one of four-point selection signal, eight-point selection signal, sixteen-point selection signal, thirty-two-point selection signal and sixty-four-point selection signal.
The following describes the multiplexing process of each module of the universal video coding conversion circuit in the VVC video coding process by way of example:
for example, in the calculation process of the 64-point DCT-II, the type selection signal of the transformation type selection end is DCT-II, the point selection signal input by the point selection end is 64 points, and the calculation units required for determining according to the type selection signal and the point selection signal comprise sixty-four point odd-line calculation units, thirty-two point odd-line calculation units, sixteen point odd-line calculation units, eight point odd-line calculation units, four point odd-line cosine calculation units and four point even-line cosine calculation units.
In the calculation process of the 32-point DCT-II, a type selection signal of the transformation type selection end is DCT-II, a point selection signal input by the point selection end is 32 points, and a calculation unit required for determining according to the type selection signal and the point selection signal comprises a thirty-two point odd-numbered line calculation unit, a sixteen point odd-numbered line calculation unit, an eight point odd-numbered line calculation unit, a four point odd-numbered line cosine calculation unit and a four point even-numbered line cosine calculation unit.
In the calculation process of the 16-point DCT-II, a type selection signal of the transformation type selection end is DCT-II, a point selection signal input by the point selection end is 16 points, and a calculation unit required for determining according to the type selection signal and the point selection signal comprises a sixteen-point odd-line calculation unit, an eight-point odd-line calculation unit, a four-point odd-line cosine calculation unit and a four-point even-line cosine calculation unit.
In the calculation process of the 8-point DCT-II, a type selection signal of the transformation type selection end is DCT-II, a point selection signal input by the point selection end is 8 points, and calculation units required for determining according to the type selection signal and the point selection signal comprise an eight-point odd-line calculation unit, a four-point odd-line cosine calculation unit and a four-point even-line cosine calculation unit.
In the calculation process of the 4-point DCT-II, the type selection signal of the transformation type selection end is DCT-II, the point selection signal input by the point selection end is 4 points, and the calculation units required for determining according to the type selection signal and the point selection signal comprise four-point odd-numbered row cosine calculation units and four-point even-numbered row cosine calculation units.
In the calculation process of the 32-point DST-VII, the type selection signal of the transformation type selection end is DST-VII, the point selection signal input by the point selection end is 32 points, and the calculation unit required for determining according to the type selection signal and the point selection signal comprises sixty-four point odd-line calculation units.
In the calculation process of the 16-point DST-VII, the type selection signal of the transformation type selection end is DST-VII, the point selection signal input by the point selection end is 16 points, and the calculation unit required for determining according to the type selection signal and the point selection signal comprises a 32-point odd-line calculation unit.
In the calculation process of the 8-point DST-VII, the type selection signal of the transformation type selection end is DST-VII, the point selection signal input by the point selection end is 8 points, and the calculation unit required for determining according to the type selection signal and the point selection signal comprises 16 points of odd-numbered row calculation units.
In the calculation process of the 4-point DST-VII, the type selection signal of the transformation type selection end is DST-VII, the point selection signal input by the point selection end is 4 points, and the calculation unit required for determining according to the type selection signal and the point selection signal comprises an 8-point odd-line calculation unit.
In the calculation process of the 32-point DCT-VIII, the type selection signal of the transformation type selection end is DCT-VIII, the point selection signal input by the point selection end is 32 points, and the calculation unit required for determining according to the type selection signal and the point selection signal comprises sixty-four point odd-line calculation units.
In the calculation process of the 16-point DCT-VIII, the type selection signal of the transformation type selection end is DCT-VIII, the point selection signal input by the point selection end is 16 points, and the calculation unit required for determining according to the type selection signal and the point selection signal comprises a 32-point odd-line calculation unit.
In the calculation process of the 8-point DCT-VIII, the type selection signal of the transformation type selection end is DCT-VIII, the point selection signal input by the point selection end is 8 points, and the calculation unit required for determining according to the type selection signal and the point selection signal comprises 16-point odd-line calculation units.
In the calculation process of the 4-point DCT-VIII, the type selection signal of the transformation type selection end is DCT-VIII, the point selection signal input by the point selection end is 4 points, and the calculation unit required for determining according to the type selection signal and the point selection signal comprises an 8-point odd-line calculation unit.
In a specific video coding process, after the required calculation units are determined according to the type selection signals and the point selection signals, a residual matrix and a transformation coefficient matrix of an input end can be obtained, the determined calculation units are input into the calculation units to perform corresponding calculation, a video coding result is obtained, and the video coding result is output to an output end, wherein different transformation types correspond to different transformation coefficient matrixes.
Further, in the general video coding conversion circuit, the eight-point odd-line computing unit, the sixteen-point odd-line computing unit, the thirty-two-point odd-line computing unit and the sixty-four-point odd-line computing unit each include a plurality of four-point odd-line computing units, the four-point odd-line computing units include a plurality of selectors, and one end of each selector is configured to receive the conversion type selection signal.
Further, the eight-point odd line computing unit includes 4 four-point odd line computing units, the sixteen-point odd line computing unit includes 8 four-point odd line computing units, the thirty-two-point odd line computing unit includes 16 four-point odd line computing units, and the sixty-four-point odd line computing unit includes 32 four-point odd line computing units.
Further, the four-dot odd-numbered line calculating unit includes, in addition to a plurality of selectors: a plurality of first subtractors, a plurality of first multipliers and a plurality of first adders; each first subtracter is used for performing first subtraction operation on two residual elements of the residual matrix and inputting the result of the first subtraction operation to a corresponding selector; each first multiplier is used for performing a first multiplication operation on a selection result output by the corresponding selector and a coefficient value of the transformation coefficient matrix; each first adder is configured to perform a first addition operation on multiplication results of the two first multiplication operations.
Illustratively, taking the DCT-II transform of the residual matrix of 4*4 as an example, the transform coefficient matrix of the DCT-II transform is known
If the input residual matrix is +.>
The two-dimensional DCT-II transformation calculation formula is Y=AXA ' = (X ' A ') ' A ', the one-dimensional row transformation and the one-dimensional column transformation are unified into a matrix multiplication form of X ' A ', and the same circuit can be multiplexed in a time-sharing way, so that only the circuit for one-dimensional transformation is designed. Y0, y1, y2, and y3 of row 0 of the matrix multiplication result are y0=64 (x0+x3) +64 (x1+x2), y1=83 (x0-x3) +36 (x 1-x 2), y2=64 (x0+x3) -64 (x1+x2), y3=36 (x0-x3) -83 (x 1-x 2), respectively; the results of rows 1 to 3 can be obtained by replacing x0 to x3 with x4 to x7, x8 to x11, and x12 to x 15.
It can be appreciated that the 4-point DST-VII transform coefficient matrix is
The 4-point DCT-VIII transformation coefficient matrix is +.>
Based on the above transformation calculation formula, in order that the eight-point odd-line calculation unit, the sixteen-point odd-line calculation unit, the thirty-two-point odd-line calculation unit, and the sixty-four-point odd-line calculation unit may perform any one of the transformations of DCT-II, DST-VII, and DCT-VIII, an embodiment of the present application, please refer to fig. 2, proposes a four-point odd-line calculation unit composed of 4 first subtractors (J11, J12, J13, J14), 4 selectors (Xz 1, xz2, xz3, xz 4), 4 first multipliers (X11, X12, X13, X14), and 2 first adders (G11 and G12).
Further, considering that the residual elements input by the first subtractor J11 and the third first subtractor J13 shown in fig. 2 are the same, the residual elements input by the second first subtractor J12 and the fourth first subtractor J14 are the same, and thus, the use of the first subtractors can be reduced.
For example, referring to fig. 3, an embodiment of the present application proposes a four-point odd-line computing unit composed of 2 first subtractors (J11, J12), 4 selectors (Xz 1, xz2, xz3, xz 4), 4 first multipliers (X11, X12, X13, X14), and 2 first adders (G11 and G12).
Specifically, each selector in each four-point odd-numbered row calculation unit includes a transformation type selection terminal (is-dct 2), each selector is used for controlling an output terminal of the selector to output information received by a first receiving terminal of the selector or information received by a second receiving terminal of the selector according to a transformation type selection signal received by the transformation type selection terminal (is-dct 2), and each multiplier is used for performing transformation calculation of a corresponding transformation type according to a transformation matrix coefficient value received by another input terminal.
For example, when the transform type selection signal input from the transform type selection terminal (is_dct 2) in fig. 3 is 1, the output terminals of Xz1 and Xz3 output the information received by the respective first receiving terminals 1 (i.e., the difference between x0 and x 3), and the output terminals of Xz2 and Xz4 output the information received by the respective first receiving terminals 1 (i.e., the difference between x1 and x 2) to perform DCT-II transform based on the output information of the output terminals of the respective selectors and the input transform matrix coefficients; when the transform type selection signal inputted from the transform type selection terminal (is_dct 2) is 0, the output terminals of Xz1 and Xz3 output the information received by the respective second receiving terminal 0 (i.e., x 0), and the output terminals of Xz2 and Xz4 output the information received by the respective second receiving terminal 0 (i.e., x 1), so as to perform DST-VII transform and/or DCT-VIII transform based on the output information of the output terminal of each selector and the inputted transform matrix coefficient.
Based on the above transform calculation formula, please refer to fig. 4, an embodiment of the present application proposes a four-point even row cosine calculation unit including 2 second adders (G21 and G22), 2 second multipliers (X21 and X22), 1 third adder G31 and 1 second subtractor J21 for performing even row cosine transform in the above calculation, that is, y0=64 (x0+x3) +64 (x1+x2) and y2=64 (x0+x3) -64 (x1+x2).
Each second adder is used for performing second addition operation on two residual elements of the residual matrix; each second multiplier is configured to perform a second multiplication operation on a result of the second addition operation output by the corresponding second adder and a coefficient value of the transform coefficient matrix; the third adder is used for performing third addition operation on multiplication results of the two second multiplication operations; the second subtracter is used for performing a second subtraction operation on multiplication results of the two second multiplication operations.
Based on the above transformation calculation formula, the embodiment of the present application provides a four-point odd-numbered row cosine calculation unit including a plurality of fourth adders, a plurality of third multipliers and a plurality of third subtractors; each third subtracter is used for performing third subtraction operation on two residual error elements of the residual error matrix; each third multiplier is configured to perform a third multiplication operation on a result of the third subtraction operation output by the corresponding third subtractor and a coefficient value of the transform coefficient matrix; each fourth adder is configured to perform a fourth addition operation on the multiplication result of the two third multiplication operations.
For example, referring to fig. 5, the four-point odd-numbered row cosine calculating unit is composed of 2 fourth adders (G41 and G42), 4 third multipliers (X31, X32, X33, X34) and 4 third subtractors (J31, J32, J33, J34) for performing odd-numbered row cosine transforms in the above calculations, that is, y1=83 (X0-X3) +36 (X1-X2) and y3=36 (X0-X3) -83 (X1-X2).
Further, considering that the residual elements input by the first third subtractor J31 and the third subtractor J33 shown in fig. 5 are the same, the residual elements input by the second third subtractor J32 and the fourth third subtractor J34 are the same, the use of the third subtractor can be reduced. Therefore, referring to fig. 6, an embodiment of the present application proposes that a four-point odd-numbered row cosine calculating unit may further be composed of 2 fourth adders (G41 and G42), 4 third multipliers (X31, X32, X33, X34) and 2 third subtractors (J31, J32) for performing odd-numbered row cosine transforms in the above calculations, that is, y1=83 (X0-X3) +36 (X1-X2) and y3=36 (X0-X3) -83 (X1-X2).
It can be understood that the eight-point odd-line computing unit, the sixteen-point odd-line computing unit, the thirty-two-point odd-line computing unit and the sixty-four-point odd-line computing unit are realized through the selector in the eight-point odd-line computing unit, the sixteen-point odd-line computing unit, the thirty-two-point odd-line computing unit and the sixty-four-point odd-line computing unit, any one of DCT-II, DST-VII and DCT-VIII can be selectively transformed, modification can be performed on the basis of the DCT-II circuit of the original HEVC, and the circuit modification is very simple without modifying the multiplier, the adder and the output path of the DCT-II circuit of the original HEVC.
Note that, in the four-point odd-numbered line calculation unit: the transform matrix coefficient values received at the other input of each multiplier vary with the type of transform.
Exemplarily, the transform coefficient matrix of the 8-point DCT-II is known as:
comparing A4 with A8, the first 4 columns of the even rows of A8 are equal to A4, the last 4 columns of the 0 th row and the 4 th row are equal to the first 4 columns, and the last 4 columns of the 2 nd row and the 6 th row are equal to the first 4 columns in number and have opposite signs.
Therefore, the four-point EVEN-line cosine calculation unit (EVEN 4) and the four-point ODD-line cosine calculation unit (ODD 4) can be used to perform DCT-II transform on EVEN lines of the residual matrix of 8×8, that is, two four-point EVEN-line cosine calculation units (EVEN 4) and two four-point ODD-line cosine calculation units (ODD 4) can be combined into eight-point EVEN-line cosine calculation unit (EVEN 8), that is, y0=64 (x0+x3) +64 (x1+x2) +64 (x4+x7) +64 (x5+x6) corresponding to a first EVEN line of the residual matrix of 8×8, y2=83 (x 0-x3) +36 (x 1-x 2) +83 (x 4-x 7) +36 (x 5-x 6), and y4=64 (x3) -64 (x1+x2) +64 (x6) -64 (x6) corresponding to a second EVEN line of the residual matrix of 8×8×3+x4+x6), as shown in fig. 3×6×3+6×6×3+3+x 6.
Further, referring to fig. 8, the eight-point ODD-line computing unit composed of 4 four-point ODD-line computing units (ODD 4') may perform DCT-II transform on ODD lines of the 8×8 residual matrix, DCT-VIII transform on ODD lines of the 8×8 residual matrix, and DST-VII transform on ODD lines of the 8×8 residual matrix.
It will be appreciated that, since the inputs corresponding to y1 and y5 are the same, and since the inputs corresponding to y3 and y7 are the same, the four-point ODD-line computing unit (ODD 4 ') corresponding to y5 may multiplex the subtracter of the four-point ODD-line computing unit (ODD 4 ') corresponding to y1, the four-point ODD-line computing unit (ODD 4 ') corresponding to y7 may multiplex the subtracter of the four-point ODD-line computing unit (ODD 4 ') corresponding to y3, two subtractors may be omitted from the four-point ODD-line computing unit (ODD 4 ') corresponding to y5 and y7, and the four-point ODD-line computing unit from which the subtracter is omitted may be denoted as ODD4″ as shown in fig. 9.
Taking the DCT-II transform as an example, the transform matrix coefficient values of the DCT-II transform in the eight-point odd-line computing unit are different from those of the four-point odd-line computing unit, for example, the transform coefficient values of the DCT-II transform in the original four-point odd-line computing unit are [83, 36, 36, -83], whereas in the eight-point odd-line computing unit, the input coefficient matrices of the left two four-point odd-line computing units should be [89, 75, 75, 18] and [50, 18, -89, -50], and the input coefficient matrices of the right two four-point odd-line computing units should be [50, -89, 18, -50] and [18, 75, 75, -89].
It should be noted that, since the eight-point ODD-line computing unit has the function of the eight-point ODD-line cosine computing unit (ODD 8), the eight-point ODD-line cosine computing unit (EVEN 16) can be implemented based on the eight-point EVEN-line cosine computing unit (EVEN 8) shown in fig. 7 and the eight-point ODD-line computing unit shown in fig. 8 (or fig. 9); likewise, the sixteen-point EVEN-numbered line cosine calculating unit (EVEN 16) and the sixteen-point odd-numbered line cosine calculating unit (EVEN 32) can realize the function of thirty-two points EVEN-numbered line cosine calculating unit; the thirty-two point EVEN row cosine calculation unit (EVEN 32) and the thirty-two point odd row calculation unit may implement the function of the sixty-four point EVEN row cosine calculation unit (EVEN 64).
It should be noted that, when the eight-point ODD-numbered line calculation unit shown in fig. 8 (or fig. 9) is used to calculate the 4-point DST-VII, the left two ODDs 4 'calculate the upper two lines, the input transform coefficient matrices should be [29, 55, 74, 74] and [74, 84,0, -74], the right two ODDs 4' (or ODD4 ") calculate the lower two lines, the input transform coefficient matrices should be [84, -29, 55, -84] and [ -74, 55, 74, -29]; similarly, when calculating the 4-point DCT-VIII, the input transform coefficient matrices for the left two ODDs 4 'should be [84, 74, 74,0] and [55, 29, -74, -74], and the input transform coefficient matrices for the right two ODDs 4' (or ODDs 4 ") should be [55, -74, 29, -74] and [ -29, 84, 84, -55].
Similarly, 32-point DCT-VIII/DST-VII may multiplex sixty-four-point odd line computing units, 16-point DCT-VIII/DST-VII may multiplex thirty-two-point odd line computing units, and 8-point DCT-VIII/DST-VII may multiplex sixteen-point odd line computing units.
It can be understood that the universal video coding conversion circuit provided by the application comprises an eight-point odd-line computing unit, a sixteen-point odd-line computing unit, a thirty-two-point odd-line computing unit, a sixty-four-point odd-line computing unit, a four-point odd-line cosine computing unit and a four-point even-line cosine computing unit, a conversion type selecting end, a point selecting end, an input end for inputting a residual matrix and a conversion coefficient matrix and an output end for outputting a video coding result; the transformation type selection end is used for inputting a transformation type selection signal, and the point selection end is used for inputting a point selection signal so as to realize eight-point odd-line computing units, sixteen-point odd-line computing units, thirty-two-point odd-line computing units, sixty-four-point odd-line computing units, four-point odd-line cosine computing units and four-point even-line cosine computing units which are multiplexed in the video coding transformation computation according to the transformation type selection signal and the point selection signal. The video coding circuit is obtained by modifying the DCT-II circuit of the original HEVC, the universal video coding conversion can be realized on the circuit, the circuit is simple in design, easy to realize and low in research and development cost.
Further, the application proposes a general video coding device, which includes the general video coding conversion circuit described in the above embodiments of the application.
In the several embodiments provided in this application, it should be understood that the disclosed circuits and devices may be implemented in other ways. The above-described embodiments are merely illustrative, for example, of the structures in the drawings that show the architecture, functionality, and operation of possible implementations of products according to various embodiments of the present invention. In this regard, each block in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. It will also be noted that each block of the block diagrams, and combinations of blocks in the block diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules or units in various embodiments of the invention may be integrated together to form a single part, or the modules may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned readable storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention.
Claims (10)
1. A universal video coding conversion circuit, the conversion circuit comprising:
eight-point odd-line computing unit, sixteen-point odd-line computing unit, thirty-two-point odd-line computing unit, sixty-four-point odd-line computing unit, four-point odd-line cosine computing unit, four-point even-line cosine computing unit, transformation type selecting end, point selecting end, input end for inputting residual matrix and transformation coefficient matrix and output end for outputting video coding result;
the transformation type selection end is used for inputting a transformation type selection signal, and the point selection end is used for inputting a point selection signal so that the eight-point odd-line computing unit, the sixteen-point odd-line computing unit, the thirty-two-point odd-line computing unit, the sixty-four-point odd-line computing unit, the four-point odd-line cosine computing unit and the four-point even-line cosine computing unit are multiplexed in the video coding transformation computing according to the transformation type selection signal and the point selection signal.
2. The universal video transcoding circuit of claim 1, wherein the eight point odd line computing unit, the sixteen point odd line computing unit, the thirty-two point odd line computing unit and the sixty-four point odd line computing unit each comprise a plurality of four point odd line computing units, the four point odd line computing units comprising a plurality of selectors having one end for receiving the transform type selection signal.
3. The universal video transcoding circuit of claim 2, wherein said eight point odd line computing unit comprises 4 of said four point odd line computing units, said sixteen point odd line computing unit comprises 8 of said four point odd line computing units, said thirty-two point odd line computing unit comprises 16 of said four point odd line computing units, and said sixty-four point odd line computing unit comprises 32 of said four point odd line computing units.
4. The universal video transcoding circuit of claim 2, wherein the four-point odd line computing unit further comprises: a plurality of first subtractors, a plurality of first multipliers and a plurality of first adders;
each first subtracter is used for performing first subtraction operation on two residual elements of the residual matrix and inputting the result of the first subtraction operation to a corresponding selector;
each first multiplier is used for performing a first multiplication operation on a selection result output by the corresponding selector and a coefficient value of the transformation coefficient matrix;
each first adder is configured to perform a first addition operation on multiplication results of the two first multiplication operations.
5. The universal video transcoding circuit of claim 4, wherein said four-point odd line computing unit comprises 2 first subtractors, 4 selectors, 4 first multipliers and 2 first adders.
6. The universal video transcoding circuit of claim 4, wherein said four-point odd line computing unit comprises 4 first subtractors, 4 selectors, 4 first multipliers and 2 first adders.
7. The universal video transcoding circuit of claim 1, wherein said four-point even row cosine calculation unit comprises 2 second adders, 2 second multipliers, 1 third adder and 1 second subtractor;
each second adder is used for performing second addition operation on two residual elements of the residual matrix;
each second multiplier is configured to perform a second multiplication operation on a result of the second addition operation output by the corresponding second adder and a coefficient value of the transform coefficient matrix;
the third adder is used for performing third addition operation on multiplication results of the two second multiplication operations;
the second subtracter is used for performing a second subtraction operation on multiplication results of the two second multiplication operations.
8. The universal video transcoding circuit of claim 1, wherein said four-point odd row cosine calculation unit comprises a plurality of fourth adders, a plurality of third multipliers and a plurality of third subtractors;
each third subtracter is used for performing third subtraction operation on two residual error elements of the residual error matrix;
each third multiplier is configured to perform a third multiplication operation on a result of the third subtraction operation output by the corresponding third subtractor and a coefficient value of the transform coefficient matrix;
each fourth adder is configured to perform a fourth addition operation on the multiplication result of the two third multiplication operations.
9. The universal video coding transform circuit according to any of claims 1 to 8, wherein the transform type selection signal comprises at least one of a DCT-II type selection signal, a DST-VII type selection signal, and a DCT-VIII type selection signal;
the dot number selection signal includes at least one of a four-dot selection signal, an eight-dot selection signal, a sixteen-dot selection signal, a thirty-two-dot selection signal, and a sixty-four-dot selection signal.
10. A universal video encoding device comprising the universal video transcoding circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111435475.XA CN114125461B (en) | 2021-11-29 | 2021-11-29 | Universal video coding conversion circuit and universal video coding device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111435475.XA CN114125461B (en) | 2021-11-29 | 2021-11-29 | Universal video coding conversion circuit and universal video coding device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114125461A CN114125461A (en) | 2022-03-01 |
| CN114125461B true CN114125461B (en) | 2023-07-14 |
Family
ID=80371495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111435475.XA Active CN114125461B (en) | 2021-11-29 | 2021-11-29 | Universal video coding conversion circuit and universal video coding device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114125461B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102714714A (en) * | 2009-06-24 | 2012-10-03 | 高通股份有限公司 | 8-point transform for media data coding |
| CN102857756A (en) * | 2012-07-19 | 2013-01-02 | 西安电子科技大学 | Transfer coder adaptive to high efficiency video coding (HEVC) standard |
| CN107027039A (en) * | 2017-04-14 | 2017-08-08 | 西安电子科技大学 | Discrete cosine transform implementation method based on efficient video coding standard |
| WO2020071736A1 (en) * | 2018-10-01 | 2020-04-09 | 엘지전자 주식회사 | Encoding/decoding method for video signal and device therefor |
| CN113170179A (en) * | 2018-12-21 | 2021-07-23 | 松下电器（美国）知识产权公司 | Encoding device, decoding device, encoding method, and decoding method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001346213A (en) * | 2000-06-02 | 2001-12-14 | Nec Corp | Discrete cosine transform unit and its discrete cosine transform method |
| WO2019235491A1 (en) * | 2018-06-08 | 2019-12-12 | パナソニック インテレクチュアル プロパティ コーポレーション オブ アメリカ | Coding device, decoding device, coding method, and decoding method |
| US20210281842A1 (en) * | 2018-07-08 | 2021-09-09 | Lg Electronics Inc. | Method and apparatus for processing video |
-
2021
- 2021-11-29 CN CN202111435475.XA patent/CN114125461B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102714714A (en) * | 2009-06-24 | 2012-10-03 | 高通股份有限公司 | 8-point transform for media data coding |
| CN102857756A (en) * | 2012-07-19 | 2013-01-02 | 西安电子科技大学 | Transfer coder adaptive to high efficiency video coding (HEVC) standard |
| CN107027039A (en) * | 2017-04-14 | 2017-08-08 | 西安电子科技大学 | Discrete cosine transform implementation method based on efficient video coding standard |
| WO2020071736A1 (en) * | 2018-10-01 | 2020-04-09 | 엘지전자 주식회사 | Encoding/decoding method for video signal and device therefor |
| CN113170179A (en) * | 2018-12-21 | 2021-07-23 | 松下电器（美国）知识产权公司 | Encoding device, decoding device, encoding method, and decoding method |
Non-Patent Citations (1)
| Title |
|---|
| H.264/AVC标准中关键技术的研究;杨奇泽;《中国优秀硕士论文电子期刊》;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114125461A (en) | 2022-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4924904B2 (en) | Efficient encoding / decoding of sequences of data frames | |
| RU2413983C2 (en) | Reversible transformation for lossy or lossless two-dimensional data compression | |
| KR20140053155A (en) | Mode-dependent transforms for residual coding with low latency | |
| US8254700B1 (en) | Optimized method and system for entropy coding | |
| JP3902990B2 (en) | Hadamard transform processing method and apparatus | |
| CN104244010B (en) | Improve the method and digital signal converting method and device of digital signal conversion performance | |
| JP2011504000A (en) | Method of video encoding and decoding | |
| TWI412281B (en) | A Method of Calculating Reverse Conversion of Low Complexity | |
| CN114125461B (en) | Universal video coding conversion circuit and universal video coding device | |
| CN114007079A (en) | Conversion circuit, method, device and encoder | |
| US20030133507A1 (en) | Adaptive inverse transformation device | |
| WO2020060832A1 (en) | Fast implementation of odd one dimensional transforms | |
| US9819969B2 (en) | Generalization of methods and systems for image compression while encoding at least one extra bit | |
| US10432937B2 (en) | Adaptive precision and quantification of a wavelet transformed matrix | |
| JPH10283343A (en) | Data processing method | |
| CN114554225B (en) | Image encoding method, apparatus, device and computer readable medium | |
| JP5546329B2 (en) | Data converter | |
| JP4266512B2 (en) | Data processing device | |
| Vayalil et al. | An efficient ASIC design of variable-length discrete cosine transform for HEVC | |
| CN113068033B (en) | Multimedia inverse quantization processing method, device, equipment and storage medium | |
| JP2006227666A (en) | Matrix operation unit | |
| JP2003030174A (en) | Dct matrix decomposition method and dct device | |
| KR101711495B1 (en) | Reusable DCT Architecture for Parallel Processing of Y, U and V Transforms in HEVC | |
| CN113286150B (en) | Transform coding hardware implementation method, device and equipment for video coding and decoding | |
| JP2006332836A (en) | Orthogonal transformation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |