CN114124357A - Ciphertext generation method based on Fourier series, server, medium and device - Google Patents

Ciphertext generation method based on Fourier series, server, medium and device Download PDF

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CN114124357A
CN114124357A CN202111404963.4A CN202111404963A CN114124357A CN 114124357 A CN114124357 A CN 114124357A CN 202111404963 A CN202111404963 A CN 202111404963A CN 114124357 A CN114124357 A CN 114124357A
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王公桃
叶雪峰
张峤
孙波
吕鹏
李理
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Bank of China Ltd
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    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract

The application discloses a ciphertext generation method, a server, a medium and a device based on Fourier series, which can be applied to the field of block chains or the field of finance. In this application, if the input information is divided into a plurality of data blocks, in the process of calculating the next data block, the identifier H of the buffer corresponding to the next data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4Is the initial value of H obtained for the last data block0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4A final value of; and, the expansion values of 80 fourier series are used instead of the preset 80 constants, so the specific content of the obtained 160-bit ciphertext is related not only to the number of data blocks into which the input information is divided, but also to the 80 expansion values of the fourier series. If violence is brokenAnd if the ciphertext is decoded, the number of the divided data blocks of the input information and 80 expansion values of the Fourier series need to be decoded, so that brute force decoding is more difficult, and the safety of the ciphertext is improved.

Description

Ciphertext generation method based on Fourier series, server, medium and device
Technical Field
The present application relates to the field of block chaining technologies, and in particular, to a method, a server, a medium, and an apparatus for generating a ciphertext based on a fourier series.
Background
SHA-1(Secure Hash Algorithm 1) is a function for generating 160-bit ciphertext and is widely applied in the prior art, but with the continuous development of computer computing capacity, security personnel have successfully broken the SHA-1 Algorithm.
Therefore, how to strengthen the existing SHA-1 is a necessary requirement for the technical development.
Disclosure of Invention
In view of this, the present application provides a ciphertext generation method, a server, a medium, and an apparatus based on a fourier series.
In order to achieve the above purpose, the present application provides the following technical solutions:
according to a first aspect of the embodiments of the present disclosure, a ciphertext generation method based on a fourier series is provided, including:
acquiring input information to be stored to a block chain;
expanding the length complementary bits of the input information into 512 bits x Q to obtain a first message, wherein Q is any integer greater than or equal to 1;
dividing the first message into Q data blocks, wherein the number of bits of the data blocks is 512 bits;
setting the initial value of G to be 1;
the following operations are performed for the G-th data block:
dividing the data block into 16 target sub data blocks, wherein the number of bits of the target sub data blocks is 32;
performing operation on the 16 target sub data blocks to obtain 64 operation sub data blocks so as to obtain 80 sub data blocks, wherein the bit number of the operation sub data blocks is 32 bits, and the 80 sub data blocks comprise the 16 target sub data blocks and the 64 operation sub data blocks;
obtaining preset 80 constants, wherein the values of the 80 constants are as follows:
Ktfirst preset value (0)<＝t<＝19)
KtSecond predetermined value (20)<＝t<＝39)
KtThird preset value (40)<＝t<＝59)
KtFourth preset value (60)<＝t<＝79)；
Fourier series
Figure BDA0003371955540000021
Spreading at x ═ i to obtain spread values f (i), i having values in the order of 1 to 80 to obtain 80 spread values, where a1To a40The values of (A) are as follows: constants of odd number among 80 constants, b, ordered from small to large in position1To b40The values of (A) are as follows: constants positioned at even-numbered positions in the 80 constants are sorted from small to large according to positions;
assigning f (i) to Ki-1；
Obtaining an identity of a buffer H0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
h is to be0Of (d), H1Of (d), H2Of (d), H3Of (d), H4Respectively assigning the initial values to a first parameter, a second parameter, a third parameter, a fourth parameter and a fifth parameter;
setting the initial value of P to be 0;
for t ═ P, the following calculation is performed:
TEMP＝S5(H0)+ft(H1,H2,H3)+H4+Wt+Kt；H4＝H3；H3＝H2；H2＝S30(H1)；H1＝H0；H0TEMP; wherein, WtFor the t +1 th sub-data block of the 80 sub-data blocks, ft(H1,H2,H3) Is a preset function; s5(H0) Means that H is0Left shift by 5; s30(H1) Means that H is1Left shift by 30;
setting P +1, returning to the step for t P, the following calculation is performed until P equals 80 to obtain the identification H of the buffer area0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4A value of (d);
let H0Final value of ═ H0Value of + first parameter, H1Final value of ═ H1Value of + second parameter, H2Final value of ═ H2Value of + third parameter, H3Final value of ═ H3Value of + fourth parameter, H4Final value of ═ H4The value of + the fifth parameter;
subjecting said H to0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4Respectively as the mark H of the buffer corresponding to the G +1 th data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
setting G to G +1, and returning to the step to execute the following operations on the G-th data block until G is larger than Q;
according to H0、H1、H2、H3、H4In the order of (A) and (B), is0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4The 160-bit abstract composed of the final values of the two-bit abstract is determined as a ciphertext;
and storing the ciphertext to a block chain.
According to a second aspect of the embodiments of the present disclosure, there is provided a ciphertext generating apparatus based on a fourier series, including:
the first acquisition module is used for acquiring input information to be stored to the block chain;
a bit-complementing expansion module, configured to expand the length bit-complementing of the input information to 512 bits × Q to obtain a first packet, where Q is any integer greater than or equal to 1;
the first dividing module is used for dividing the first message into Q data blocks, and the bit number of each data block is 512 bits;
the first setting module is used for setting the initial value of G to be 1;
the following operations are performed for the G-th data block:
the second dividing module is used for dividing the data block into 16 target sub data blocks, and the number of bits of each target sub data block is 32;
the operation module is used for performing operation on the 16 target sub data blocks to obtain 64 operation sub data blocks so as to obtain 80 sub data blocks, the bit number of each operation sub data block is 32 bits, and the 80 sub data blocks comprise 16 target sub data blocks and 64 operation sub data blocks;
the second obtaining module is configured to obtain preset 80 constants, where values of the 80 constants are as follows:
Ktfirst preset value (0)<＝t<＝19)
KtSecond predetermined value (20)<＝t<＝39)
KtThird preset value (40)<＝t<＝59)
KtFourth preset value (60)<＝t<＝79)；
An expansion module for expanding the Fourier series
Figure BDA0003371955540000031
Spreading at x ═ i to obtain spread values f (i), i having values in the order of 1 to 80 to obtain 80 spread values, where a1To a40The values of (A) are as follows: constants of odd number among 80 constants, b, ordered from small to large in position1To b40The values of (A) are as follows: bits ordered from small to large according to positionConstants in even-numbered bits of the 80 constants;
a first assigning module for assigning f (i) to Ki-1；
A third obtaining module, configured to obtain an identifier H of the buffer0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
a second assignment module for assigning H0Of (d), H1Of (d), H2Of (d), H3Of (d), H4Respectively assigning the initial values to a first parameter, a second parameter, a third parameter, a fourth parameter and a fifth parameter;
the third assignment module is used for setting the initial value of P to be 0;
a calculation module for performing the following calculation for t ═ P:
TEMP＝S5(H0)+ft(H1,H2,H3)+H4+Wt+Kt；H4＝H3；H3＝H2；H2＝S30(H1)；H1＝H0；H0TEMP; wherein, WtFor the t +1 th sub-data block of the 80 sub-data blocks, ft(H1,H2,H3) Is a preset function; s5(H0) Means that H is0Left shift by 5; s30(H1) Means that H is1Left shift by 30;
a first trigger module, configured to set P +1, and return to the calculation module until P equals 80, so as to obtain an identifier H of the buffer area0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4A value of (d);
a fourth assignment module for ordering H0Final value of ═ H0Value of + first parameter, H1Final value of ═ H1Value of + second parameter, H2Final value of ═ H2Value of + third parameter, H3Final value of ═ H3Value of (A)+ fourth parameter, H4Final value of ═ H4The value of + the fifth parameter;
a fifth assignment module for assigning the H0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4Respectively as the mark H of the buffer corresponding to the G +1 th data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
the second trigger module is used for setting G +1 and returning to the second dividing module until G is larger than Q;
a determination module for following H0、H1、H2、H3、H4In the order of (A) and (B), is0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4The 160-bit abstract composed of the final values of the two-bit abstract is determined as a ciphertext;
and the storage module is used for storing the ciphertext to the block chain.
According to a third aspect of the embodiments of the present disclosure, there is provided a server, including:
a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the Fourier series based ciphertext generation method of the first aspect.
According to a fourth aspect of embodiments of the present disclosure, there is provided a computer-readable storage medium, wherein instructions, when executed by a processor of a server, enable the server to perform the fourier series-based ciphertext generation method of the first aspect.
According to a fifth aspect of the embodiments of the present disclosure, there is provided a computer program product directly loadable into an internal memory of a computer, the memory is a memory included in the server shown in the third aspect and contains software codes, and the computer program can realize the ciphertext generation method based on fourier series according to the first aspect when loaded and executed by the computer.
According to the above technical solution, after 80 preset constants are obtained, the fourier series is expanded at x-i to obtain an expanded value f (i), and values of i are sequentially 1 to 80 to obtain 80 expanded values, where a1To a40The values of (A) are as follows: constants of odd number among 80 constants, b, ordered from small to large in position1To b40The values of (A) are as follows: constants positioned at even-numbered positions in the 80 constants are sorted from small to large according to positions; f (1) to f (80) as 80 constants, and therefore, H is obtained based on f (1) to f (80) as 80 constants0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4And H obtained based on 80 constants set in advance0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4If the input information is divided into a plurality of data blocks, the identifier H of the buffer area corresponding to the next data block is calculated in the next data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4Is the initial value of H obtained for the last data block0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4The final value of (b), i.e., the specific content of the resulting 160-bit ciphertext, is related not only to the number of data blocks into which the input information is divided, but also to the 80 expansion values of the fourier series. If brute force cracking is needed, the number of the divided data blocks of the input information needs to be cracked, and 80 expansion values of the Fourier series need to be cracked.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a block chain apparatus according to an embodiment of the present disclosure;
fig. 2 is a block chain structure diagram provided in an embodiment of the present application;
fig. 3 is a flowchart of a ciphertext generation method based on fourier series according to an embodiment of the present application;
fig. 4a to 4c are schematic diagrams illustrating the input information bit complement expansion provided in the embodiment of the present application;
FIG. 5 is a schematic diagram of the data block being divided into 16 target sub data blocks;
fig. 6 is a structural diagram of a ciphertext generating apparatus based on fourier series according to an embodiment of the present application;
FIG. 7 is a block diagram illustrating an apparatus for a server in accordance with an example embodiment.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a ciphertext generation method, a ciphertext generation device, a ciphertext generation server, a ciphertext generation medium and a ciphertext generation product based on Fourier series.
Fig. 1 is a block chain apparatus according to an embodiment of the present disclosure.
The blockchain apparatus comprises a plurality of nodes 11, which may be electronic devices or servers.
For example, the electronic device may be any electronic product that can interact with a user through one or more ways such as a keyboard, a touch PAD, a touch screen, a remote controller, a voice interaction device, or a handwriting device, for example, a mobile phone, a notebook computer, a tablet computer, a palm computer, a personal computer, a wearable device, a smart television, a PAD, and the like.
The server may be, for example, one server, a server cluster composed of a plurality of servers, or a cloud computing server center. The server may include a processor, memory, and a network interface, among others.
The plurality of nodes included in the block chain device respectively store one same block chain.
For any node in the plurality of nodes, the node stores the node identifiers of other nodes in the blockchain device, so that the generated block is broadcasted to other nodes in the blockchain device according to the other node identifiers.
In order to make the embodiments of the present application more understandable to those skilled in the art, the structure of the blockchain is described in detail below.
As shown in fig. 2, the blockchain is composed of a plurality of blocks. The starting block comprises a block head and a block main body, wherein the block head stores an input information characteristic value, a version number, a timestamp and a difficulty value, and the block main body stores input information; the next block of the starting block takes the starting block as a parent block, the next block also comprises a block head and a block main body, the block head stores the input information characteristic value of the current block, the block head characteristic value of the parent block, the version number, the timestamp and the difficulty value, and the like, so that the block data stored in each block in the block chain is associated with the block data stored in the parent block, and the safety of the input information in the block is ensured.
When each block in the block chain is generated, when the node where the block chain is located receives input information, the SHA-1 algorithm needs to be carried out on the input information for calculation, and the obtained 160-bit ciphertext is used as a characteristic value of the input information and is stored to the head of the block. And after obtaining the block main body and the block head, obtaining the current block, then respectively sending the newly generated blocks to other nodes by the node where the block chain is located according to the node identifications of the other nodes, verifying the newly generated blocks by the other nodes, and adding the newly generated blocks to the block chain stored in the newly generated blocks after the verification is finished.
With the continuous development of computer computing power and the continuous accumulation of collision cipher libraries in the application process of the SHA-1 algorithm, the ciphertext generated by the SHA-1 algorithm has the possibility of being cracked violently. If the SHA-1 algorithm is replaced by other algorithms, for example, the SHA-2 algorithm, to prevent the ciphertext generated by the SHA-1 algorithm from being violently cracked, but the SHA-2 algorithm generates 256-bit ciphertext, that is, the length of the ciphertext is different from the length of 160-bit ciphertext generated by the SHA-1 algorithm, the improvement will affect the interface and the message format, improve the transformation cost, and have high difficulty.
The embodiment of the application provides an improved method for SHA-1, so that the length of a ciphertext obtained by an improved SHA-1 algorithm is still 160 bits, an interface and a message format do not need to be improved, and the reconstruction cost is reduced.
The ciphertext generating method based on the Fourier series can be applied to any application scene using SHA-1, such as a computing scene of characteristic values of transaction data of a bank. The input information is different in different application scenes, such as in a calculation scene of a characteristic value of transaction data of a bank, and the input information is the transaction data.
The following describes a ciphertext generation method based on fourier series provided by an embodiment of the present application.
As shown in fig. 3, a flowchart of a ciphertext generation method based on fourier series according to an embodiment of the present application includes the following steps S301 to S320.
Step S301: input information to be stored to a blockchain is obtained.
For example, the input information may be transaction data. Such as transfer transaction data.
Step S302: and expanding the length complementary bits of the input information into 512 bits x Q to obtain a first message, wherein Q is any integer greater than or equal to 1.
The bit-filling expansion method provided by the embodiment of the present application has various types, but the embodiment of the present application provides, but is not limited to, the following three types.
The first implementation of step S302 includes steps a11 through a 14.
Step A11: and complementing one 1 at the tail of the input information.
Illustratively, the input information is binary data.
For example, if the length of the input information is an integer multiple of 512, the complementary bit extension operation may not be required, and if the length of the input information is not an integer multiple of 512, the complementary bit extension operation may be required.
Step A12: and supplementing 0 after 1 of the input information padding bit until the length of the second message after padding bit is 448 after modulo 512.
For example, if the remainder of the input information modulo 512 is 448, the steps a11 to a12 may not be performed. If the remainder of the length of the input information modulo 512 is not 448, steps a11 through a12 may be performed.
Step A13: and supplementing one 1 at the tail of the second message.
Step A14: and supplementing 63 0 s after 1 of the complementary bit of the second message to obtain the first message.
In order to make the implementation of the first step S302 more understood by those skilled in the art, the following description is made.
Fig. 4a is a schematic diagram illustrating an expansion of input information padding according to an embodiment of the present application.
Assuming that the length of the input message is 600 bits, the remainder of the input message modulo 512 is 88, and a second message is obtained after the input message is supplemented with a1 and 359 0. After the second message is supplemented with one 1 and 63 0's, the first message is obtained.
The second implementation of step S302 includes steps a21 through a 23.
Step A21: and complementing one 1 at the tail of the input information.
Illustratively, the input information is binary data.
For example, if the length of the input information is an integer multiple of 512, the complementary bit extension operation may not be required, and if the length of the input information is not an integer multiple of 512, the complementary bit extension operation may be required.
Step A22: and supplementing 0 after 1 of the input information padding bit until the length of the second message after padding bit is 448 after modulo 512.
For example, if the remainder of the input information modulo 512 is 448, the steps a21 to a22 may not be performed. If the remainder of the length of the input information modulo 512 is not 448, steps a21 through a22 may be performed.
Step A23: and padding 64 bits of 1 at the tail of the second message to obtain the first message.
In order to make the implementation of the second step S302 more understood by those skilled in the art, the following description is made.
Fig. 4b is a schematic diagram illustrating the input information padding expansion according to the embodiment of the present application.
Assuming that the length of the input message is 600 bits, the remainder of the input message modulo 512 is 88, and a second message is obtained after the input message is supplemented with a1 and 359 0. And supplementing 64 pieces of 1 after the second message to obtain the first message.
The third implementation of step S302 includes steps a31 through a 32.
Step A31: and complementing one 1 at the tail of the input information.
Illustratively, the input information is binary data.
For example, if the length of the input information is an integer multiple of 512, the complementary bit extension operation may not be required, and if the length of the input information is not an integer multiple of 512, the complementary bit extension operation may be required.
Step A32: and supplementing 0 after 1 of the input information padding bit until the remainder is 0 after the length of the first message after padding bit is modulo 512, so as to obtain the first message.
In order to make the implementation of the third step S302 more understood by those skilled in the art, the following description is made.
Fig. 4c is a schematic diagram illustrating the input information padding expansion according to the embodiment of the present application.
Assuming that the length of the input message is 600 bits, the remainder of the input message modulo 512 is 88, 1 is added after the input message, and 423 0 s are added to obtain the first message.
Step S303: and dividing the first message into Q data blocks, wherein the bit number of the data blocks is 512 bits.
Taking fig. 4a to 4c as an example, Q is 2.
For example, in this embodiment of the present application, the first packet is divided into Q data blocks, and one data block is obtained every time 512 bits of data are obtained from the head of the first packet.
Step S304: the initial value of G is set to 1.
Step S305: the following operations are performed for the G-th data block:
step S306: and dividing the data block into 16 target sub data blocks, wherein the number of bits of the target sub data blocks is 32.
Step S307: and performing operation on the 16 target sub data blocks to obtain 64 operation sub data blocks so as to obtain 80 sub data blocks, wherein the bit number of the operation sub data blocks is 32 bits, and the 80 sub data blocks comprise 16 target sub data blocks and 64 operation sub data blocks.
Step S308: obtaining preset 80 constants, wherein the values of the 80 constants are as follows:
Ktfirst preset value (0)<＝t<＝19)
KtSecond predetermined value (20)<＝t<＝39)
KtThird preset value (40)<＝t<＝59)
KtFourth preset value (60)<＝t<＝79)。
In an optional implementation manner, the 80 constants corresponding to different data blocks may be different, for example, the corresponding relationship between the 16 target sub data blocks obtained in step S306 and the 80 constants may be preset. I.e., 80 constants, vary from data block to data block.
In an alternative implementation, the 80 constants corresponding to different input information may be different, for example, the correspondence between the input information and the 80 constants may be preset. I.e., 80 constants, vary from input to input.
In an alternative implementation, the 80 constants corresponding to different data blocks may be the same.
In an alternative implementation, the first preset value is 0x5a827999, the second preset value is 0x6ED9EBA1, the third preset value is 0x8F1BBCDC, and the fourth preset value is 0xCA62C1D 6.
For example, 80 sub-data blocks sequentially include: 16 target sub-data blocks and 64 operation sub-data blocks.
Wherein, the sequence of the 16 target sub-data blocks is as follows: and sequencing according to the sequence of dividing the data block to obtain the target sub data block.
FIG. 5 is a schematic diagram showing the data block being divided into 16 target sub data blocks.
From the head of the data block, each time a target sub-data block is obtained by extracting 32 bits of data, a target sub-data block 1, a target sub-data block 2, a target sub-data block 3, a target sub-data block 4, …, and a target sub-data block 16 can be obtained in sequence. The sequence of the 16 target sub-data blocks is as follows: target sub data block 1, target sub data block 2, target sub data block 3, target sub data block 4, …, target sub data block 16.
In an alternative implementation manner, there are various implementation manners of step S307, and the embodiment of the present application provides, but is not limited to, the following implementation manner, and the method includes step B11 to step B14.
Step B11: the initial value of R is set to 0.
Step B12: let t be R, perform the following operations:
step B13: wt＝Mt(t is more than or equal to 0 and less than 16), wherein MtThe t +1 th target subdata block；Wt＝S1(Wt-3XOR Wt-14 XOR Wt-16) (16 is less than or equal to t is less than or equal to 79); wherein, S1 indicates a shift of 1 bit to the left.
Step B14: let R ═ R +1, return to step B12 until R equals 80.
Wherein, the 80 sub-data blocks are sequentially: w0、W1、W2、W3，…，W79。
In an alternative implementation, at least one of the 16 target sub-data blocks may be logically operated to obtain 64 operation sub-data blocks. The exclusive or operation XOR described above is not limited.
Step S309: fourier series
Figure BDA0003371955540000121
Spreading at x ═ i to obtain spread values f (i), i having values in the order of 1 to 80 to obtain 80 spread values, where a1To a40The values of (A) are as follows: constants of odd number among 80 constants, b, ordered from small to large in position1To b40The values of (A) are as follows: and constants positioned at even-numbered positions in 80 constants in order of position from small to large.
Wherein the content of the first and second substances,
Figure BDA0003371955540000122
namely a1＝K0、a2＝K2、a3＝K4、a4＝K6、a5＝K8、a6＝K10、…；b1＝K1、b2＝K3、b3＝K5、b4＝K7、b5＝K9、b6s＝K11、…。
Exemplary, a0May be a preset value.
Exemplary, a0May be a1To a40And b1To b40The sum of the values of (a).
It is understood that if a fourier series is expanded at x ═ 1, then f (1) is obtained, and if a fourier series is expanded at x ═ 1 to x ═ 80, then a total of 80 expansion values of f (1) to f (80) are obtained.
In an alternative implementation, the 80 constants obtained in step S308 are different for different input information or data blocks, that is, the parameter term (i.e., a) of the fourier series is different for different input information or data blocksnAnd bn) And the randomness and the brute force cracking resistance of the algorithm are improved, the algorithm performance consumption is low, and the algorithm can be transplanted and realized on different platforms and hardware equipment so as to meet the requirements of various use scenes of a block chain in a financial business system.
Step S310: assigning f (i) to Ki-1。
Wherein, K0＝f(1)、K1＝f(2)、K2＝f(3)、…，K79＝f(80)。
Step S311: obtaining an identity of a buffer H0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4Is started.
In an alternative implementation manner, for the first data block, that is, when step S311 is performed for the first time, the preset identifier H of 16 sub data blocks and buffer may be used0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4In the corresponding relation of the initial values, the identifier H of the buffer area corresponding to the 16 target sub data blocks is searched0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4Is started.
I.e. H corresponding to different target sub-data blocksiSince the target sub data block is related to the input information, the obtained H is different in the case of different plaintext input in the present applicationiAre different from each other. Thereby increasing randomness and the brute force cracking resistance of the algorithm.
In an alternative implementation, the buffer { Hi } is initialized to the following values:
H0＝0x67452301
H1＝0xEFCDAB89
H2＝0x98BADCFE
H3＝0x10325476
H4＝0xC3D2E1F0
step S312: h is to be0Of (d), H1Of (d), H2Of (d), H3Of (d), H4Respectively assigning the initial values to a first parameter, a second parameter, a third parameter, a fourth parameter and a fifth parameter.
Step S313: the initial value of P is set to 0.
Step S314: for t ═ P, the following calculation is performed:
TEMP＝S5(H0)+ft(H1,H2,H3)+H4+Wt+Kt；H4＝H3；H3＝H2；H2＝S30(H1)；H1＝H0；H0TEMP; wherein, WtFor the t +1 th sub-data block of the 80 sub-data blocks, ft(H1,H2,H3) Is a preset function; s5(H0) Means that H is0Left shift by 5; s30(H1) Means that H is1Shifted 30 to the left.
Exemplary, ft(H1,H2,H3) Is preset with H1,H2,H3As a function of the argument, e.g. a preset function ft(H1,H2,H3) The following were used:
ft(H1,H2,H3)＝(H1 AND H2)or((NOT H1)AND H3)(0<＝t<＝19)
ft(H1,H2,H3)＝H1 XOR H2 XOR H3(20<＝t<＝39)
ft(H1,H2,H3)＝(H1 AND H2)or(H1 AND H3)or(H2 AND H3)(40<＝t<＝59)
ft(H1,H2,H3)＝H1 XOR H2 XOR H3(60<＝t<＝79)。
in an alternative implementation, ft(H1,H2,H3) It may or may not be a piecewise function, and the above is only an example and is not for ft(H1,H2,H3) Resulting in a definition.
Step S315: setting P +1, return to step S314 until P equals 80 to obtain the identification H of the buffer area0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4The value of (c).
Step S316: let H0Final value of ═ H0Value of + first parameter, H1Final value of ═ H1Value of + second parameter, H2Final value of ═ H2Value of + third parameter, H3Final value of ═ H3Value of + fourth parameter, H4Final value of ═ H4Value + fifth parameter.
Step S317: subjecting said H to0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4Respectively as the mark H of the buffer corresponding to the G +1 th data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4Is started.
I.e. the obtained identification H of the buffer when step S311 is performed for the second timeiIs the initial value of (a) obtained when step S316 is first performed, H is obtainediThe final value of (c).
When step S311 is executed for the third time, the obtained identifier H of the buffer areaiIs obtained when step S316 is executed for the second timeHiThe final value of (c). And so on, will not be described again.
If the first packet is divided into a plurality of data blocks, multiple iterations may be required, and H obtained from the previous data block0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4Is the final value of H for the next data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4The initial value of (2) so that the finally obtained ciphertext is related to the number of iterations, and the ciphertext is more difficult to crack.
Step S318: set G +1 and return to step S305 until G is greater than Q.
Step S319: according to H0、H1、H2、H3、H4In the order of (A) and (B), is0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4The final value of (a) is composed of a 160-bit digest, which is determined to be the ciphertext.
It is understood that HiThe values of (a) are all 32 bits in length, so 5HiConstituting 160-bit cipher text.
Step S320: and storing the ciphertext to a block chain.
For example, the ciphertext may be stored as a feature value of the input information to a corresponding block in the blockchain.
According to the ciphertext generating method based on the Fourier series, after 80 preset constants are obtained, the Fourier series is expanded at x-i to obtain expansion values f (i), the values of i are 1-80 in sequence to obtain 80 expansion values, wherein a1To a40The values of (A) are as follows: constants of odd number among 80 constants, b, ordered from small to large in position1To b40The values of (A) are as follows: constants positioned at even-numbered positions in the 80 constants are sorted from small to large according to positions; f (1) to f (80) as 80 constants, and therefore, H is obtained based on f (1) to f (80) as 80 constants0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4And H obtained based on 80 constants set in advance0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4If the input information is divided into a plurality of data blocks, the identifier H of the buffer area corresponding to the next data block is calculated in the next data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4Is the initial value of H obtained for the last data block0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4The final value of (b), i.e., the specific content of the resulting 160-bit ciphertext, is related not only to the number of data blocks into which the input information is divided, but also to the 80 expansion values of the fourier series. If brute force cracking is needed, the number of the divided data blocks of the input information needs to be cracked, and 80 expansion values of the Fourier series need to be cracked.
By adopting the ciphertext generation method based on the Fourier series, the safety of the characteristic value of the input information of the block chain is improved, an attacker cannot use the conventional SHA-1 dictionary base to reversely decrypt the characteristic value, and the possibility of brute force cracking is avoided.
The embodiment of the application organically fuses the Fourier series and the characteristic value, so that the encryption processing value has uniqueness, when one or more characters contained in the input information are changed, at least 1/2 expansion values in 80 expansion values obtained by the introduced Fourier series expansion are obviously changed, namely the avalanche effect of the algorithm, the password complexity is obviously enhanced, the brute force cracking can be hardly realized under the existing operational capability, and the cost of the brute force cracking is greatly increased.
The method is described in detail in the embodiments disclosed in the present application, and the method of the present application can be implemented by various types of apparatuses, so that an apparatus is also disclosed in the present application, and the following detailed description is given of specific embodiments.
As shown in fig. 6, a structure diagram of a ciphertext generating apparatus based on fourier series according to an embodiment of the present application, the apparatus includes: the device comprises a first obtaining module 601, a bit-filling expanding module 602, a first dividing module 603, a first setting module 604, a second dividing module 605, an operation module 606, a second obtaining module 607, an expansion module 608, a first assignment module 609, a third obtaining module 610, a second assignment module 611, a third assignment module 612, a calculation module 613, a first triggering module 614, a fourth assignment module 615, a fifth assignment module 616, a second triggering module 617, a determination module 618 and a storage module 619, wherein:
a first obtaining module 601, configured to obtain input information to be stored in a block chain;
a bit-complementing expansion module 602, configured to expand the length-complementing bits of the input information to 512 bits × Q to obtain a first packet, where Q is any integer greater than or equal to 1;
a first dividing module 603, configured to divide the first packet into Q data blocks, where the number of bits of each data block is 512 bits;
a first setting module 604, configured to set an initial value of G to 1;
the following operations are performed for the G-th data block:
a second dividing module 605, configured to divide the data block into 16 target sub data blocks, where the number of bits of the target sub data blocks is 32 bits;
an operation module 606, configured to perform an operation on the 16 target sub data blocks to obtain 64 operation sub data blocks, so as to obtain 80 sub data blocks, where the bit number of the operation sub data block is 32 bits, and the 80 sub data blocks include 16 target sub data blocks and 64 operation sub data blocks;
a second obtaining module 607, configured to obtain preset 80 constants, where values of the 80 constants are as follows:
Ktfirst preset value (0)<＝t<＝19)
KtSecond predetermined value (20)<＝t<＝39)
KtThird preset value (40)<＝t<＝59)
KtFourth preset value (60)<＝t<＝79)；
An expansion module 608 for expanding the Fourier series
Figure BDA0003371955540000161
Spreading at x ═ i to obtain spread values f (i), i having values in the order of 1 to 80 to obtain 80 spread values, where a1To a40The values of (A) are as follows: constants of odd number among 80 constants, b, ordered from small to large in position1To b40The values of (A) are as follows: constants positioned at even-numbered positions in the 80 constants are sorted from small to large according to positions;
a first assigning block 609 configured to assign f (i) to Ki-1；
A third obtaining module 610, configured to obtain an identifier H of the buffer0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
a second assignment module 611 for assigning H0Of (d), H1Of (d), H2Of (d), H3Of (d), H4Respectively assigning the initial values to a first parameter, a second parameter, a third parameter, a fourth parameter and a fifth parameter;
a third assignment module 612, configured to set an initial value of P to 0;
a calculating module 613, configured to perform the following calculation for t ═ P:
TEMP＝S5(H0)+ft(H1,H2,H3)+H4+Wt+Kt；H4＝H3；H3＝H2；H2＝S30(H1)；H1＝H0；H0TEMP; wherein, WtFor the t +1 th sub-data block of the 80 sub-data blocks, ft(H1,H2,H3) Is presetA function of position; s5(H0) Means that H is0Left shift by 5; s30(H1) Means that H is1Left shift by 30;
a first triggering module 614, configured to set P +1, and return to the calculating module until P equals 80, so as to obtain the identifier H of the buffer area0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4A value of (d);
a fourth valuation module 615 for order H0Final value of ═ H0Value of + first parameter, H1Final value of ═ H1Value of + second parameter, H2Final value of ═ H2Value of + third parameter, H3Final value of ═ H3Value of + fourth parameter, H4Final value of ═ H4The value of + the fifth parameter;
a fifth assigning module 616 for assigning said H0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4Respectively as the mark H of the buffer corresponding to the G +1 th data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
a second triggering module 617, configured to set G +1, and return to the second dividing module until G is greater than Q;
a determining module 618 for following H0、H1、H2、H3、H4In the order of (A) and (B), is0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4The 160-bit abstract composed of the final values of the two-bit abstract is determined as a ciphertext;
a storage module 619, configured to store the ciphertext to the block chain.
In an optional implementation manner, the bit complement expansion module includes:
a first padding unit for padding one 1 at the end of the input information;
a second bit complement unit, configured to complement 0 after 1 of the input information bit complement until a remainder of a length of the second packet after the bit complement modulo 512 is 448;
a third bit complementing unit, configured to complement a bit 1 at the end of the second packet;
a fourth bit complement unit, configured to complement 63 0 s after 1 of the bit complement of the second packet, so as to obtain the first packet.
In an alternative implementation, the first preset value is 0x5a827999, the second preset value is 0x6ED9EBA1, the third preset value is 0x8F1BBCDC, and the fourth preset value is 0xCA62C1D 6.
In an alternative implementation, the preset function ft(H1,H2,H3) The following were used:
ft(H1,H2,H3)＝(H1 AND H2)or((NOT H1)AND H3)(0<＝t<＝19)
ft(H1,H2,H3)＝H1 XOR H2 XOR H3(20<＝t<＝39)
ft(H1,H2,H3)＝(H1 AND H2)or(H1 AND H3)or(H2 AND H3)(40<＝t<＝59)
ft(H1,H2,H3)＝H1 XOR H2 XOR H3(60<＝t<＝79)。
with regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
FIG. 7 is a block diagram illustrating an apparatus for a server in accordance with an example embodiment.
Servers include, but are not limited to: a processor 71, a memory 72, a network interface 73, an I/O controller 74, and a communication bus 75.
It should be noted that the structure of the server shown in fig. 7 does not constitute a limitation of the server, and the server may include more or less components than those shown in fig. 7, or combine some components, or arrange different components, as will be understood by those skilled in the art.
The following describes each component of the server in detail with reference to fig. 7:
the processor 71 is a control center of the server, connects various parts of the entire server using various interfaces and lines, and performs various functions of the server and processes data by running or executing software programs and/or modules stored in the memory 72 and calling data stored in the memory 72, thereby performing overall monitoring of the server. Processor 71 may include one or more processing units; illustratively, the processor 71 may integrate an application processor, which primarily handles operating systems, user interfaces, applications, etc., and a modem processor, which primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 71.
Processor 71 may be a Central Processing Unit (CPU), or an application Specific Integrated circuit (asic), or one or more Integrated circuits configured to implement embodiments of the present invention, etc.;
the Memory 72 may include Memory, such as a Random-Access Memory (RAM) 721 and a Read-Only Memory (ROM) 722, and may also include a mass storage device 723, such as at least 1 disk storage. Of course, the server may also include hardware needed for other services.
The memory 72 is used for storing the executable instructions of the processor 71. The processor 71 has a function of a ciphertext generation method based on a fourier series.
A wired or wireless network interface 73 is configured to connect the server to a network.
The processor 71, the memory 72, the network interface 73, and the I/O controller 74 may be connected to each other by a communication bus 75, which may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc.
In an exemplary embodiment, the server may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described fourier series based ciphertext generation method.
In an exemplary embodiment, the disclosed embodiments provide a storage medium comprising instructions, such as a memory 72 comprising instructions, executable by a processor 71 of a server to perform the above-described method. Alternatively, the storage medium may be a non-transitory computer readable storage medium, which may be, for example, a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
In an exemplary embodiment, a computer-readable storage medium is also provided, which is directly loadable into an internal memory of a computer, such as the memory 72 described above, and contains software codes, and when the computer program is loaded into the computer and executed, the computer program can implement the steps shown in any embodiment of the above-mentioned fourier-series-based ciphertext generation method.
In an exemplary embodiment, a computer program product is further provided, which is directly loadable into an internal memory of a computer, for example, a memory included in the server, and contains software codes, and which, when loaded and executed by the computer, is capable of implementing the steps shown in any embodiment of the above-mentioned fourier series-based ciphertext generation method.
The ciphertext generating method, the server, the medium and the device based on the Fourier series can be used in the field of block chains or the field of finance. The above description is merely an example, and does not limit the application fields of the ciphertext generation method based on the fourier series, the server, the medium, and the apparatus provided by the present invention.
Note that the features described in the embodiments in the present specification may be replaced with or combined with each other. For the device or system type embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A ciphertext generation method based on Fourier series is characterized by comprising the following steps:
acquiring input information to be stored to a block chain;
expanding the length complementary bits of the input information into 512 bits x Q to obtain a first message, wherein Q is any integer greater than or equal to 1;
dividing the first message into Q data blocks, wherein the number of bits of the data blocks is 512 bits;
setting the initial value of G to be 1;
the following operations are performed for the G-th data block:
dividing the data block into 16 target sub data blocks, wherein the number of bits of the target sub data blocks is 32;
performing operation on the 16 target sub data blocks to obtain 64 operation sub data blocks so as to obtain 80 sub data blocks, wherein the bit number of the operation sub data blocks is 32 bits, and the 80 sub data blocks comprise the 16 target sub data blocks and the 64 operation sub data blocks;
obtaining preset 80 constants, wherein the values of the 80 constants are as follows:
Ktfirst preset value (0)<＝t<＝19)
KtSecond predetermined value (20)<＝t<＝39)
KtThird preset value (40)<＝t<＝59)
KtFourth preset value (60)<＝t<＝79)；
Fourier series
Figure FDA0003371955530000011
Spreading at x ═ i to obtain spread values f (i), i having values in the order of 1 to 80 to obtain 80 spread values, wherein，a1To a40The values of (A) are as follows: constants of odd number among 80 constants, b, ordered from small to large in position1To b40The values of (A) are as follows: constants positioned at even-numbered positions in the 80 constants are sorted from small to large according to positions;
assigning f (i) to Ki-1；
Obtaining an identity of a buffer H0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
h is to be0Of (d), H1Of (d), H2Of (d), H3Of (d), H4Respectively assigning the initial values to a first parameter, a second parameter, a third parameter, a fourth parameter and a fifth parameter;
setting the initial value of P to be 0;
for t ═ P, the following calculation is performed:
TEMP＝S5(H0)+ft(H1,H2,H3)+H4+Wt+Kt；H4＝H3；H3＝H2；H2＝S30(H1)；H1＝H0；H0TEMP; wherein, WtFor the t +1 th sub-data block of the 80 sub-data blocks, ft(H1,H2,H3) Is a preset function; s5(H0) Means that H is0Left shift by 5; s30(H1) Means that H is1Left shift by 30;
setting P +1, returning to the step for t P, the following calculation is performed until P equals 80 to obtain the identification H of the buffer area0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4A value of (d);
let H0Final value of ═ H0Value of + first parameter, H1Final value of ═ H1Value of + second parameter, H2Final value of ═ H2Value of + third parameter, H3Final value of ═ H3Value of + fourth parameter, H4Final value of ═ H4The value of + the fifth parameter;
subjecting said H to0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4Respectively as the mark H of the buffer corresponding to the G +1 th data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
setting G to G +1, and returning to the step to execute the following operations on the G-th data block until G is larger than Q;
according to H0、H1、H2、H3、H4In the order of (A) and (B), is0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4The 160-bit abstract composed of the final values of the two-bit abstract is determined as a ciphertext;
and storing the ciphertext to a block chain.
2. The method of generating ciphertext based on the fourier series of claim 1, wherein the step of expanding the length padding of the input message to 512 bits x Q to obtain the first packet comprises:
padding one 1 at the tail of the input information;
supplementing 0 after 1 of the input information bit-complementing position until the remainder is 448 after the length of the second message after the bit-complementing position is modulo 512;
padding one 1 at the tail of the second message;
and supplementing 63 0 s after 1 of the complementary bit of the second message to obtain the first message.
3. The method for generating ciphertext based on fourier series according to claim 1 or 2, wherein the step of performing the operation on the 16 target sub data blocks to obtain 64 operation sub data blocks comprises:
setting the initial value of R to be 0;
let t be R, perform the following operations:
Wt＝Mt(t is more than or equal to 0 and less than 16), wherein MtThe target subdata block is the t +1 th subdata block;
Wt＝S1(Wt-3 XORWt-14 XOR Wt-16) (16 is less than or equal to t is less than or equal to 79); wherein, S1 indicates a shift of 1 bit to the left;
let R ═ R +1, return to step let t ═ R, perform the following operations until R equals 80.
4. The method for generating ciphertext based on the fourier series as claimed in claim 1, wherein the first predetermined value is 0x5a827999, the second predetermined value is 0x6ED9EBA1, the third predetermined value is 0x8F1BBCDC, and the fourth predetermined value is 0xCA62C1D 6.
5. The ciphertext generation method based on the fourier series as claimed in claim 1, wherein the preset function ft(H1,H2,H3) The following were used:
ft(H1,H2,H3)＝(H1 AND H2)or((NOT H1)AND H3)(0<＝t<＝19)
ft(H1,H2,H3)＝H1 XOR H2 XOR H3(20<＝t<＝39)
ft(H1,H2,H3)＝(H1 AND H2)or(H1 AND H3)or(H2 AND H3)(40<＝t<＝59)
ft(H1,H2,H3)＝H1 XOR H2 XOR H3(60<＝t<＝79)。
6. a ciphertext generation apparatus based on a fourier series, comprising:
the first acquisition module is used for acquiring input information to be stored to the block chain;
a bit-complementing expansion module, configured to expand the length bit-complementing of the input information to 512 bits × Q to obtain a first packet, where Q is any integer greater than or equal to 1;
the first dividing module is used for dividing the first message into Q data blocks, and the bit number of each data block is 512 bits;
the first setting module is used for setting the initial value of G to be 1;
the following operations are performed for the G-th data block:
the second dividing module is used for dividing the data block into 16 target sub data blocks, and the number of bits of each target sub data block is 32;
the operation module is used for performing operation on the 16 target sub data blocks to obtain 64 operation sub data blocks so as to obtain 80 sub data blocks, the bit number of each operation sub data block is 32 bits, and the 80 sub data blocks comprise 16 target sub data blocks and 64 operation sub data blocks;
the second obtaining module is configured to obtain preset 80 constants, where values of the 80 constants are as follows:
Ktfirst preset value (0)<＝t<＝19)
KtSecond predetermined value (20)<＝t<＝39)
KtThird preset value (40)<＝t<＝59)
KtFourth preset value (60)<＝t<＝79)；
An expansion module for expanding the Fourier series
Figure FDA0003371955530000041
Spreading at x ═ i to obtain spread values f (i), i having values in the order of 1 to 80 to obtain 80 spread values, where a1To a40The values of (A) are as follows: constants of odd number among 80 constants, b, ordered from small to large in position1To b40The values of (A) are as follows: constants positioned at even-numbered positions in the 80 constants are sorted from small to large according to positions;
a first assigning module for assigning f (i) to Ki-1；
A third obtaining module, configured to obtain an identifier H of the buffer0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
a second assignment module for assigning H0Of (d), H1Of (d), H2Of (d), H3Of (d), H4Respectively assigning the initial values to a first parameter, a second parameter, a third parameter, a fourth parameter and a fifth parameter;
the third assignment module is used for setting the initial value of P to be 0;
a calculation module for performing the following calculation for t ═ P:
TEMP＝S5(H0)+ft(H1,H2,H3)+H4+Wt+Kt；H4＝H3；H3＝H2；H2＝S30(H1)；H1＝H0；H0TEMP; wherein, WtFor the t +1 th sub-data block of the 80 sub-data blocks, ft(H1,H2,H3) Is a preset function; s5(H0) Means that H is0Left shift by 5; s30(H1) Means that H is1Left shift by 30;
a first trigger module, configured to set P +1, and return to the calculation module until P equals 80, so as to obtain an identifier H of the buffer area0Value of (A), H1Value of (A), H2Value of (A), H3Value of (A), H4A value of (d);
a fourth assignment module for ordering H0Final value of ═ H0Value of + first parameter, H1Final value of ═ H1Value of + second parameter, H2Final value of ═ H2Value of + third parameter, H3Final value of ═ H3Value of + fourth parameter, H4Final value of ═ H4The value of + the fifth parameter;
a fifth assignment module for assigning the H0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4Respectively as the mark H of the buffer corresponding to the G +1 th data block0Initial value of (1), H1Initial value of (1), H2Initial value of (1), H3Initial value of (1), H4An initial value of (1);
the second trigger module is used for setting G +1 and returning to the second dividing module until G is larger than Q;
a determination module for following H0、H1、H2、H3、H4In the order of (A) and (B), is0Final value of (1), H1Final value of (1), H2Final value of (1), H3Final value of (1), H4The 160-bit abstract composed of the final values of the two-bit abstract is determined as a ciphertext;
and the storage module is used for storing the ciphertext to the block chain.
7. The apparatus according to claim 6, wherein the complementary bit expansion module comprises:
a first padding unit for padding one 1 at the end of the input information;
a second bit complement unit, configured to complement 0 after 1 of the input information bit complement until a remainder of a length of the second packet after the bit complement modulo 512 is 448;
a third bit complementing unit, configured to complement a bit 1 at the end of the second packet;
a fourth bit complement unit, configured to complement 63 0 s after 1 of the bit complement of the second packet, so as to obtain the first packet.
8. A server, comprising:
a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the fourier series based ciphertext generation method of any one of claims 1 to 5.
9. A computer-readable storage medium in which instructions, when executed by a processor of a server, enable the server to perform the fourier series-based ciphertext generation method of any one of claims 1 to 5.
10. A computer program product directly loadable into the internal memory of a computer, said memory being the memory comprised by the server according to claim 8 and containing software code, said computer program being loadable and executable by the computer to implement the method for generating a ciphertext based on a fourier series as claimed in any one of claims 1 to 5.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110503434A (en) * 2019-07-15 2019-11-26 平安普惠企业管理有限公司 Data verification method, device, equipment and storage medium based on hash algorithm
CN113688350A (en) * 2021-07-15 2021-11-23 千方捷通科技股份有限公司 Method, device, storage medium and terminal for predicting traffic flow based on Fourier function

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110503434A (en) * 2019-07-15 2019-11-26 平安普惠企业管理有限公司 Data verification method, device, equipment and storage medium based on hash algorithm
CN113688350A (en) * 2021-07-15 2021-11-23 千方捷通科技股份有限公司 Method, device, storage medium and terminal for predicting traffic flow based on Fourier function

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