CN114122101A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN114122101A CN114122101A CN202111431992.XA CN202111431992A CN114122101A CN 114122101 A CN114122101 A CN 114122101A CN 202111431992 A CN202111431992 A CN 202111431992A CN 114122101 A CN114122101 A CN 114122101A
- Authority
- CN
- China
- Prior art keywords
- transistor
- pixel driving
- orthographic projection
- active
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 222
- 239000003990 capacitor Substances 0.000 claims description 13
- 230000000694 effects Effects 0.000 abstract description 2
- 238000004020 luminiscence type Methods 0.000 abstract 1
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 14
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 14
- 230000001105 regulatory effect Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 230000001808 coupling effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The utility model relates to a show technical field, provide a display panel, display device, pixel drive circuit includes drive transistor, first transistor, second transistor, seventh transistor among the display panel, the second pole of first transistor, the first pole of second transistor all connect drive transistor's grid, the seventh transistor is connected between second initial signal line and luminescence unit, display panel still includes the substrate base plate, active layer, the second conducting layer that stack gradually. The active layer comprises a first active part for forming a channel region of the first transistor, a second active part for forming a channel region of the second transistor, and an eighth active part connected between the first active part and the second active part; the second conducting layer comprises a second initial signal line, and the orthographic projection of the second initial signal line in the pixel driving circuit of the upper row on the substrate at least partially overlaps the orthographic projection of the eighth active part in the pixel driving circuit of the current row on the substrate. The display panel has a good display effect.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a display panel and a display device.
Background
In the related art, a pixel driving circuit generally includes a driving transistor, and in a light emitting stage of the pixel driving circuit, a gate of the driving transistor is in a floating state, and a gate voltage of the driving transistor is changed due to a coupling effect of other signal lines on the gate of the driving transistor, so that a light emitting unit emits light abnormally.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
BRIEF SUMMARY OF THE PRESENT DISCLOSURE
According to an aspect of the present disclosure, a display panel is provided, wherein the display panel includes a plurality of pixel driving circuits distributed in an array along a row and column direction, the pixel driving circuits being configured to supply a driving current to first electrodes of light emitting units; the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, and a seventh transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate of the driving transistor, a first electrode of the second transistor is connected to a gate of the driving transistor, a second electrode of the second transistor is connected to a first electrode of the driving transistor, a gate of the second transistor is connected to a gate driving signal line, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to a first electrode of the light emitting unit, and the display panel further includes: the transistor comprises a substrate base plate, an active layer and a second conducting layer, wherein the active layer is positioned on one side of the substrate base plate and comprises a first active part, a second active part and an eighth active part connected between the first active part and the second active part, the first active part is used for forming a channel region of the first transistor, and the second active part is used for forming a channel region of the second transistor; the second conducting layer is located on one side, away from the substrate base plate, of the active layer, the second conducting layer comprises the second initial signal line, the orthographic projection of the second initial signal line on the substrate base plate extends along the row direction, and the orthographic projection of the second initial signal line in the upper row of pixel driving circuits on the substrate base plate at least partially overlaps with the orthographic projection of the eighth active part in the current row of pixel driving circuits on the substrate base plate.
In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a first pole of the fourth transistor is connected to the data line, and a second pole of the fourth transistor is connected to the second pole of the driving transistor; the active layer further includes a fourth active portion for forming a channel region of the fourth transistor, a ninth active portion connected between the fourth active portion and the data line; the orthographic projection of the second initial signal line on the substrate in the pixel driving circuit in the previous row is intersected with the orthographic projection of the ninth active part on the substrate in the pixel driving circuit in the current row.
In an exemplary embodiment of the present disclosure, a gate of the first transistor is connected to a first reset signal line, and a gate of the seventh transistor is connected to a second reset signal line; the active layer further includes a seventh active portion for forming a channel region of the seventh transistor; the display panel further includes: a first conductive layer between the active layer and the second conductive layer, the first conductive layer comprising: the first reset signal line and the second reset signal line, an orthographic projection of the first reset signal line on the substrate extends along a row direction and covers an orthographic projection of the first active part on the substrate, and a partial structure of the first reset signal line is used for forming a grid electrode of the first transistor; an orthographic projection of the second reset signal line on the substrate base plate extends along the row direction and covers an orthographic projection of the seventh active part on the substrate base plate, and a partial structure of the second reset signal line is used for forming a grid electrode of the seventh transistor; the first reset signal line in the pixel driving circuit of the row shares the second reset signal line in the pixel driving circuit of the previous row.
In an exemplary embodiment of the present disclosure, a gate of the first transistor is connected to a first reset signal line, a gate of the fourth transistor is connected to the gate driving signal line, and the display panel further includes: a first conductive layer between the active layer and the second conductive layer, the first conductive layer comprising: the first reset signal line and the gate drive signal line, an orthographic projection of the first reset signal line on the substrate extends along a row direction and covers an orthographic projection of the first active part on the substrate, and a partial structure of the first reset signal line is used for forming a gate of the first transistor; the orthographic projection of the gate driving signal line on the substrate extends along the row direction and covers the orthographic projection of the second active part on the substrate and the orthographic projection of the fourth active part on the substrate, part of the structure of the gate driving signal line is used for forming the gate of the second transistor, and the other part of the structure of the gate driving signal line is used for forming the gate of the fourth transistor.
In an exemplary embodiment of the present disclosure, an orthographic projection of the second initial signal line on the substrate in the previous row of pixel driving circuits is located between an orthographic projection of the gate driving signal line on the substrate in the present row of pixel driving circuits and an orthographic projection of the first reset signal line on the substrate in the present row of pixel driving circuits.
In one exemplary embodiment of the present disclosure, an orthographic projection of the eighth active portion on the substrate base plate extends in a column direction, and the second initial signal line includes: the orthographic projection of the first main body line on the substrate base plate extends along the row direction, and the orthographic projection of the first main body line on the substrate base plate in the pixel driving circuit in the upper row is intersected with the orthographic projection of the eighth active part on the substrate base plate in the pixel driving circuit in the current row; the first protruding parts are connected to the main body line, the orthographic projections of the first protruding parts on the substrate base plate extend along the column direction, and in two adjacent pixel driving circuits in the same column, the orthographic projections of the first protruding parts on the substrate base plate in the pixel driving circuits in the upper row at least partially overlap with the orthographic projections of the eighth active parts on the substrate base plate in the pixel driving circuits in the current row.
In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a sixth transistor and a fourth transistor, a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light emitting unit, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the second electrode of the driving transistor; the active layer further includes: a third active portion, a sixth active portion, a seventh active portion, and a tenth active portion, the third active portion being used to form a channel region of the driving transistor; a sixth active portion connected to the third active portion for forming a channel region of the sixth transistor; the seventh active part is connected to one end of the sixth active part, which is far away from the third active part, and is used for forming a channel region of the seventh transistor; the tenth active portion is connected to one end of the seventh active portion, which is far from the sixth active portion. The display panel further includes: and the third conducting layer is positioned on one side of the second conducting layer, which is deviated from the substrate base plate, and comprises a first connecting part, and the first connecting part is respectively connected with the second initial signal line and the tenth active part through a through hole. The data lines comprise first data lines, the orthographic projection of the first data lines on the substrate extends along the column direction, one first data line is correspondingly arranged on each column of pixel driving circuits, and in two adjacent pixel driving circuits in the same column, the orthographic projection of the tenth active part in the pixel driving circuit in the previous row on the substrate is positioned between the orthographic projection of the eighth active part in the pixel driving circuit in the current row on the substrate and the orthographic projection of the first data lines on the substrate in the row direction; in two adjacent pixel driving circuits in the same column, an orthogonal projection of at least part of the structure of the first connecting portion in the pixel driving circuit in the upper row on the substrate is located between an orthogonal projection of the eighth active portion in the pixel driving circuit in the current row on the substrate and an orthogonal projection of the first data line on the substrate in the row direction.
In one exemplary embodiment of the present disclosure, the third conductive layer further includes: a second connection part connected to the eighth active part through a via hole and connected to the gate of the driving transistor; the first connecting portion comprises a first via hole connecting portion, a second via hole connecting portion and an extending portion, the first via hole connecting portion is connected with the second initial signal line through a via hole, the second via hole connecting portion is connected with the first via hole connecting portion and is connected with the tenth active portion through a via hole, and the extending portion is connected to one end, away from the first via hole connecting portion, of the second via hole connecting portion; in two adjacent pixel driving circuits in the same column, the orthographic projection of the extension part in the pixel driving circuit in the upper row on the substrate is located between the orthographic projection of the second connecting part in the pixel driving circuit in the current row on the substrate and the orthographic projection of the first data line on the substrate in the row direction.
In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a fifth transistor, a first electrode of the fourth transistor is connected to the data line, a second electrode of the fourth transistor is connected to the second electrode of the driving transistor, a first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the second electrode of the driving transistor; the active layer further includes a fourth active portion for forming a channel region of the fourth transistor, a ninth active portion connected between the fourth active portion and the data line; an orthographic projection of the ninth active portion on the substrate base plate extends in a column direction, the second conductive layer further includes: the orthographic projection of the first conductive part on the substrate base plate extends along the row direction and is intersected with the orthographic projection of the ninth active part on the substrate base plate, and the first conductive part is connected with a stable voltage source.
In an exemplary embodiment of the present disclosure, the display panel further includes: the third conducting layer is positioned on one side, away from the substrate base plate, of the second conducting layer, the third conducting layer comprises the first power line, the orthographic projection of the first power line on the substrate base plate extends in the column direction, and the first power line is connected with the first conducting part through a through hole.
In one exemplary embodiment of the present disclosure, the second active portion includes: a first sub-active portion and a second sub-active portion, the active layer further including a third sub-active portion connected between the first sub-active portion and the second sub-active portion; in the same row of pixel driving circuits, the orthographic projection of the first conductive part in the pixel driving circuit of the current column on the substrate is at least partially overlapped with the orthographic projection of the third sub-active part in the pixel driving circuit of the adjacent column on the substrate.
In an exemplary embodiment of the present disclosure, the display panel further includes: the third conductive layer is positioned on one side, away from the substrate base plate, of the second conductive layer, and the third conductive part comprises a second connecting part which is connected with the eighth active part through a through hole and is connected with the grid electrode of the driving transistor; the fourth conducting layer is located on one side, away from the substrate base plate, of the third conducting layer and comprises a second conducting part, the second conducting part is connected with a stable voltage source, and the orthographic projection of the second conducting part on the substrate base plate covers the orthographic projection of the second connecting part on the substrate base plate.
In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fifth transistor, a first pole of the fifth transistor is connected to the first power line, and a second pole of the fifth transistor is connected to the second pole of the driving transistor; the third conductive layer includes: the first power supply line, the orthographic projection of the first power supply line on the substrate base plate extends along the column direction, the first power supply line includes: the orthographic projection of the second main body line on the substrate base plate extends along the column direction; the second bulge is connected to the second main body line, and the orthographic projection of the second bulge on the substrate base plate extends along the row direction; in the same row of pixel driving circuits, the second protruding portion in the pixel driving circuit of the current column is connected with the second conductive portion in the pixel driving circuit of the adjacent column through a via hole.
In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fifth transistor, a first pole of the fifth transistor is connected to the first power line, a second pole of the fifth transistor is connected to the second pole of the driving transistor, and the display panel further includes: the third conducting layer is positioned on one side, away from the substrate base plate, of the second conducting layer and comprises the first power line, and the orthographic projection of the first power line on the substrate base plate extends along the column direction; the fourth conducting layer is located on one side, away from the substrate base plate, of the third conducting layer and comprises a second power line, the orthographic projection of the second power line on the substrate base plate extends in the column direction and at least partially overlaps with the orthographic projection of the first power line on the substrate base plate, and the second power line is connected with the first power line through a through hole.
In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a first pole of the fourth transistor is connected to the data line, and a second pole of the fourth transistor is connected to the second pole of the driving transistor; the pixel driving circuits in each column are correspondingly provided with two data lines, in the same column of pixel driving circuits, the two data lines are connected with the pixel driving circuits in different rows, and the pixel driving circuits connected with the different data lines are sequentially and alternately distributed in the column direction.
In one exemplary embodiment of the present disclosure, the plurality of pixel driving circuits includes a plurality of first pixel driving circuit groups and a plurality of second pixel driving circuit groups, the first pixel driving circuit groups are all disposed adjacent to the second pixel driving circuit groups in the row and column directions, and the second pixel driving circuit groups are all disposed adjacent to the first pixel driving circuit groups in the row and column directions; the first pixel driving circuit group comprises two adjacent first pixel driving circuits which are positioned in the same row, and the second pixel driving circuit group comprises two adjacent second pixel driving circuits which are positioned in the same row; the two data lines correspondingly arranged on each column of the pixel driving circuits comprise a first data line and a second data line, the first data line is connected with the first pixel driving circuits on the same column, and the second data line is connected with the second pixel driving circuits on the same column.
In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fifth transistor, a capacitor, a first electrode of the fifth transistor is connected to a first power line, a second electrode of the fifth transistor is connected to a second electrode of the driving transistor, and the capacitor is connected between a gate of the driving transistor and the first power line; the active layer further includes: a third active portion for forming a channel region of the driving transistor; the display panel further includes a first conductive layer between the active layer and the second conductive layer, the first conductive layer further including: an orthographic projection of the third conductive part on the substrate covers an orthographic projection of the third active part on the substrate, and the third conductive part is used for forming a grid electrode of the driving transistor and a first electrode of the capacitor; the second conductive layer further includes: a fourth conductive portion, an orthographic projection of the fourth conductive portion on the substrate base plate and an orthographic projection of the third conductive portion on the substrate base plate are at least partially overlapped, the fourth conductive portion is used for forming a second electrode of the capacitor, and two adjacent fourth conductive portions in the row direction are connected with each other; the display panel further includes: the third conducting layer is positioned on one side, away from the substrate base plate, of the second conducting layer, the third conducting layer comprises the first power line, the orthographic projection of the first power line on the substrate base plate extends in the column direction, and the first power line is connected with the fourth conducting part through a through hole.
In one exemplary embodiment of the present disclosure, the first active portion includes: a fourth sub-active portion and a fifth sub-active portion, the active layer further including a sixth sub-active portion connected between the fourth sub-active portion and the fifth sub-active portion. The second conductive layer further includes: the first initial signal line extends in a row direction in an orthographic projection of the first initial signal line on the substrate base plate and overlaps with an orthographic projection portion of the sixth sub-active portion on the substrate base plate.
According to an aspect of the present disclosure, a display device is provided, wherein the display device includes the display panel described above.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of a display panel according to the present disclosure;
FIG. 2 is a timing diagram of nodes in a driving method of the pixel driving circuit of FIG. 1;
FIG. 3 is a structural layout of an exemplary embodiment of a display panel of the present disclosure;
FIG. 4 is a layout of the active layer structure of FIG. 3;
FIG. 5 is a structural layout of the second conductive layer in FIG. 3;
FIG. 6 is a structural layout of the first conductive layer in FIG. 3;
FIG. 7 is a layout of the structure of the active layer and the first conductive layer in FIG. 3;
FIG. 8 is a structural layout of another exemplary embodiment of a display panel of the present disclosure;
fig. 9 is a structural layout of the active layer in fig. 8;
fig. 10 is a structural layout of the first conductive layer in fig. 8;
fig. 11 is a structural layout of the second conductive layer in fig. 8;
fig. 12 is a structural layout of the third conductive layer in fig. 8;
fig. 13 is a structural layout of the fourth conductive layer in fig. 8;
fig. 14 is a structural layout of the active layer and the first conductive layer in fig. 8;
fig. 15 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in fig. 8;
fig. 16 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in fig. 8;
FIG. 17 is a partial cross-sectional view taken along dashed line AA in FIG. 8;
fig. 18 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
Fig. 1 is a schematic circuit diagram of a pixel driving circuit in an exemplary embodiment of a display panel according to the present disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. A first electrode of the first transistor T1 is connected to the node N, a second electrode is connected to the first initial signal terminal Vinit1, and a gate is connected to the first reset signal terminal Re 1; the second pole of the second transistor T2 is connected to the first pole of the driving transistor T3, and the first pole is connected to the node N; the grid is connected with a grid driving signal end Gate; the gate of the driving transistor T3 is connected to the node N; a first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode thereof is connected to the second electrode of the driving transistor T3, and a Gate thereof is connected to the Gate driving signal terminal Gate; a fifth transistor T5 having a first terminal connected to the first power terminal VDD, a second terminal connected to the second terminal of the driving transistor T3, and a gate connected to the enable signal terminal EM; a first electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor T3, and a gate electrode thereof is connected to the enable signal terminal EM; the seventh transistor T7 has a first pole connected to the second initial signal terminal Vinit2, a second pole connected to the second pole of the sixth transistor T6, and a gate connected to the second reset signal terminal Re 2. The capacitor C is connected between the gate of the driving transistor T3 and the first power source terminal VDD. The pixel driving circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power source terminal VSS. The transistors T1-T7 may be P-type transistors.
Fig. 2 is a timing diagram of nodes in a driving method of the pixel driving circuit of fig. 1. Here, Gate represents a timing of the Gate driving signal terminal Gate, Re1 represents a timing of the first reset signal terminal Re1, Re2 represents a timing of the second reset signal terminal Re2, EM represents a timing of the enable signal terminal EM, and Da represents a timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light emitting phase t 3. At the reset phase t 1: the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 is turned on, and the first initialization signal terminal Vinit1 inputs a first initialization signal to the node N. In the compensation phase t 2: a second reset signal terminal Re2, a Gate drive signal terminal Gate outputting low level signals, a fourth transistor T4, a second transistorT2 and the seventh transistor T7 are turned on, the data signal terminal Da outputs a driving signal to write a voltage Vdata + Vth to the node N, where Vdata is a voltage of the driving signal, Vth is a threshold voltage of the driving transistor T3, and the second initialization signal terminal Vinit2 inputs a second initialization signal to the second pole of the sixth transistor T6. Lighting phase t 3: the enable signal terminal EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the voltage Vdata + Vth stored in the capacitor C. According to the formula of the output current of the driving transistor, I ═ (mu WCox/2L) (Vgs-Vth)2Wherein μ is the carrier mobility; cox is the gate capacitance per unit area, W is the width of the drive transistor channel, L is the length of the drive transistor channel, Vgs is the difference in gate-source voltages of the drive transistors, and Vth is the threshold voltage of the drive transistors. The output current I ═ mu WCox/2L (Vdata + Vth-Vdd-Vth) of the driving transistor in the pixel driving circuit of the present disclosure2。
However, the gate of the driving transistor is in a floating state during the light emitting period, and the coupling effect of other signal lines on the gate of the driving transistor may cause the voltage of the gate of the driving transistor to change, thereby causing the light emitting unit to emit light abnormally. For example, in the line-by-line driving process of the display panel, the data line for providing the data signal terminal needs to input different data signals to each pixel driving circuit, the voltage on the data line fluctuates, and the voltage variation of the gate of the driving transistor can be caused by the coupling action of the data line on the gate of the driving transistor.
In view of this, the present exemplary embodiment first provides a display panel, which may include a plurality of pixel driving circuits distributed in an array in a row and column direction for supplying a driving current to a first electrode of a light emitting unit, and the pixel driving circuits may be as shown in fig. 1. The display panel may further include a substrate, an active layer, a second conductive layer, and an insulating layer between the active layer and the second conductive layer. As shown in fig. 3-5, fig. 3 is a structural layout of an exemplary embodiment of a display panel according to the present disclosure, fig. 4 is a structural layout of an active layer in fig. 3, and fig. 5 is a structural layout of a second conductive layer in fig. 3. The active layer is positioned at one side of the substrate, and the active layer may include a first active portion 61, a second active portion 62, and an eighth active portion 68 connected between the first active portion 61 and the second active portion 62, the first active portion 61 being used to form a channel region of the first transistor T1, and the second active portion 62 being used to form a channel region of the second transistor T2. A second conductive layer is located on a side of the active layer facing away from the substrate base board, the second conductive layer may include the second initial signal line Vinit2, an orthogonal projection of the second initial signal line Vinit2 on the substrate base board extends in the row direction X, and an orthogonal projection of the second initial signal line Vinit2 in an adjacent previous row of pixel driving circuits on the substrate base board partially overlaps an orthogonal projection of the eighth active portion 68 on the substrate base board in a present row of pixel driving circuits. Among them, the second initialization signal line Vinit2 may be used to provide the second initialization signal terminal in fig. 1.
In the present exemplary embodiment, the eighth active portion 68 is an equipotential point of the gate of the driving transistor, and the present disclosure overlaps an orthographic projection of the second initial signal line Vinit2 on the substrate in the previous row of pixel driving circuits with an orthographic projection of the eighth active portion 68 on the substrate in the present row of pixel driving circuits, so that the second initial signal line Vinit2 with a stable voltage can stabilize the eighth active portion 68, that is, the second initial signal line Vinit2 can stabilize the gate of the driving transistor. The arrangement can improve the voltage fluctuation problem of the grid electrode of the driving transistor in the light-emitting stage and provide the display effect of the display panel.
The second initialization signal line Vinit2 in the pixel driving circuit in the previous row refers to the second initialization signal line Vinit2 connected to the first electrode of the seventh transistor in the pixel driving circuit in the previous row. The eighth active portion 68 in the pixel driving circuit of the present row refers to the eighth active portion 68 connected between the first active portion and the second active portion in the pixel driving circuit of the present row. In the present exemplary embodiment, the orthographic projection of a certain structure on the substrate base plate extends in a certain direction, and it is understood that the orthographic projection of the structure on the substrate base plate extends linearly or extends bent in the direction.
In other exemplary embodiments, the pixel driving circuit in the display panel may have other structures. As long as the pixel driving circuit includes the first transistor, the second transistor, the driving transistor, and the seventh transistor, the eighth active portion connected to the gate of the driving transistor may be regulated by the second preliminary signal line connected to the first pole of the seventh transistor.
In the present exemplary embodiment, as shown in fig. 3, the display panel may further include a first conductive layer, and the first conductive layer may be between the active layer and the second conductive layer. As shown in fig. 6 and 7, fig. 6 is a structural layout of the first conductive layer in fig. 3, and fig. 7 is a structural layout of the active layer and the first conductive layer in fig. 3. Wherein an insulating layer is arranged between the active layer and the first conductive layer, and an insulating layer is arranged between the first conductive layer and the second conductive layer. As shown in fig. 3, 6, and 7, the first conductive layer may include a first reset signal line Re1, a Gate driving signal line Gate, and a third conductive part 13, an orthographic projection of the first reset signal line Re1 on the substrate extends in the row direction X and covers an orthographic projection of the first active part 61 on the substrate, a partial structure of the first reset signal line Re1 is used to form a Gate of the first transistor T1, and the first reset signal line Re1 is used to provide a first reset signal terminal in fig. 1. The orthographic projection of the Gate driving signal line Gate on the base substrate extends in the row direction X and covers the orthographic projection of the second active portion 62 on the base substrate, a partial structure of the Gate driving signal line Gate is used to form the Gate of the second transistor, and the Gate driving signal line Gate is used to provide the Gate driving signal terminal in fig. 1. As shown in fig. 3, 4 and 7, the active layer may further include a third active portion 63, and the third active portion 63 is used to form a channel region of the driving transistor T3. The orthographic projection of the third conductive part 13 on the substrate covers the orthographic projection of the third active part 63 on the substrate, and the third conductive part 13 is used for forming the gate of the driving transistor. The orthographic projection of the first reset signal line Re1 on the substrate base may be located on a side of the orthographic projection of the Gate drive signal line Gate on the substrate base away from the orthographic projection of the third conductive part 13 on the substrate base. The orthographic projection of the second initial signal line Vinit2 on the substrate in the pixel driving circuit of the previous row may be between the orthographic projection of the first reset signal line Re1 on the substrate in the pixel driving circuit of the present row and the orthographic projection of the Gate driving signal line Gate on the substrate in the pixel driving circuit of the present row. The first reset signal line Re1 in the pixel driving circuit of the current row refers to the first reset signal line Re1 connected to the gate of the first transistor in the pixel driving circuit of the current row; the Gate driving signal line Gate in the pixel driving circuit of the row refers to a Gate driving signal line Gate connected to the Gate of the second transistor in the pixel driving circuit of the row.
As shown in fig. 3, 4 and 7, the active layer may further include a fourth active portion 64 and a ninth active portion 69, the fourth active portion 64 is used for forming a channel region of the fourth transistor T4, the ninth active portion 69 is connected between the fourth active portion 64 and the data line, and the data line is used for providing the data signal terminal in fig. 1. The orthographic projection of the second initial signal line Vinit2 on the substrate in the pixel driving circuit in the previous row may also intersect the orthographic projection of the ninth active portion 69 on the substrate in the pixel driving circuit in the present row. Since the ninth active portion 69 is connected to the data line, the voltage variation of the gate of the driving transistor may be caused by the coupling effect of the ninth active portion 69 to the gate of the driving transistor. The present exemplary embodiment can shield a noise influence of a part of the ninth active portion 69 on the gate of the driving transistor by covering a part of the ninth active portion 69 through the second initialization signal line Vinit2 in the previous row of pixel driving circuits. The ninth active portion 69 in the pixel driving circuit of the present row is the ninth active portion 69 connected between the fourth transistor and the data line in the pixel driving circuit of the present row.
As shown in fig. 3, 4, 6, and 7, the orthographic projection of the Gate driving signal line Gate on the substrate may also cover the orthographic projection of the fourth active portion 64 on the substrate, and a partial structure of the Gate driving signal line Gate may be used to form the Gate of the fourth transistor.
As shown in fig. 3, 6 and 7, the active layer further includes a seventh active portion 67, and the seventh active portion 67 is used to form a channel region of the seventh transistor T7. The first conductive layer further includes a second reset signal line Re2, an orthogonal projection of the second reset signal line Re2 on the substrate extends in the row direction X and covers an orthogonal projection of the seventh active portion 67 on the substrate, and a partial structure of the second reset signal line Re2 is used to form a gate of the seventh transistor T7. Among them, the first reset signal line Re1 in the pixel driving circuit of the present row may share the second reset signal line Re2 in the pixel driving circuit of the previous row.
As shown in fig. 3, 4, and 5, an orthogonal projection of the eighth active portion 68 on the substrate base may extend in the column direction Y, and an orthogonal projection of the second initial signal line Vinit2 on the substrate base may intersect an orthogonal projection of the eighth active portion 68 on the substrate base.
The present exemplary embodiment further provides another display panel, as shown in fig. 8, which is a structural layout of another exemplary embodiment of the display panel of the present disclosure, a pixel driving circuit in the display panel may be as shown in fig. 1, and the display panel includes all structures of the display panel shown in fig. 3. In addition, the display panel further comprises a third conducting layer and a fourth conducting layer, wherein the substrate, the active layer, the first conducting layer, the second conducting layer, the third conducting layer and the fourth conducting layer are sequentially stacked, and an insulating layer is arranged between the structural layers. As shown in fig. 9-16, fig. 9 is a structural layout of the active layer in fig. 8, fig. 10 is a structural layout of the first conductive layer in fig. 8, fig. 11 is a structural layout of the second conductive layer in fig. 8, fig. 12 is a structural layout of the third conductive layer in fig. 8, fig. 13 is a structural layout of the fourth conductive layer in fig. 8, fig. 14 is a structural layout of the active layer and the first conductive layer in fig. 8, fig. 15 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in fig. 8, and fig. 16 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in fig. 8.
As shown in fig. 8, 9 and 14, the active layer may include a fifth active portion 65, a sixth active portion 66 and a tenth active portion 610 in addition to the first active portion 61, the second active portion 62, the third active portion 63, the fourth active portion 64, the eighth active portion 68 and the ninth active portion 69. Wherein the fifth active portion is used to form a channel region of the fifth transistor T5, the sixth active portion 66 is used to form a channel region of the sixth transistor T6, and the tenth active portion 610 is connected to an end of the seventh active portion 67 remote from the sixth active portion 66. The second active portion 62 may include a first sub-active portion 621 and a second sub-active portion 622, and accordingly, the second transistor has a double gate structure. The active layer further includes a third sub-active portion 623 connected between the first sub-active portion 621 and the second sub-active portion 622. The first active portion 61 may include a fourth sub-active portion 614 and a fifth sub-active portion 615, and accordingly, the first transistor has a double gate structure. The active layer may further include a sixth sub-active portion 616 connected between the fourth sub-active portion 614 and the fifth sub-active portion 615.
As shown in fig. 8, 10 and 14, the first conductive layer may include an enable signal line EM in addition to the Gate driving signal line Gate, the first reset signal line Re1, the second reset signal line Re2 and the third conductive part 13, and the enable signal line EM may be used to provide an enable signal terminal in fig. 1. The orthographic projection of the enable signal line EM on the substrate base plate may extend in the row direction X, and the orthographic projection of the enable signal line EM on the substrate base plate covers the orthographic projection of the fifth active portion 65 on the substrate base plate and the orthographic projection of the sixth active portion 66 on the substrate base plate. A partial structure of the enable signal line EM may be used to form the gate of the fifth transistor T5, and an outer partial structure of the enable signal line EM may be used to form the channel region of the sixth transistor T6. The third conductive portion 13 may be used to form both the gate of the drive transistor and the first electrode of the capacitor C. In this exemplary embodiment, the display panel may perform a conductor processing on the active layer by using the first conductive layer as a mask, that is, a channel region of the transistor may be formed in a region covered by the active layer, and a conductor structure may be formed in a region not covered by the active layer.
As shown in fig. 8, 11, and 15, the second conductive layer may include the first initial signal line Vinit1, the first conductive portion 21, and the fourth conductive portion 24, in addition to the second initial signal line Vinit 2. The first initial signal line Vinit1 may be used to provide the first initial signal terminal Vinit1 in fig. 1, an orthogonal projection of the first initial signal line Vinit1 on the substrate base may extend in the row direction X, and an orthogonal projection of the first initial signal line Vinit1 on the substrate base may be located on a side of an orthogonal projection of the first reset signal line Re1 on the substrate base away from an orthogonal projection of the second initial signal line Vinit2 on the substrate base. The orthographic projection of the first initial signal line Vinit1 on the substrate base may at least partially overlap with the orthographic projection of the sixth sub-active portion 616 on the substrate base, and the first initial signal line Vinit1 may play a role in stabilizing voltage of the sixth sub-active portion 616, so that the problem of leakage to the source and drain of the first transistor T1 due to voltage fluctuation of the sixth sub-active portion 616 may be improved.
An orthographic projection of the first conductive portion 21 on the substrate may extend in the row direction X, and an orthographic projection of the first conductive portion 21 on the substrate may intersect with an orthographic projection of the ninth active portion 69 on the substrate. The first conductive portion 21 may be connected to a regulated voltage source, and the first conductive portion 21 may shield a portion of the ninth active portion 69 from coupling to the gate of the driving transistor. The fourth conductive portions 24 may be used to form the other electrode of the capacitor C, and in the same row of pixel driving circuits, the adjacent fourth conductive portions 24 may be connected to each other, and further, the fourth conductive portions 24 may be provided with openings 241. As shown in fig. 8, 11 and 15, the second initial signal line Vinit2 may include: a first body line Vinit21 and a first bump Vinit22, an orthographic projection of the first body line Vinit21 on the substrate base plate may extend in the row direction X, and an orthographic projection of the first body line Vinit21 on the substrate base plate intersects with an orthographic projection of the eighth active portion 68 on the substrate base plate; a first bump Vinit22 is connected to the first body line Vinit21, and an orthographic projection of the first bump Vinit22 on the substrate base plate extends in the column direction Y. Wherein an orthographic projection of the first boss Vinit21 on the substrate in the pixel driving circuit of the previous row at least partially overlaps with an orthographic projection of the eighth active portion 68 on the substrate in the pixel driving circuit of the present row. This arrangement may increase the overlapping area of the second preliminary signal line Vinit2 and the eighth active portion 68, thereby increasing the voltage stabilizing effect of the second preliminary signal line Vinit2 on the eighth active portion 68. The first boss Vinit21 in the previous row of pixel driving circuits refers to the first boss Vinit21 in the second initial signal line Vinit2 in the previous row of pixel driving circuits.
As shown in fig. 8, 11 and 15, in the same row of pixel driving circuits, the orthographic projection of the first conductive part 21 on the substrate in the present column of pixel driving circuits may at least partially overlap with the orthographic projection of the third sub-active part 623 on the substrate in the adjacent column of pixel driving circuits. The first conductive part 21 may stabilize the voltage of the third sub-active part 623, and thus may improve a problem of leakage to a source and a drain of the second transistor T2 due to voltage fluctuation of the third sub-active part 623.
As shown in fig. 8, 12, and 16, the third conductive layer may include: a first connection portion 31, a second connection portion 32, a third connection portion 33, a fourth connection portion 34, a fifth connection portion 35, and a first power line VDD 1. The first connection portion 31 may connect the second initialization signal line Vinnit2 and the tenth active portion 610 through a via H, respectively, to connect the first pole and the second initialization signal terminal of the seventh transistor T7. It should be noted that the black square in the present exemplary embodiment represents the position of the via, and the present exemplary embodiment only marks a part of the via. The second connection part 32 may connect the third and eighth conductive parts 13 and 68 through vias, respectively, to connect the gate of the driving transistor T3 and the second and first poles of the first and second transistors T1 and T2, respectively. The third connection portion 33 may connect the first initial signal line Vinit1 and the active layer of the first active portion 61 on the side away from the eighth active portion 68 through vias, respectively, to connect the first initial signal terminal and the first pole of the first transistor. The fourth connection portion 34 may be connected to the ninth active portion 69 through a via to connect the first pole of the fourth transistor. The first power line VDD1 may be used to provide the first power source terminal in fig. 1, an orthographic projection of the first power line VDD1 on the substrate may extend in the column direction Y, one first power line VDD1 may be correspondingly disposed for each column of pixel driving circuits, and an orthographic projection of the first power line VDD1 on the substrate may be located between orthographic projections of two adjacent third conductive portions 13 in the row direction on the substrate. The first power line VDD1 may be connected to the active layer of the fifth active portion 65 on the side away from the third active portion 63 and the fourth conductive portion 24 through vias, respectively, to connect the first power supply terminal and the first electrode of the fifth transistor and the second electrode of the capacitor C. The fifth connection part 35 may connect the active layer between the seventh and sixth active parts 67 and 66 through a via to connect the second pole of the sixth and seventh transistors. In the present exemplary embodiment, the fourth conductive part 24 and the first power line VDD1 connected to each other in the row direction may form a mesh structure whose power line has a smaller self-resistance, so that the voltage drop of the power signal on the power line may be reduced. The first power line VDD1 may also be connected to the first conductive part 21 through a via to provide a regulated voltage to the first conductive part 21. It should be understood that the first conductive part 21 may also be connected to other regulated voltage sources, for example, the first conductive part 21 may also be connected to a first initial signal line or a second initial signal line.
As shown in fig. 8 and 13, the fourth conductive layer may include a second power line VDD2, a first data line Da1, a second data line Da2, a second conductive portion 42, and a fifth conductive portion 45. One second power line VDD2 may be provided for each column of pixel driving circuits, and a plurality of second power lines VDD2 may be provided in one-to-one correspondence with the plurality of first power lines VDD 1. The orthographic projection of the second power line VDD2 on the substrate base may extend in the column direction Y, the orthographic projection of the second power line VDD2 on the substrate base may at least partially overlap with the orthographic projection of the corresponding first power line VDD1 on the substrate base, the second power line VDD2 may be connected to the first power line VDD1 through a via, and the parallel arrangement of the first power line VDD1 and the second power line VDD2 may further reduce the self-resistance of the power lines. The second power line VDD2 may be connected to the first power line VDD1 through a plurality of vias, the orthographic projections of the plurality of vias connected between the first power line VDD1 and the second power line VDD2 on the substrate may be equally distributed along the column direction, and one via may be correspondingly disposed for each row of pixel driving circuits. Two data lines may be provided per column of pixel driving circuits: a first data line Da1, and a second data line Da 2. In two adjacent pixel driving circuits in the same column, an orthogonal projection of the tenth active portion 610 on the substrate in the pixel driving circuit in the previous row is located between an orthogonal projection of the eighth active portion 68 on the substrate in the pixel driving circuit in the current row and an orthogonal projection of the first data line D1 on the substrate in the row direction X. The orthographic projection of the eighth active portion 68 on the substrate in the present row of pixel driving circuits is located between the orthographic projection of the second data line Da2 on the substrate and the orthographic projection of the tenth active portion 610 on the substrate in the previous row of pixel driving circuits in the first direction. In the same column of pixel driving circuits, the first data line Da1 and the second data line Da2 are connected to pixel driving circuits of different rows, and the pixel driving circuits connected to the different data lines are alternately distributed in sequence in the column direction. The display panel can scan two rows of pixel driving circuits simultaneously, and the first data line Da1 and the second data line Da2 can independently provide data signals for the two rows of pixel driving circuits which are scanned simultaneously, so that the refresh rate of the display panel can be improved by the arrangement, and the display panel applying the design can realize the refresh rate of 120 Hz. For example, as shown in fig. 8 and 13, the second data line Da2 in the first column of pixel driving circuits is connected to the fourth connecting portion 34 in the first column of pixel driving circuits in the first row through a via hole to connect the first pole of the fourth transistor in the first column of pixel driving circuits in the first row and the data signal terminal; the first data line Da1 in the first column of pixel driving circuits is connected to the fourth connection portion 34 in the first column of pixel driving circuits in the second row of pixel driving circuits through a via hole to connect the first pole of the fourth transistor in the first column of pixel driving circuits in the second row of pixel driving circuits and the data signal terminal.
As shown in fig. 8 and 13, in two adjacent pixel driving circuits in the same column, an orthogonal projection of at least part of the structure of the first connection portion 31 in the pixel driving circuit in the upper row on the substrate is located between an orthogonal projection of the eighth active portion 68 in the pixel driving circuit in the current row on the substrate and an orthogonal projection of the first data line D1 on the substrate in the row direction X. The first connection portion 31 in the pixel driving circuit in the previous row is a first connection portion connected to the tenth active portion in the pixel driving circuit in the previous row. The orthographic projection of the structure A on the substrate base plate is positioned between the orthographic projection of the structure B on the substrate base plate and the orthographic projection of the structure C on the substrate base plate in the row direction, and it can be understood that the area covered by the infinite movement of the orthographic projection of the structure A on the substrate base plate along the row direction is overlapped with the orthographic projection of the structure B on the substrate base plate and the orthographic projection of the structure C on the substrate base plate. In the present exemplary embodiment, the first connection portion 31 in the previous row of pixel driving circuits may shield the noise influence of the partial structure of the first data line Da1 on the eighth active portion 68, i.e., shield the noise influence of the partial structure of the first data line Da1 on the gate of the driving transistor.
As shown in fig. 8 and 12, the first connection portion 31 may include a first via connection portion 311, a second via connection portion 312, and an extension portion 313 distributed along the column direction Y, the first via connection portion 311 is connected to the second initial signal line Vinit2 through a via, the second via connection portion 312 is connected to the first via connection portion 311 and to the tenth active portion 610 through a via, and the extension portion 313 is connected to one end of the second via connection portion 312, which is far from the first via connection portion 311. In two adjacent pixel driving circuits in the same column, the orthographic projection of the extension part 313 in the pixel driving circuit in the upper row on the substrate is located between the orthographic projection of the second connecting part 32 in the pixel driving circuit in the current row on the substrate and the orthographic projection of the first data line Da1 on the substrate in the row direction. The extension part 313 in the previous row of pixel driving circuits may shield the noise influence of the partial structure of the first data line Da1 on the second connection part 32, i.e., shield the noise influence of the partial structure of the first data line Da1 on the gate of the driving transistor.
As shown in fig. 8 and 13, the orthographic projection of the second conductive part 42 on the substrate may cover the orthographic projection of the second connecting part 32 on the substrate, the second conductive part 42 may be connected to a stable voltage source, the second conductive part 42 may stabilize the voltage of the second connecting part 32, and may shield the noise influence of other signal lines on the second connecting part 32, that is, the second conductive part 42 may shield the noise influence of other signal lines on the gate of the driving transistor. For example, the second conductive part 42 may shield the first and second data lines Da1 and Da2 from noise on the second connection part 32.
As shown in fig. 8, 12 and 13, the first power line VDD1 may include a second body line VDD11, a second bump VDD12, and an orthogonal projection of the second body line VDD11 on the substrate extending in the column direction Y; the second bump VDD12 is connected to the second body line VDD11, and an orthogonal projection of the second bump VDD12 on the substrate extends in the row direction X. In the same row of pixel driving circuits, the second protruding portion VDD12 in the present column of pixel driving circuits may be connected to the second conductive portion 42 in the adjacent column of pixel driving circuits through a via. The first power line VDD1 may provide a regulated voltage source to the second conductive portion 42. It should be understood that in other exemplary embodiments, the second conductive portion 42 may also be connected to other regulated voltage sources such as the first initial signal line, the second initial signal line, and the like.
As shown in fig. 8, 12 and 13, the fifth conductive part 45 may be connected to the fifth connection part 35 through a via hole for connecting the second pole of the sixth transistor, while the fifth conductive part 45 may be used for switching the first electrode of the light emitting unit.
It should be noted that, as shown in fig. 8 and 16, the black square drawn on the side of the third conductive layer away from the substrate indicates the via hole of the other level where the third conductive layer is connected to the side facing the substrate; the black squares drawn on the side of the fourth conductive layer facing away from the substrate base represent vias of other levels where the fourth conductive layer is connected to the side facing the substrate base. The black squares represent only the locations of the vias, and different vias represented by the black squares at different locations may penetrate through different insulating layers. For example, a via hole connected between the first connection portion 31 and the tenth active portion 610 penetrates through the insulating layer between the active layer and the third conductive layer; the via hole connected between the first connection portion 31 and the second preliminary signal line Vinit2 penetrates the insulating layer between the second conductive layer and the third conductive layer; the via hole connected between the second connection portion 32 and the third conductive portion 13 penetrates the insulating layer between the first conductive layer and the third conductive layer; the via hole connected between the second data line Da2 and the fourth connection portion 34 penetrates the insulating layer between the third conductive layer and the fourth conductive layer.
As shown in fig. 17, which is a partial cross-sectional view taken along a dotted line AA in fig. 8, the display panel may further include a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a first dielectric layer 75, a passivation layer 76, and a second dielectric layer 77, wherein the substrate 71, the buffer layer 72, the active layer, the first insulating layer 73, the first conductive layer, the second insulating layer 74, the second conductive layer, the first dielectric layer 75, the third conductive layer, the passivation layer 76, the second dielectric layer 77, and the fourth conductive layer are sequentially stacked. The first and second insulating layers 73 and 74 may be silicon oxide layers, the first and second dielectric layers 75 and 77 may be silicon nitride layers, and the passivation layer 76 and the buffer layer 72 may be made of silicon oxide, silicon nitride, or the like. The base substrate 71 may include a glass substrate, a barrier layer, and a polyimide layer, which are sequentially stacked, and the barrier layer may be an inorganic material. The material of the first conductive layer and the second conductive layer can be one of molybdenum, aluminum, copper, titanium and niobium or an alloy, or a molybdenum/titanium alloy or a laminated layer, and the like. The material of the third conductive layer and the fourth conductive layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum/titanium alloy or a laminate, or may be a titanium/aluminum/titanium laminate.
In addition, it should be noted that the attached drawings in the present disclosure may be used as reference in the actual process, but not limited thereto, for example: the width-length ratio of the channel, the thickness and the interval of each film layer and the width and the interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in the present disclosure are only schematic structural views.
As shown in fig. 18, in another exemplary embodiment of the display panel of the present disclosure, in this exemplary embodiment, the plurality of pixel driving circuits includes a plurality of first pixel driving circuit groups P01 and a plurality of second pixel driving circuit groups P02, the first pixel driving circuit groups P01 are all disposed adjacent to the second pixel driving circuit groups P02 in the row and column directions, and the second pixel driving circuit groups P02 are all disposed adjacent to the first pixel driving circuit groups P01 in the row and column directions; the first pixel driving circuit group P01 includes two adjacent first pixel driving circuits P1 located in the same row, and the second pixel driving circuit group P02 includes two adjacent second pixel driving circuits P2 located in the same row; the first data line Da1 is connected to the first pixel driving circuit P1 in the same column, and the second data line Da2 is connected to the second pixel driving circuit P2 in the same column.
The present exemplary embodiment also provides a display device, including the display panel described above. The display device can be a mobile phone, a tablet computer, a television and other display devices.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the following claims.
Claims (19)
1. A display panel comprises a plurality of pixel driving circuits distributed in an array along a row and column direction, wherein the pixel driving circuits are used for providing driving current for a first electrode of a light-emitting unit;
the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, and a seventh transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate of the driving transistor, a first electrode of the second transistor is connected to a gate of the driving transistor, a second electrode of the second transistor is connected to a first electrode of the driving transistor, a gate of the second transistor is connected to a gate driving signal line, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to a first electrode of the light emitting unit, and the display panel further includes:
a substrate base plate;
an active layer on one side of the substrate, the active layer including a first active portion for forming a channel region of the first transistor, a second active portion for forming a channel region of the second transistor, and an eighth active portion connected between the first active portion and the second active portion;
and the second conducting layer is positioned on one side of the active layer, which is far away from the substrate base plate, the second conducting layer comprises a second initial signal line, the orthographic projection of the second initial signal line on the substrate base plate extends along the row direction, and the orthographic projection of the second initial signal line in the upper row of pixel driving circuits on the substrate base plate at least partially overlaps with the orthographic projection of the eighth active part in the current row of pixel driving circuits on the substrate base plate.
2. The display panel according to claim 1, wherein the pixel driving circuit further comprises a fourth transistor having a first pole connected to a data line and a second pole connected to the second pole of the driving transistor;
the active layer further includes a fourth active portion for forming a channel region of the fourth transistor, a ninth active portion connected between the fourth active portion and the data line;
the orthographic projection of the second initial signal line on the substrate in the pixel driving circuit in the previous row is intersected with the orthographic projection of the ninth active part on the substrate in the pixel driving circuit in the current row.
3. The display panel according to claim 1, wherein a gate of the first transistor is connected to a first reset signal line, and a gate of the seventh transistor is connected to a second reset signal line;
the active layer further includes a seventh active portion for forming a channel region of the seventh transistor;
the display panel further includes: a first conductive layer between the active layer and the second conductive layer, the first conductive layer comprising:
the orthographic projection of the first reset signal line on the substrate extends along the row direction and covers the orthographic projection of the first active part on the substrate, and part of the structure of the first reset signal line is used for forming a grid electrode of the first transistor;
the orthographic projection of the second reset signal line on the substrate base plate extends along the row direction and covers the orthographic projection of the seventh active part on the substrate base plate, and the partial structure of the second reset signal line is used for forming the grid electrode of the seventh transistor;
the first reset signal line in the pixel driving circuit of the row shares the second reset signal line in the pixel driving circuit of the previous row.
4. The display panel according to claim 2, wherein a gate of the first transistor is connected to a first reset signal line, and a gate of the fourth transistor is connected to the gate drive signal line, the display panel further comprising: a first conductive layer between the active layer and the second conductive layer, the first conductive layer comprising:
the orthographic projection of the first reset signal line on the substrate extends along the row direction and covers the orthographic projection of the first active part on the substrate, and part of the structure of the first reset signal line is used for forming a grid electrode of the first transistor;
the orthographic projection of the gate driving signal line on the substrate extends along the row direction and covers the orthographic projection of the second active part on the substrate and the orthographic projection of the fourth active part on the substrate, part of the gate driving signal line is used for forming the gate of the second transistor, and the other part of the gate driving signal line is used for forming the gate of the fourth transistor.
5. The display panel according to claim 4, wherein an orthogonal projection of the second initial signal line on the substrate in the pixel driving circuit of the previous row is located between an orthogonal projection of the gate driving signal line on the substrate in the pixel driving circuit of the present row and an orthogonal projection of the first reset signal line on the substrate in the pixel driving circuit of the present row.
6. The display panel according to claim 1, wherein an orthogonal projection of the eighth active portion on the substrate base plate extends in a column direction, the second initial signal line includes:
a first main line extending in a row direction in an orthogonal projection on the substrate base plate, wherein an orthogonal projection of the first main line on the substrate base plate in the pixel driving circuit in the upper row intersects an orthogonal projection of the eighth active portion on the substrate base plate in the pixel driving circuit in the present row;
and in two adjacent pixel driving circuits in the same column, the orthographic projection of the first boss on the substrate base plate in the upper row of pixel driving circuits at least partially overlaps with the orthographic projection of the eighth active part on the substrate base plate in the current row of pixel driving circuits.
7. The display panel according to claim 1, wherein the pixel driving circuit further comprises a sixth transistor and a fourth transistor, wherein a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light emitting unit, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the second electrode of the driving transistor;
the active layer further includes:
a third active portion for forming a channel region of the driving transistor;
a sixth active portion connected to the third active portion, for forming a channel region of the sixth transistor;
a seventh active portion, connected to one end of the sixth active portion away from the third active portion, for forming a channel region of the seventh transistor;
a tenth active portion connected to one end of the seventh active portion away from the sixth active portion;
the display panel further includes:
the third conducting layer is positioned on one side, away from the substrate base plate, of the second conducting layer and comprises a first connecting part, and the first connecting part is connected with the second initial signal line and the tenth active part through via holes respectively;
the data lines comprise first data lines, the orthographic projection of the first data lines on the substrate extends along the column direction, one first data line is correspondingly arranged on each column of pixel driving circuits, and in two adjacent pixel driving circuits in the same column, the orthographic projection of the tenth active part in the pixel driving circuit in the previous row on the substrate is positioned between the orthographic projection of the eighth active part in the pixel driving circuit in the current row on the substrate and the orthographic projection of the first data lines on the substrate in the row direction;
in two adjacent pixel driving circuits in the same column, an orthogonal projection of at least part of the structure of the first connecting portion in the pixel driving circuit in the upper row on the substrate is located between an orthogonal projection of the eighth active portion in the pixel driving circuit in the current row on the substrate and an orthogonal projection of the first data line on the substrate in the row direction.
8. The display panel of claim 7, wherein the third conductive layer further comprises:
a second connection part connected to the eighth active part through a via hole and connected to the gate of the driving transistor;
the first connecting portion comprises a first via hole connecting portion, a second via hole connecting portion and an extending portion, the first via hole connecting portion is connected with the second initial signal line through a via hole, the second via hole connecting portion is connected with the first via hole connecting portion and is connected with the tenth active portion through a via hole, and the extending portion is connected to one end, away from the first via hole connecting portion, of the second via hole connecting portion;
in two adjacent pixel driving circuits in the same column, the orthographic projection of the extension part in the pixel driving circuit in the upper row on the substrate is located between the orthographic projection of the second connecting part in the pixel driving circuit in the current row on the substrate and the orthographic projection of the first data line on the substrate in the row direction.
9. The display panel according to claim 1, wherein the pixel driving circuit further comprises a fourth transistor and a fifth transistor, wherein a first electrode of the fourth transistor is connected to a data line, a second electrode of the fourth transistor is connected to a second electrode of the driving transistor, a first electrode of the fifth transistor is connected to a first power line, and a second electrode of the fifth transistor is connected to a second electrode of the driving transistor;
the active layer further includes a fourth active portion for forming a channel region of the fourth transistor, a ninth active portion connected between the fourth active portion and the data line;
an orthographic projection of the ninth active portion on the substrate base plate extends in a column direction, the second conductive layer further includes:
the orthographic projection of the first conductive part on the substrate base plate extends along the row direction and is intersected with the orthographic projection of the ninth active part on the substrate base plate, and the first conductive part is connected with a stable voltage source.
10. The display panel of claim 9, wherein the display panel further comprises:
the third conducting layer is positioned on one side, away from the substrate base plate, of the second conducting layer and comprises the first power line, the orthographic projection of the first power line on the substrate base plate extends in the column direction, and the first power line is connected with the first conducting part through a through hole.
11. The display panel of claim 9, wherein the second active portion comprises: a first sub-active portion and a second sub-active portion, the active layer further including a third sub-active portion connected between the first sub-active portion and the second sub-active portion;
in the same row of pixel driving circuits, the orthographic projection of the first conductive part in the pixel driving circuit of the current column on the substrate is at least partially overlapped with the orthographic projection of the third sub-active part in the pixel driving circuit of the adjacent column on the substrate.
12. The display panel of claim 1, wherein the display panel further comprises:
the third conductive layer is positioned on one side, away from the substrate base plate, of the second conductive layer, and the third conductive part comprises a second connecting part which is connected with the eighth active part through a through hole and is connected with the grid electrode of the driving transistor;
and the fourth conducting layer is positioned on one side of the third conducting layer, which is far away from the substrate base plate, and comprises a second conducting part, the second conducting part is connected with a stable voltage source, and the orthographic projection of the second conducting part on the substrate base plate covers the orthographic projection of the second connecting part on the substrate base plate.
13. The display panel according to claim 12, wherein the pixel driving circuit further comprises a fifth transistor having a first pole connected to a first power supply line and a second pole connected to the second pole of the driving transistor;
the third conductive layer includes:
the first power supply line, the orthographic projection of the first power supply line on the substrate base plate extends along the column direction, the first power supply line includes:
a second body line extending in a column direction in an orthogonal projection on the substrate base plate;
the second bulge part is connected to the second main body line, and the orthographic projection of the second bulge part on the substrate base plate extends along the row direction;
in the same row of pixel driving circuits, the second protruding portion in the pixel driving circuit of the current column is connected with the second conductive portion in the pixel driving circuit of the adjacent column through a via hole.
14. The display panel of claim 1, wherein the pixel driving circuit further comprises a fifth transistor having a first pole connected to a first power line and a second pole connected to a second pole of the driving transistor, the display panel further comprising:
the third conducting layer is positioned on one side, away from the substrate base plate, of the second conducting layer and comprises the first power line, and the orthographic projection of the first power line on the substrate base plate extends along the column direction;
the fourth conducting layer is positioned on one side, away from the substrate base plate, of the third conducting layer and comprises a second power line, the orthographic projection of the second power line on the substrate base plate extends in the column direction and at least partially overlaps with the orthographic projection of the first power line on the substrate base plate, and the second power line is connected with the first power line through a through hole.
15. The display panel according to claim 1, wherein the pixel driving circuit further comprises a fourth transistor having a first pole connected to a data line and a second pole connected to the second pole of the driving transistor;
the pixel driving circuits in each column are correspondingly provided with two data lines, in the same column of pixel driving circuits, the two data lines are connected with the pixel driving circuits in different rows, and the pixel driving circuits connected with the different data lines are sequentially and alternately distributed in the column direction.
16. The display panel according to claim 15, wherein the plurality of pixel drive circuits includes a plurality of first pixel drive circuit groups and a plurality of second pixel drive circuit groups, the first pixel drive circuit groups being disposed adjacent to the second pixel drive circuit groups in both the row and column directions, and the second pixel drive circuit groups being disposed adjacent to the first pixel drive circuit groups in both the row and column directions;
the first pixel driving circuit group comprises two adjacent first pixel driving circuits which are positioned in the same row, and the second pixel driving circuit group comprises two adjacent second pixel driving circuits which are positioned in the same row;
the two data lines correspondingly arranged on each column of the pixel driving circuits comprise a first data line and a second data line, the first data line is connected with the first pixel driving circuits on the same column, and the second data line is connected with the second pixel driving circuits on the same column.
17. The display panel according to claim 1, wherein the pixel driving circuit further comprises a fifth transistor having a first electrode connected to a first power line and a second electrode connected to a second electrode of the driving transistor, and a capacitor connected between the gate of the driving transistor and the first power line;
the active layer further includes:
a third active portion for forming a channel region of the driving transistor;
the display panel further includes a first conductive layer between the active layer and the second conductive layer, the first conductive layer further including:
an orthographic projection of the third conductive part on the substrate covers an orthographic projection of the third active part on the substrate, and the third conductive part is used for forming a grid electrode of the driving transistor and a first electrode of the capacitor;
the second conductive layer further includes:
a fourth conductive portion, an orthographic projection of the fourth conductive portion on the substrate base plate and an orthographic projection of the third conductive portion on the substrate base plate are at least partially overlapped, the fourth conductive portion is used for forming a second electrode of the capacitor, and two adjacent fourth conductive portions in the row direction are connected with each other;
the display panel further includes:
and the third conducting layer is positioned on one side of the second conducting layer, which is deviated from the substrate base plate, and comprises the first power line, the orthographic projection of the first power line on the substrate base plate extends along the column direction, and the first power line is connected with the fourth conducting part through a through hole.
18. The display panel of claim 1, wherein the first active portion comprises: a fourth sub-active portion and a fifth sub-active portion, the active layer further including a sixth sub-active portion connected between the fourth sub-active portion and the fifth sub-active portion;
the second conductive layer further includes:
the first initial signal line extends in a row direction in an orthographic projection of the first initial signal line on the substrate base plate and overlaps with an orthographic projection portion of the sixth sub-active portion on the substrate base plate.
19. A display device comprising the display panel according to any one of claims 1 to 18.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111431992.XA CN114122101A (en) | 2021-11-29 | 2021-11-29 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111431992.XA CN114122101A (en) | 2021-11-29 | 2021-11-29 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114122101A true CN114122101A (en) | 2022-03-01 |
Family
ID=80371321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111431992.XA Pending CN114122101A (en) | 2021-11-29 | 2021-11-29 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114122101A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115152030A (en) * | 2022-05-31 | 2022-10-04 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN115835730A (en) * | 2022-05-31 | 2023-03-21 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN116097442A (en) * | 2022-06-21 | 2023-05-09 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2023193207A1 (en) * | 2022-04-07 | 2023-10-12 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2023198113A1 (en) * | 2022-04-15 | 2023-10-19 | 京东方科技集团股份有限公司 | Array substrate, display panel and display apparatus |
| WO2023206157A1 (en) * | 2022-04-27 | 2023-11-02 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| WO2023230810A1 (en) * | 2022-05-31 | 2023-12-07 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2023230915A1 (en) * | 2022-05-31 | 2023-12-07 | 京东方科技集团股份有限公司 | Display substrates and display apparatus |
| WO2023245676A1 (en) * | 2022-06-24 | 2023-12-28 | 京东方科技集团股份有限公司 | Pixel driving circuit and driving method therefor, display panel and display apparatus |
| WO2024045059A1 (en) * | 2022-08-31 | 2024-03-07 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2024065591A1 (en) * | 2022-09-30 | 2024-04-04 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| WO2024149064A1 (en) * | 2023-01-13 | 2024-07-18 | 京东方科技集团股份有限公司 | Display panel, preparation method therefor, and display apparatus |
-
2021
- 2021-11-29 CN CN202111431992.XA patent/CN114122101A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023193207A1 (en) * | 2022-04-07 | 2023-10-12 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2023198113A1 (en) * | 2022-04-15 | 2023-10-19 | 京东方科技集团股份有限公司 | Array substrate, display panel and display apparatus |
| WO2023206157A1 (en) * | 2022-04-27 | 2023-11-02 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| WO2023230810A1 (en) * | 2022-05-31 | 2023-12-07 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN115835730A (en) * | 2022-05-31 | 2023-03-21 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2023230915A1 (en) * | 2022-05-31 | 2023-12-07 | 京东方科技集团股份有限公司 | Display substrates and display apparatus |
| CN115835730B (en) * | 2022-05-31 | 2023-09-08 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN115152030A (en) * | 2022-05-31 | 2022-10-04 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2023230885A1 (en) * | 2022-05-31 | 2023-12-07 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| CN116097442B (en) * | 2022-06-21 | 2023-09-29 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN116097442A (en) * | 2022-06-21 | 2023-05-09 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2023245444A1 (en) * | 2022-06-21 | 2023-12-28 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| WO2023245676A1 (en) * | 2022-06-24 | 2023-12-28 | 京东方科技集团股份有限公司 | Pixel driving circuit and driving method therefor, display panel and display apparatus |
| WO2024045059A1 (en) * | 2022-08-31 | 2024-03-07 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2024065591A1 (en) * | 2022-09-30 | 2024-04-04 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| WO2024149064A1 (en) * | 2023-01-13 | 2024-07-18 | 京东方科技集团股份有限公司 | Display panel, preparation method therefor, and display apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114122101A (en) | Display panel and display device | |
| CN112885850B (en) | Display panel and display device | |
| CN114495835B (en) | Pixel driving circuit, driving method thereof, display panel and display device | |
| CN216818344U (en) | Display panel and display device | |
| CN113053982A (en) | Display panel and display device | |
| CN114373773A (en) | Display panel and display device | |
| CN113611247B (en) | Display substrate and display panel | |
| WO2022147679A1 (en) | Display panel and display apparatus | |
| CN113517322B (en) | Display panel and display device | |
| CN115274708A (en) | Display panel and display device | |
| CN114930543A (en) | Array substrate and display device | |
| WO2023159602A1 (en) | Display panel and display device | |
| EP4303931A1 (en) | Display panel and display apparatus | |
| US12020642B2 (en) | Display panel and display device | |
| US20220352278A1 (en) | Array substrate and display device | |
| CN115605943A (en) | Display panel and display device | |
| CN117321768A (en) | Display panel and display device | |
| CN117223045A (en) | Display panel and display device | |
| CN117642801A (en) | Display panel and display device | |
| CN117242512A (en) | Pixel circuit, driving method, display panel, driving method and display device | |
| CN115732509A (en) | Display panel and display device | |
| CN116454089A (en) | Display panel and display device | |
| CN117337099A (en) | Display panel and display device | |
| CN118015987A (en) | Display panel and display device | |
| CN118104419A (en) | Display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |