CN114121637A - 一种用于多晶硅层的研磨工艺及晶圆 - Google Patents

一种用于多晶硅层的研磨工艺及晶圆 Download PDF

Info

Publication number
CN114121637A
CN114121637A CN202010897529.3A CN202010897529A CN114121637A CN 114121637 A CN114121637 A CN 114121637A CN 202010897529 A CN202010897529 A CN 202010897529A CN 114121637 A CN114121637 A CN 114121637A
Authority
CN
China
Prior art keywords
wafer
grinding
polishing
cleaning
grinding process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010897529.3A
Other languages
English (en)
Inventor
姚斯嘉
曹雪平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Warship Chip Manufacturing Suzhou Ltd By Share Ltd
Original Assignee
Warship Chip Manufacturing Suzhou Ltd By Share Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Warship Chip Manufacturing Suzhou Ltd By Share Ltd filed Critical Warship Chip Manufacturing Suzhou Ltd By Share Ltd
Priority to CN202010897529.3A priority Critical patent/CN114121637A/zh
Publication of CN114121637A publication Critical patent/CN114121637A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本发明公开了一种用于多晶硅层的研磨工艺,包含以下步骤:1)测量晶圆厚度;2)对晶圆的多晶硅层进行化学机械研磨以获得研磨面;3)对研磨面进行RCA清洗;4)对研磨面进行抛光研磨;5)对研磨面进行CPC清洗;6)再次测量晶圆的厚度。该研磨工艺能够有效减少多晶硅表面随机分布的凸起缺陷。本发明同时提供一种使用上述研磨工艺制备的晶圆。

Description

一种用于多晶硅层的研磨工艺及晶圆
技术领域
本发明涉及半导体技术领域,特别涉及一种用于半导体器件的研磨工艺及使用该研磨工艺制备的晶圆。
背景技术
化学机械研磨(CMP)是晶圆制造中常用的表面平坦化技术,其利用化学腐蚀作用和机械去除作用相结合来提高晶圆表面的平坦程度。传统研磨工艺在化学机械研磨后需依次进行RCA清洗和CPC清洗。其中,CPC清洗过程中有机材料制成的清洗刷在清洗多晶硅表面过程中会有有机残渣滞留,在多晶硅表面形成主要成分为碳的凸起缺陷。如图1所示,在随机抽检的10片晶圆中均具有凸起缺陷,且平均数量大于90粒/每片。由于这些凸起缺陷随机分布于多晶硅表面,即便经过多晶硅蚀刻也无法彻底减少,影响整个晶圆的质量。
因此,如何减少凸起缺陷成为晶圆制备领域亟待解决的技术问题。
发明内容
为了解决现有的技术问题,本发明提出了一种有效减少凸起缺陷的多晶硅层的研磨工艺,以及使用该研磨工艺制备的晶圆。
依据本发明,提供一种用于多晶硅层的研磨工艺,包含以下步骤:
1)测量晶圆厚度;
2)对晶圆的多晶硅层进行化学机械研磨以获得研磨面;
3)对研磨面进行RCA清洗;
4)对研磨面进行抛光研磨;
5)对研磨面进行CPC清洗;
6)再次测量晶圆的厚度。
依据本发明的一个实施例,步骤2)中RCA清洗包含使用含氨水的过氧化氢溶液进行清洗。
依据本发明的一个实施例,步骤4)中对晶圆施加的压力为1.7-2.2psi。
依据本发明的一个实施例,步骤4)中抛光时间为40-80s。
依据本发明的一个实施例,步骤4)中抛光时间为60s。
依据本发明的一个实施例,步骤4)中使用纯净水作为抛光剂。
依据本发明的一个实施例,步骤4)中使用硬度为30D的多孔高分子聚合物的抛光垫。
依据本发明,提供一种使用上述研磨工艺制备的晶圆。
由于采用以上技术方案,本发明与现有技术相比,在CMP研磨后清洗(CPC)前添加抛光研磨步骤,以获得光滑平坦的晶圆表面,有效避免CPC过程中有机物残留于晶圆表面形成凸起缺陷。
附图说明
图1示出了现有技术中随机分布有凸起缺陷的多晶硅表面;
图2示出了本发明的用于多晶硅层的研磨工艺的一个实施例的流程图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,下面结合实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
图2示出了依据本发明的用于多晶硅层的研磨工艺的一个实施例的具体流程。研磨工艺总体包含以下步骤:
1)测量晶圆厚度
获得晶圆研磨前的初始厚度D0。
2)对晶圆的多晶硅层进行化学机械研磨以获得研磨面
基于化学腐蚀作用和机械去除作用来获得具有一定平坦程度的研磨面。在该步骤中,技术人员可以针对不同的产品需求来调整具体的研磨参数,以便在允许的晶圆厚度范围内获得符合要求的平坦晶面。研磨过程中,研磨剂的颗粒状磨料一方面可以磨掉晶圆表面较大的凸起,使研磨面总体趋于平坦;另一方面由于其自身质地较硬且呈游离态,同时也会在研磨表面留下细小、密集且分布不规则的划痕。
3)对研磨面进行RCA清洗
RCA清洗是将研磨后的晶圆浸泡于酸性和/或碱性的洗液中于特定温度下泡洗。常见的洗液有含硫酸的酸性过氧化氢溶液(SPM清洗)、用含胺的弱碱性过氧化氢溶液(APM清洗)、氢氟酸溶液(DHP清洗)、含盐酸的酸性过氧化氢溶液(HMP清洗)等。在本发明的实施例中,RCA清洗是将研磨后的晶圆浸入含氨水的过氧化氢溶液进行清洗,以实现改善晶圆表面疏水性的目的。
4)对研磨面进行抛光研磨
抛光研磨的主要目的为进一步改善研磨面的平坦度,例如消除研磨过程中在晶圆表面形成的划痕等。
为避免抛光剂在晶圆表面形成二次划痕,可选用流动的纯净水作为抛光剂,以在抛光过程中起到润滑晶圆表面的作用,同时还可避免摩擦温度过高而损坏晶圆。由于待抛光的晶圆表面为质地较软的多晶硅材质,可选用材质同样较软的抛光垫——例如硬度为30D的多孔高分子聚合物的抛光垫,并在晶圆背面施加适当的压力——例如1.7-2.2psi,优选2psi,以便在使研磨表面进一步平坦化的同时不会影响晶圆总体的厚度。在本发明的实施例中,抛光研磨40-80s——优选60s——即可消除研磨过程中在晶圆表面形成的划痕。
5)对研磨面进行CPC清洗
CPC清洗通常使用有机物材质的清洗刷蘸取清洗液对晶圆表面进行刷洗。传统技术中经研磨后的晶圆表面上分布有不规则的划痕——实质上为尺寸较小的高低不同的沟壑,在与清洗刷反复摩擦过程导致刷头有碎屑脱落并粘附于晶圆表面,形成不规则分布的凸起缺陷。然而,经抛光研磨后的晶圆表面消除了研磨过程中在晶圆表面形成的划痕,进而有效避免了刷头碎屑脱落并粘附于晶圆表面。
6)再次测量晶圆的厚度
获得晶圆研磨后的最终厚度D1。该最终厚度D1与初始厚度D0的差即为整个研磨过程中晶圆减薄的厚度。
在使用依据本发明的研磨工艺制备的晶圆中随机抽检10片晶圆进行检测,平均凸起缺陷数量小于20粒/每片,明显优于现有研磨工艺制备的晶圆。
以上实施例仅表达了本发明的实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。

Claims (8)

1.一种用于多晶硅层的研磨工艺,其特征在于,包含以下步骤:
1)测量晶圆厚度;
2)对所述晶圆的多晶硅层进行化学机械研磨以获得研磨面;
3)对所述研磨面进行RCA清洗;
4)对所述研磨面进行抛光研磨;
5)对所述研磨面进行CPC清洗;
6)再次测量晶圆的厚度。
2.根据权利要求1所述的研磨工艺,其特征在于,步骤2)中所述RCA清洗包含使用含氨水的过氧化氢溶液进行清洗。
3.根据权利要求1所述的研磨工艺,其特征在于,步骤4)中对所述晶圆施加的压力为1.7-2.2psi。
4.根据权利要求1所述的研磨工艺,其特征在于,步骤4)中抛光时间为40-80s。
5.根据权利要求1所述的研磨工艺,其特征在于,步骤4)中抛光时间为60s。
6.根据权利要求1所述的研磨工艺,其特征在于,步骤4)中使用纯净水作为抛光剂。
7.根据权利要求1所述的研磨工艺,其特征在于,步骤4)中使用硬度为30D的多孔高分子聚合物的抛光垫。
8.一种使用权利要求1-7任一项所述的研磨工艺制备的晶圆。
CN202010897529.3A 2020-08-31 2020-08-31 一种用于多晶硅层的研磨工艺及晶圆 Pending CN114121637A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010897529.3A CN114121637A (zh) 2020-08-31 2020-08-31 一种用于多晶硅层的研磨工艺及晶圆

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010897529.3A CN114121637A (zh) 2020-08-31 2020-08-31 一种用于多晶硅层的研磨工艺及晶圆

Publications (1)

Publication Number Publication Date
CN114121637A true CN114121637A (zh) 2022-03-01

Family

ID=80360123

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010897529.3A Pending CN114121637A (zh) 2020-08-31 2020-08-31 一种用于多晶硅层的研磨工艺及晶圆

Country Status (1)

Country Link
CN (1) CN114121637A (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5913712A (en) * 1995-08-09 1999-06-22 Cypress Semiconductor Corp. Scratch reduction in semiconductor circuit fabrication using chemical-mechanical polishing
EP1050369A2 (en) * 1999-04-29 2000-11-08 Ebara Corporation Method and apparatus for polishing workpieces
CN101722469A (zh) * 2008-10-13 2010-06-09 台湾积体电路制造股份有限公司 对晶圆进行化学机械研磨工艺的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5913712A (en) * 1995-08-09 1999-06-22 Cypress Semiconductor Corp. Scratch reduction in semiconductor circuit fabrication using chemical-mechanical polishing
EP1050369A2 (en) * 1999-04-29 2000-11-08 Ebara Corporation Method and apparatus for polishing workpieces
CN101722469A (zh) * 2008-10-13 2010-06-09 台湾积体电路制造股份有限公司 对晶圆进行化学机械研磨工艺的方法

Similar Documents

Publication Publication Date Title
JP3004891B2 (ja) 表面粗さを減少させるための半導体ウエハの粗研磨法
US7749908B2 (en) Edge removal of silicon-on-insulator transfer wafer
US6406923B1 (en) Process for reclaiming wafer substrates
US7510974B2 (en) CMP process
US6227944B1 (en) Method for processing a semiconductor wafer
WO2012002525A1 (ja) シリコンウェーハの研磨方法
KR20000017512A (ko) 웨이퍼 기판 재생방법 및 웨이퍼 기판 재생을 위한 연마액 조성물
KR20160113723A (ko) 반도체 웨이퍼의 제조 방법
JP2010109370A (ja) 半導体ウェーハの両面をポリッシングする方法
US20010039101A1 (en) Method for converting a reclaim wafer into a semiconductor wafer
CN111095491A (zh) 硅晶片的双面抛光方法
US6189546B1 (en) Polishing process for manufacturing dopant-striation-free polished silicon wafers
CN114121637A (zh) 一种用于多晶硅层的研磨工艺及晶圆
JP4683233B2 (ja) 半導体ウェーハの製造方法
CN113043159A (zh) 硅晶圆的研磨方法
JP4681970B2 (ja) 研磨パッドおよび研磨機
KR100883511B1 (ko) 반도체 웨이퍼 연마 방법 및 장치
US20230197455A1 (en) Methods for polishing semiconductor substrates
JP2005005490A (ja) 半導体ウェーハの製造方法
JP2003100668A (ja) 半導体ウェーハの研磨方法
KR100963043B1 (ko) 웨이퍼의 제조방법 및 웨이퍼의 연마장치
JPH10321566A (ja) 半導体装置の研磨方法
KR101581469B1 (ko) 웨이퍼 연마방법
JPH11291157A (ja) 半導体ウエ―ハの研磨方法及び該研磨方法に用いる研磨布
JP2004106134A (ja) 加工用基板固定装置およびその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20220301