CN114117943A

CN114117943A - Time sequence prediction method for physical design layout stage

Info

Publication number: CN114117943A
Application number: CN202210088465.1A
Authority: CN
Inventors: 贺旭; 傅智勇
Original assignee: Hunan University
Current assignee: Hunan University
Priority date: 2022-01-26
Filing date: 2022-01-26
Publication date: 2022-03-01
Anticipated expiration: 2042-01-26
Also published as: CN114117943B

Abstract

The invention provides a time sequence prediction method for a physical design layout stage, which comprises the following steps: step 1, dividing the acquired process library, circuit netlist and layout result data thereof into a training set and a test set, and extracting circuit time sequence characteristics of the training set and circuit time sequence characteristics of the test set respectively based on the training set and the test set; and 2, inputting the circuit time sequence characteristics of the training set and the Sign-Off time sequence results corresponding to the training set into a random forest model for training to obtain a time delay prediction model based on the wire network. The difference between the time sequence result of the time sequence prediction and the time sequence result of Sign-Off is small, the accuracy of the time sequence prediction is improved, the additional influence of performance and power consumption caused by time sequence optimization can be well guided in the chip design process, the accurate time sequence prediction is realized, and the whole chip design period and the whole chip design cost are reduced.

Description

Time sequence prediction method for physical design layout stage

Technical Field

The invention relates to the technical field of time sequence prediction, in particular to a time sequence prediction method for a physical design layout stage.

Background

In chip design, the accuracy of time sequence analysis is crucial to guiding time sequence optimization and ensuring the time sequence convergence and the operation performance of a chip. In the layout stage, a rapid and accurate time sequence analysis tool can guide time sequence optimization in the layout stage, and the design period is shortened.

Static Timing Analysis (STA), in which a circuit netlist is modeled as a Directed Acyclic Graph (DAG), is an important means for verifying Timing closure. The Input/Output Ports (PIO) and Pins (Pins) in the circuit diagram correspond to nodes of the directed acyclic graph, and the time sequence arcs inside the wire net connecting wires or gates correspond to edges of the directed acyclic graph. Time delay of the timing arc, weight of the corresponding edge. In a directed acyclic graph, all nodes may be topologically ordered, and the Arrival Time (AT) of each node is calculated by layer traversal. Then, the Required Arrival Time (RAT) of each node in the circuit diagram is reversely calculated according to the required Time of the terminal node (the register data end or the output port). And finally, obtaining the time margin (Slack) of each node according to the difference between the arrival time of each node and the required arrival time of each node. If the margin is negative, the time delay requirement is not met, and the time sequence optimization is required in the subsequent design. According to the directed acyclic graph, the edge Delay belongs to the internal Delay of a Gate circuit, and can be divided into Gate Delay (Gate Delay) and line Delay (Wire Delay). In static timing analysis, gate delay can be calculated by a table look-up method according to the characteristics of components in a process library (Lib file) through the Slew values of an output load and an input pin, and line delay can be calculated by a line delay model according to wiring information.

However, in the layout stage, no wiring is provided, and no specific Resistance and Capacitance (RC) information, gate delay and line delay can be accurately calculated. Therefore, at present, the timing analysis is performed in the layout stage mainly by the following three methods:

pessimistic prediction: because of the lack of wiring information, pessimistic predictions are added to the circuit when performing timing analysis to ensure that the circuit will meet timing requirements even in the worst case. In practice, the traditional pessimistic prediction method has an additional impact on chip performance and power consumption, since the worst case scenario is rare. Practical experience has shown that based on pessimistic predictions of EDA tools, the difference between their predicted performance and the performance after final tape-out can be as high as 30%.

And adding design iteration: if the subsequent wiring result cannot meet the time delay requirement and the design is not converged, local correction is needed, and even the previous stage redesign is returned. Repeated iterations of such a design can significantly increase the overall chip design cycle and cost.

Machine learning based timing prediction: in order to improve excessive pessimism in prediction, improve the accuracy of prediction and reduce design iteration, a machine learning method is introduced. The method trains a timing model by using existing design data. The obtained model can provide time sequence prediction for unknown circuit design under the same process in the layout stage. Machine learning-based timing prediction requires extraction of as many timing-related features as possible at the layout stage and building of a prediction model. The correlation between the predicted result and the Sign-Off time sequence result is the main basis for measuring the accuracy of the model.

Disclosure of Invention

The invention provides a time sequence prediction method in a physical design layout stage, which aims to solve the problems that the difference between the time sequence prediction performance of the traditional time sequence prediction method and the time sequence performance of final Sign-Off is large, the time sequence optimization cannot be well guided in the chip design process, the performance and power consumption are additionally influenced, and the inaccurate time sequence prediction can greatly increase the whole chip design period and the cost.

In order to achieve the above object, an embodiment of the present invention provides a method for predicting a timing sequence of a physical design layout phase, including:

step 1, dividing the acquired process library, circuit netlist and layout result data thereof into a training set and a test set, and extracting circuit time sequence characteristics of the training set and circuit time sequence characteristics of the test set respectively based on the training set and the test set;

step 2, inputting the circuit time sequence characteristics of the training set and the Sign-Off time sequence results corresponding to the training set into a random forest model for training to obtain a time delay prediction model based on a wire network;

step 3, inputting the circuit time sequence characteristics of the test set into a time delay prediction model based on a wire network to perform time delay prediction, and obtaining a wire network Sign-Off time delay prediction result of each circuit in the test set;

step 4, performing circuit diagram topology traversal on the wire net Sign-Off time delay prediction results of all circuits in the test set, and calculating the time margin of the output pin of each wire net of each circuit;

and 5, distinguishing a critical path from a non-critical path according to the calculated time margin to obtain a critical path prediction result of each circuit in the test set.

Wherein, the step 1 specifically comprises:

step 11, dividing a given process library, a given circuit netlist and layout result data thereof into a training set and a test set;

step 12, performing pre-wiring analysis on the data in the training set and the test set respectively to obtain a training set pre-wiring analysis result and a test set pre-wiring analysis result;

step 13, obtaining an RC network generated based on training set pre-wiring analysis according to the training set pre-wiring analysis result, and obtaining an RC network generated based on test set pre-wiring analysis according to the test set pre-wiring analysis result;

step 14, extracting circuit timing sequence characteristics by combining the circuit netlist data and the layout result data thereof in the training set and the process library data according to the pre-wiring analysis result of the training set to obtain the circuit timing sequence characteristics of the training set; and according to the test set pre-wiring analysis result, circuit timing sequence feature extraction is carried out by combining the circuit netlist data and the layout result data thereof as well as the process library data in the test set to obtain the circuit timing sequence feature of the test set.

Wherein the step 12 specifically includes:

step 121, performing pre-wiring analysis on each circuit in the training set, including the following steps:

step 1211, obtaining position information of pins in each net of each circuit in the training set, dividing the multi-terminal net into a plurality of two-terminal connection relations by adopting a minimum Steiner tree algorithm according to the position information of the pins in each net of each circuit in the training set, and performing L-type wiring on each two-terminal connection relation to obtain a pre-wiring analysis result of the training set.

Wherein the step 12 specifically includes:

step 122, performing pre-wiring analysis on each circuit in the test set, including the following steps:

step 1221, obtaining position information of pins in each net of each circuit in the test set, dividing the multi-terminal net into a plurality of two-terminal connection relations by adopting a minimum Steiner tree algorithm according to the position information of the pins in each net of each circuit in the test set, and performing L-type wiring on each two-terminal connection relation to obtain a pre-wiring analysis result of the test set.

Wherein, the step 14 specifically comprises:

the circuit timing characteristics of the training set and the circuit timing characteristics of the test set both include: drive strength, number of fan-outs, output load, gate transition tilt under a nonlinear model, gate delay under a nonlinear model, distance, Elmore delay, Context Elmore delay, and D2M delay.

Wherein, the step 2 specifically comprises:

in a time delay prediction model based on a wire network, gate time delay and line time delay are combined together for prediction, the gate time delay of a driving gate and the line time delay of a line of a certain fan-out gate are combined from one input of the driving gate to a corresponding fan-out receiving end after the gate time delay of the driving gate and the line time delay of the line of the fan-out gate, and the two time delays are combined to be called the wire network time delay, and the time delay prediction model based on the wire network is used for predicting the wire network time delay;

in a delay prediction model based on nets, the output pin nodes of gates are removed in a directed acyclic graph, and a net is combined from one input pin of a gate to one fanout input pin of the gate into an edge of the directed acyclic graph, and the edge weight comprises the gate delay from the input pin to the output pin in a driver and the line delay from the drive output pin to the fanout input pin.

Wherein, the step 2 specifically comprises:

in the time delay prediction model based on the wire network, the gate time delay has 4 different values, which correspond to the following four conditions: the signal of the gate input pin is a rising edge, and the signal of the gate output pin is a falling edge; the signal of the gate input pin is a rising edge, and the signal of the gate output pin is a rising edge; the signal of the gate input pin is a falling edge, and the signal of the gate output pin is a rising edge; the signal at the gate input pin is a falling edge, and the signal at the gate output pin is a falling edge.

Wherein, the step 2 further comprises:

the signal jump of the input pin of the line delay is consistent with the signal jump of the output pin, when the combination driving gate and the fan-out connecting line of the combination driving gate are used as a line network, the time delay of one line network considers the four conditions, one line network corresponds to 4 samples, the time delay under different conditions is respectively predicted, and the time sequence characteristics and the Sign-Off time delay under different conditions are different, so the characteristics and the time delay corresponding to different samples are different.

Wherein, the step 4 specifically comprises:

and traversing the topology of the circuit diagram according to the prediction result of the line net Sign-Off time delay of each circuit in the test set, calculating the arrival time delay of the output pin of each line net of each circuit in the test set, and further obtaining the time margin of the output pin of each line net of each circuit in the test set.

Wherein, the step 5 specifically comprises:

distinguishing a critical path and a non-critical path of each circuit based on the time margin of the output pin of each net of each circuit in the test set, sequentially judging whether the time margin of the output pin of each net of each circuit in the test set is negative, and when the time margin of the output pin of the current net is negative, a circuit corresponding to the current net generates time sequence violation, and the current net is the critical path; and when the time margin of the output pin of the current net is positive, the time sequence of the circuit corresponding to the current net is normal, the current net is a non-critical path, and the critical path prediction result of each circuit in the test set is obtained.

The scheme of the invention has the following beneficial effects:

according to the time sequence prediction method in the physical design layout stage, the difference between the time sequence prediction and the time sequence result of Sign-Off is small, the accuracy of the time sequence prediction is improved, the additional influence of performance and power consumption brought by time sequence optimization can be well guided in the chip design process, the accurate time sequence prediction is realized, and the design period and the cost of the whole chip are reduced.

Drawings

FIG. 1 is a flow chart embodying the present invention;

FIG. 2 is an overall flow chart of the present invention;

FIG. 3 is a schematic diagram of the present invention converting a circuit netlist graph into a directed acyclic graph, wherein (a) is the present invention circuit netlist graph; (b) is a directed acyclic graph of the present invention;

FIG. 4 is a diagram illustrating pre-wiring analysis and timing feature extraction according to the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.

The invention provides a time sequence prediction method in a physical design layout stage, aiming at the problems that the existing traditional time sequence prediction method can bring additional influence on the performance and the power consumption of a chip, can greatly increase the design period and the cost of the whole chip and has large difference between the predicted performance and the performance after final flow.

As shown in fig. 1 to 4, an embodiment of the present invention provides a timing prediction method for a physical design layout phase, including: step 1, dividing the acquired process library, circuit netlist and layout result data thereof into a training set and a test set, and extracting circuit time sequence characteristics of the training set and circuit time sequence characteristics of the test set respectively based on the training set and the test set; step 2, inputting the circuit time sequence characteristics of the training set and the Sign-Off time sequence results corresponding to the training set into a random forest model for training to obtain a time delay prediction model based on a wire network; step 3, inputting the circuit time sequence characteristics of the test set into a time delay prediction model based on a wire network to perform time delay prediction, and obtaining a wire network Sign-Off time delay prediction result of each circuit in the test set; step 4, performing circuit diagram topology traversal on the wire net Sign-Off time delay prediction results of all circuits in the test set, and calculating the time margin of the output pin of each wire net of each circuit; and 5, distinguishing a critical path from a non-critical path according to the calculated time margin to obtain a critical path prediction result of each circuit in the test set.

In the time sequence prediction method for the physical design layout stage according to the embodiment of the present invention, the Gate Delay model and the Wire Delay model are separately predicted based on the time Delay prediction model difference of the Wire network, specifically as follows: number and complexity of models: if the Gate Delay and the Wire Delay are predicted separately, the method generally needs to additionally predict or calculate the Wire Slew, Output Load and the like, 2-4 models need to be trained, and the number and the complexity of the models are increased. Prediction time and error: on one path, the Gate Delay and the Wire Delay are alternated in the first-level stage, if the Gate Delay and the Wire Delay are predicted separately, the accuracy of the input characteristics of the Gate Delay and the Wire Delay prediction is mutually dependent in the first-level stage, and therefore the prediction time and the accumulated error are increased. The time delay prediction model based on the net only needs to train 1 model, so that the model is simplified, the time sequence characteristics of all nets can be extracted at one time, one-level information transmission on a path is not needed, and the accumulated error is eliminated while the complexity of the model is reduced.

Wherein, the step 1 specifically comprises: step 11, dividing a given process library, a given circuit netlist and layout result data thereof into a training set and a test set; step 12, performing pre-wiring analysis on the data in the training set and the test set respectively to obtain a training set pre-wiring analysis result and a test set pre-wiring analysis result; step 13, obtaining an RC network generated based on training set pre-wiring analysis according to the training set pre-wiring analysis result, and obtaining an RC network generated based on test set pre-wiring analysis according to the test set pre-wiring analysis result; step 14, extracting circuit timing sequence characteristics by combining the circuit netlist data and the layout result data thereof in the training set and the process library data according to the pre-wiring analysis result of the training set to obtain the circuit timing sequence characteristics of the training set; and according to the test set pre-wiring analysis result, circuit timing sequence feature extraction is carried out by combining the circuit netlist data and the layout result data thereof as well as the process library data in the test set to obtain the circuit timing sequence feature of the test set.

Wherein the step 12 specifically includes: step 121, performing pre-wiring analysis on each circuit in the training set, including the following steps: step 1211, obtaining position information of pins in each net of each circuit in the training set, dividing the multi-terminal net into a plurality of two-terminal connection relations by adopting a minimum Steiner tree algorithm according to the position information of the pins in each net of each circuit in the training set, and performing L-type wiring on each two-terminal connection relation to obtain a pre-wiring analysis result of the training set.

Wherein the step 12 specifically includes: step 122, performing pre-wiring analysis on each circuit in the test set, including the following steps: step 1221, obtaining position information of pins in each net of each circuit in the test set, dividing the multi-terminal net into a plurality of two-terminal connection relations by adopting a minimum Steiner tree algorithm according to the position information of the pins in each net of each circuit in the test set, and performing L-type wiring on each two-terminal connection relation to obtain a pre-wiring analysis result of the test set.

Wherein, the step 14 specifically comprises: the circuit timing characteristics of the training set and the circuit timing characteristics of the test set both include: drive strength, number of fan-outs, output load, gate transition tilt in nonlinear model, gate delay in nonlinear model, distance, Elmore delay, ContextElmore delay, and D2M delay.

In the method for predicting the timing sequence of the physical design layout stage according to the embodiment of the present invention, the pre-wiring analysis first divides the input Multi-terminal Net (Multi-Pin Net) into a plurality of two-end connection relationships by using a Minimum Steiner Tree (MST) according to the position information of the pins in the Net, and performs L-type wiring on each two-end connection relationship to obtain a pre-wiring analysis result. Net n, shown in FIG. 4₃Is a multi-end wire net to drive the door c₁With two fan-out pins, d and f, first for n₃Performing Minimum Steiner Tree (MST)Dividing, using red Stanner point as boundary to obtain 3 connection relations (r to Stanner point, Stanner point to d, Stanner point to f), and connecting each two ends by L-shaped wiring to obtain wire network n₃The result of pre-wiring.

After pre-wiring, one input pin of each driver gate is merged with one fan-out pin thereof to be regarded as a net, and table 1 shows the characteristics required for each net sample in the net-based delay prediction model.

TABLE 1 summary table of time series feature extraction

Based on the pre-wiring analysis result, the following timing characteristics can be obtained by combining the circuit netlist, the layout result information thereof and the process library information:

driving strength: the driving strength of the driving door is directly obtained from a Lib file of a process library through a corresponding component lookup table;

the number of fan-outs is as follows: the fan-out number of the driving gate, namely the number of the receiving pins, is provided by the circuit netlist;

and (3) output load: the load of the output pin of the driving gate, namely the wiring capacitors to all fan-outs, can be obtained by calculation according to an RC Network (Network);

and (3) NLDM Gate Slew, namely calculating the obtained Gate Slew according to an NLDM model. The method can be obtained by adopting Non-Linear Delay Model (NLDM) calculation according to a Lib file lookup table in a process library and by the Slew values of an output load and an input pin;

NLDM Gate Delay is the time Delay of the driving Gate calculated according to the NLDM model. The method can be obtained by adopting NLDM calculation according to a Lib file lookup table in a process library through an output load and a Slew value of an input pin;

distance: the Manhattan distance from the wire mesh driving pin to the receiving pin is calculated by the input layout coordinate;

elmore time delay: obtaining the Elmore time delay from the wire mesh driving pin to the current receiving pin, obtaining an RC Network according to a process library and a pre-wiring result, and calculating by using an Elmore model formula;

context Elmore delay: except the current receiving pin, the sum of Elmore time delays of other receiving pins of the multi-terminal wire network at the same input. For example, in fig. 4, the Context Elmore delay of the pin d is the Elmore delay from r to f;

D2M time delay: D2M time delay from the drive pin to the accept pin. According to RC Network, a formula is calculated through a D2M model.

Taking the net driving the gate input b to the output pin d as an example, the corresponding eigenvalue extraction information is given in fig. 4.

Wherein, the step 2 specifically comprises: in a time delay prediction model based on a wire network, gate time delay and line time delay are combined together for prediction, the gate time delay of a driving gate and the line time delay of a line of a certain fan-out gate are combined from one input of the driving gate to a corresponding fan-out receiving end after the gate time delay of the driving gate and the line time delay of the line of the fan-out gate, and the two time delays are combined to be called the wire network time delay, and the time delay prediction model based on the wire network is used for predicting the wire network time delay; in a delay prediction model based on nets, the output pin nodes of gates are removed in a directed acyclic graph, and a net is combined from one input pin of a gate to one fanout input pin of the gate into an edge of the directed acyclic graph, and the edge weight comprises the gate delay from the input pin to the output pin in a driver and the line delay from the drive output pin to the fanout input pin.

Wherein, the step 2 specifically comprises: in the time delay prediction model based on the wire network, the gate time delay has 4 different values, which correspond to the following four conditions: the signal of the gate input pin is a rising edge, and the signal of the gate output pin is a falling edge; the signal of the gate input pin is a rising edge, and the signal of the gate output pin is a rising edge; the signal of the gate input pin is a falling edge, and the signal of the gate output pin is a rising edge; the signal at the gate input pin is a falling edge, and the signal at the gate output pin is a falling edge.

In the time sequence prediction method of the physical design layout stage according to the embodiment of the present invention, as shown in fig. 4 and fig. 3 (a), a path 1 is from an output terminal q of an FF to an input terminal e of a next stage FF, and the entire Delay of the path 1 is alternately summed by a Gate Delay and a Wire Delay; in fig. 3 (b), the Delay from a to u is Gate Delay, and the Delay from u to c is Wire Delay, where a and u are the input and output pins of the driving Gate, respectively, and the fanout receiving pin of the driving Gate is c, and the Gate Delay of the driving Gate and the link Delay to a certain fanout are combined to be called a Net Delay. The net-based delay prediction model is a model that predicts net delay.

In the time delay prediction model based on nets, the output pin nodes of the gates are removed in the DAG, and a net is merged from one input pin of a gate to one fan-out input pin of the gate into a DAG edge, where the q-edge weight includes the gate time delay from the input pin to the output pin in the driver and the line time delay from the output pin to the fan-out input pin connection. Fig. 3 (a) shows a circuit netlist under a delay prediction model based on a net, and fig. 3 (b) shows a corresponding example of a directed acyclic graph, where the delay prediction model based on a net is a model for predicting the delay of a net, and the delay of each edge.

Wherein, the step 2 further comprises: the signal jump of the input pin of the line delay is consistent with the signal jump of the output pin, when the combination driving gate and the fan-out connecting line of the combination driving gate are used as a line network, the time delay of one line network considers the four conditions, one line network corresponds to 4 samples, the time delay under different conditions is respectively predicted, and the time sequence characteristics and the Sign-Off time delay under different conditions are different, so the characteristics and the time delay corresponding to different samples are different.

In the time sequence prediction method in the physical design layout stage according to the above embodiment of the present invention, based on the time delay prediction model of the wire network, because the jump of the signal, i.e. the waveform jump, in the propagation process of the electrical signal is generally divided into two types: up and down. In a gate circuit, the delay from one input pin to one output pin needs to be considered in different rising and falling conditions, so that the delay from the input pin to the output pin in the gate circuit may have more than one value, that is, the gate delay has multiple conditions. According to the time sequence prediction method of the physical design layout stage, the gate delay has 4 different values at most, and the method corresponds to the following four conditions:

the signal of the gate input pin is a rising edge, and the signal of the gate output pin is a falling edge;

the signal of the gate input pin is a rising edge, and the signal of the gate output pin is a rising edge;

the signal of the gate input pin is a falling edge, and the signal of the gate output pin is a rising edge;

the signal of the gate input pin is a falling edge, and the signal of the gate output pin is a falling edge;

since the signal transition of the input pin and the signal transition of the output pin of the line delay are consistent, when the driving gate and the fan-out connecting line thereof are combined to be used as a line network delay, the four situations need to be considered at most for one line network delay, that is, one line network can correspond to 4 samples at most, and the delay under different situations is respectively predicted. Because the timing characteristic and Sign-Off delay are different under different conditions, the characteristic (Feature) and delay (Ground Truth) corresponding to different samples are different even for the same net. Taking fig. 3 as an example, the characteristic and Sign-Off delay (Ground route) corresponding to the timing arc of b- > d can be used as a data sample when the input signal is a rising delay and the output signal is a falling edge; when the input signal is falling and the output signal is rising, the corresponding signature and Sign-Off delay (Ground Truth) are used as another data sample. Since the drive gate is an inverter, there are 2 cases in total above, and no 4 cases, namely Net of b- > d, can take 2 samples.

Wherein, the step 4 specifically comprises: and traversing the topology of the circuit diagram according to the prediction result of the line net Sign-Off time delay of each circuit in the test set, calculating the arrival time delay of the output pin of each line net of each circuit in the test set, and further obtaining the time margin of the output pin of each line net of each circuit in the test set.

Wherein, the step 5 specifically comprises: distinguishing a critical path and a non-critical path of each circuit based on the time margin of the output pin of each net of each circuit in the test set, sequentially judging whether the time margin of the output pin of each net of each circuit in the test set is negative, and when the time margin of the output pin of the current net is negative, a circuit corresponding to the current net generates time sequence violation, and the current net is the critical path; and when the time margin of the output pin of the current net is positive, the time sequence of the circuit corresponding to the current net is normal, the current net is a non-critical path, and the critical path prediction result of each circuit in the test set is obtained.

In the method for predicting the timing of the physical design layout phase according to the above embodiment of the present invention, the method for predicting the timing of the physical design layout phase is implemented in C + +17 and Pytorch 1.8.0, and is evaluated on a PC with Intel Core i7 (@ 3.00 GHz) and 16 GB DDR 4:

TABLE 2 Circuit information

All training samples are provided together to the Net-Based model for training. The timing sequence prediction method of the physical design layout stage is carried out on an ITC'99 circuit, and an advanced 28nm process library is adopted. The information corresponding to each circuit design in the ITC'99 circuit use case is shown in table 2. Wherein the data in the training set does not contain the circuit designs from b17 and b22, and the data in the test set b17 and b22 are used for cross validation of the model, namely, the predicted effect of other unknown circuit designs under the same process of our model is verified. The timing group Truth of the experiment is derived from the PrimeTime tool, hereinafter referred to as Sign-Off results.

Table 3 shows the net delay prediction effect in the net-based delay prediction model. Wherein Mean and Max are respectively the average error and the maximum error of the net delay prediction effect and the group Truth delay given by Sign-Off, and ps is taken as a unit. For comparison, the document is reproduced: the DAC' 19 feature extraction method proposed in Erick C Barboza, Nishchal Shukla, Yiran Chen, et al, Machine Learning-Based Pre-Routing differentiation with Reduced Pessism [ C ]// Proceedings of the 56th ACM/IEEE De-sign Automation Conference, 2019(106): 1-6. It can be seen that, under the same model, the time delay correlation of the net time delay prediction result of the time sequence prediction method in the physical design layout stage on the test set can be as high as 0.99, which proves the effectiveness of the time sequence feature extraction of the time sequence prediction method in the physical design layout stage.

TABLE 3 prediction of net delay

And after the prediction result of the time delay of the line network, solving the arrival time delay of each line network output pin by using topological sorting so as to obtain the time margin. When the time margin of the register or the output port is negative, the circuit is judged to be a critical path due to the fact that the timing violation occurs.

TABLE 4 time margin prediction results

The correlation between the time margin of the register or the output port and the Sign-Off report time margin Truth group is calculated by using the predicted time delay of each line network. It can be seen that the timing margin dependence of the timing prediction method of the physical design layout phase is as high as 0.98, which is much higher than the method proposed by DAC' 19.

The purpose of static timing analysis is mainly to check timing violations, namely to pre-judge a critical path with a negative Slack value and provide a basis for subsequent timing evaluation and optimization.

Table 5 shows the effect of distinguishing non-critical paths from critical paths based on the results of the delay prediction. Wherein, True Positive Ratio (TPR) represents the Ratio of the actual critical path to be predicted as the critical path, and the closer the value is to 1, the better the prediction effect is; the True Negative Ratio (TNR) represents the proportion of the actual non-critical path that is predicted as a non-critical path, and the more this value approaches 1, the better the effect.

From table 5, taken together, the sum of the TPR and TNR indicators of the timing prediction method of the physical design layout phase is higher than the DAC' 19 method. In order to predict all the critical paths as much as possible, linear correction processing is carried out on the predicted Slack, and pessimism is increased. After correction, the TPR predicted by the timing prediction method in the physical design layout stage is almost close to 1. After correction, the TNR result of the timing prediction method for the physical design layout phase is reduced due to the added pessimism, but still about 30% higher than the DAC' 19 method.

TABLE 5 Critical Path prediction results

The time sequence prediction method of the physical design layout stage in the embodiment of the invention does not bring additional influence on the performance and power consumption of the chip, reduces the design period and cost of the whole chip, has small difference between the predicted performance and the performance after final tape-out, improves the accuracy of time sequence prediction, reduces design iteration, and eliminates the accumulated error while reducing the complexity of the model.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for predicting the time sequence of a physical design layout stage is characterized by comprising the following steps:

2. The method of claim 1, wherein the step 1 specifically comprises:

3. The method of claim 2, wherein the step 12 specifically comprises:

4. The method of claim 3, wherein the step 12 specifically comprises:

5. The method of claim 4, wherein the step 14 specifically comprises:

6. The method of claim 5, wherein the step 2 specifically comprises:

7. The method of claim 6, wherein the step 2 specifically comprises:

8. The method of claim 7, wherein the step 2 further comprises:

9. The method of claim 8, wherein the step 4 specifically comprises:

10. The method of claim 9, wherein the step 5 specifically comprises: