CN1140982C - Digital constant-ampletude modulator based on frequency modualtion mode - Google Patents

Abstract

The present invention relates to a single-channel modulator which comprises a memory, an access loop, a memory reducing loop and a digital-to-analog converter, wherein the memory is provided with input for receiving a plurality of address signals and output to supplying a digital output signal; the access loop is coupled with the memory to supply a group of address signals; the memory reducing loop is coupled with the access loop to receive an output signal of the access loop so as to respond and supply the address signals to the memory, and the access loop is coupled with the memory to receive a digit output signal and supply an output signal on the basis of the digital output signal; the digital-to-analog converter is coupled with the memory reducing loop to convert the output of the memory reducing loop into an analog value. The present invention can receive input data and generate a modulation signal s(t).

Description

Digital constant-ampletude modulator in the frequency modulating mode

The present invention relates to a kind of modulator, specifically, relate to a kind of modulator that utilizes internal memory reduction loop.

Radio telephone (wireless telephone generally is also referred to as cordless telephone) is day by day popularized in family and office.Because radio telephone provides and allows the user not be subject to telephone wire and permitted user to move and length and other restriction of the telephone wire of needn't worrying everywhere, like this, radio telephone provides convenience and the elasticity many above telephone.The basic module of one typical wireless telephone has: (1) one base, be connected to a telephone jack, and it provides and being connected an of central office; And (2) one telephone receivers, it is for Portable and can be separated by remote with this base.Voice data communication between this base and this receiver.

In wireless telephonic design and execution, two important consideration points are arranged.The first, base is wanted to make institute become system that the good and accurate voice data of one quality of communication between this base and receiver is provided with the assembly that receiver is utilized.The second, when satisfying first requirement, to reduce the cost of this assembly as far as possible.

One reflector is that the necessary significant components of voice data is transmitted in this base and receiver enhancement between the two.It promptly is a modulator that one significant components is arranged in this reflector, and it is tuned as voice data the modulating signal of one suitable transmission.Existing modulator complexity is difficult to make, and quite expensive.Because modulator uses (also promptly being supplied in base position and the receiver) twice in each radio telephone system, any saving cost and simplification in the design of modulator loop all are multiplied by twice.

The reflector that the existing radio words are utilized uses a quadrature in phase modulator, and this is known by those skilled in the art person.No. the 5022054th, United States Patent (USP) (Wang) for example, title is " having the interval digital GMSK modulator of handling (Digital GMSK Modulator with Non-integer BitInterval Handling) of non-integer numerical digit "; And No. 5121412 (Borth), title is disclosed in " full digital quadrature modulator (All-Digital Quadrature Modulator) ".

Fig. 1 draws the general function calcspar of an existing modulator.More particularly, Fig. 1 is a calcspar of describing an existing quadrature in phase modulator 2.Quadrature in phase modulator 2 comprises logical circuit 6, it receive a clock signal 8 and with the transmission data 7.6 pairs one first channels of logical circuit and a second channel provide address signal.First channel comprises one first read-only memory (ROM) 3A, one first digital to analog converter (DAC) 4A, one first low pass filter (LPF) 5A, and first a frequency mixer 9A with series coupled.This second channel is parallel with this first channel, and it comprises one second read-only memory 3B, one second digital to analog converter 4B, one second low pass filter 5B, and second a frequency mixer 9B with series coupled.This first channel is denoted as the I channel, and this second channel is denoted as the Q channel.The output of frequency mixer 9A and 9B adds and produces a modulating signal s (t) together.This two channel is correctness and the quality that will transmit voice signal in order to increase.

Yet this existing modulator has following shortcoming.At first, use two channels can repeat several loop sets parts (for example two read-only memory 3A and 3B, two digital to analog converter 4A and 4B, two low pass filter 5A and 5B, two frequency mixer 9A and 9B), thus increase the cost of modulator and produce the whole cost of this reflector.In addition, owing to utilize read-only memory 3A and 3B to generate digital waveform s (t), read-only memory 3A and 3B comprise the table of comparisons for sine and cosine carrier signal, sine and cosine phase data-signal, multiplier and adder use, thereby make the size of read-only memory 3A and 3B become excessive.Because read-only memory 3A and 3B are typically the flush type read-only memory, it is important that the consideration on the space more seems.And, the production of the complex digital analogue converter that this existing modulator is utilized and apply mechanically also quite expensive.

A purpose of the present invention provides a kind of digital modulator that utilizes single channel.

Another object of the present invention provides a kind of the utilization corresponding to the symmetry of the frequency change track of transmission means and reduces the modulator of the size of used internal memory.

Another purpose of the present invention provides a kind of digital modulator, and it can utilize internal memory reduction loop reduction to finish the used component size of this modulator.

A further object of the present invention provides a kind of modulator with reduced-size internal memory, thereby makes the size of internal memory and width all have reduction that cost and space are saved.

Another purpose of the present invention provides a kind of modulator, it has less shaping filter output level (1evel), make a digital to analog converter can more existing modulator in used digital to analog converter have less bits and corresponding less level, carry out thereby more have an economic benefit and be easy to.

For achieving the above object, modulator of the present invention, it is characterized in comprising: an internal memory in order to store information, have an input in described in order to receiving several address signals, and an output is that the basis provides a digital output signal with institute's receiver address signal; One access loop with the coupling of described internal memory, in order to described internal memory being provided a group address signal, and provides output signal to internal memory reduction loop; One internal memory reduction loop, be coupled with described access loop, in order to receive the output signal in described access loop, described output signal responds described internal memory to provide address signal to described internal memory, and described internal memory reduction loop and the described digital output signal of described internal memory coupling reception, and be that the basis provides an output signal with described digital output signal; And a digital to analog converter, with described internal memory reduction loop coupling, be converted to an analogue value in order to output with described internal memory reduction loop, this analogue value for a postfilter to filter the frequency change trajectory signal.

Modulator of the present invention has a digit pulse shaping filter, and it carries out a convolution operation between an input data signal and a shaping pulse equation g (t).This pulse shaping filter comprises a counter, an offset buffer, the non-repetition values of coding of a memory storage one shaping pulse reaction.There is the input of a receiver address signal in being somebody's turn to do.This counter provides first a group address signal of delivering to this internal memory, and this offset buffer provides an output.One internal memory reduction loop and this offset buffer are coupled receiving an input data signal, and are that the basis provides one second group address signal to this internal memory with this input data signal.Export after the modification of the output of this internal memory or this internal memory is provided in this internal memory reduction loop also selectivity.One digital to analog converter is a corresponding digital value with this internal memory reduction loop coupling with the output transform with this internal memory reduction loop.One filter and this digital to analog converter are coupled with the output of filtering this digital to analog converter and frequency change track b (t) are provided.Gained signal b (t) produces a modulating signal that is suitable for transmitting by a voltage controlled oscillator (VCO) utilization.

Be clearer understanding purpose of the present invention, characteristics and advantage, below in conjunction with accompanying drawing to of the present invention preferable

Embodiment is elaborated.

Fig. 1 is a calcspar of drawing existing quadrature in phase modulator;

Fig. 2 is a calcspar according to the single channel modulator of a preferred embodiment of the present invention configuration;

Fig. 3 A and Fig. 3 B draw the frequency change trace graphics of the gauss low frequency filter (GLPF) with 68 output levels and 30 output levels respectively;

Fig. 3 C and Fig. 3 D draw the figure of the gauss low frequency filter output level of Fig. 3 A and Fig. 3 B respectively;

Fig. 4 is the calcspar according to Fig. 2 single channel modulator of a preferred embodiment of the present invention configuration;

Fig. 5 is the single channel modulator shown in Figure 4 according to a preferred embodiment of the present invention configuration;

Fig. 6 is the internal memory reduction loop diagram of single channel modulator shown in Figure 5;

Fig. 7 is the circuit diagram that the internal memory speed of Fig. 6 subtracts the non-linear, digital analogue converter in the loop;

Fig. 8 A is the single channel modulator of the one second preferred embodiment configuration according to the present invention;

Fig. 8 B is the internal memory reduction loop of the single channel modulator shown in Fig. 8 A;

Fig. 9 is the unit impulse response curve chart of the gauss low frequency filter drawing in a preferred embodiment of the present invention to be adopted;

Figure 10 be draw in a preferred embodiment of the present invention to be adopted eight kinds may the frequency change tracks and the schematic diagram of corresponding transmission data pattern;

Figure 11 is the curve charts of all frequency locus intussusceptions of Figure 10 on a single figure;

Figure 12 is the tables of data that can be stored in the coding frequency locus in Fig. 8 A internal memory.

Disclose a kind of single channel modulator at this.Can further understand the present invention by explanation to following preferred embodiment.Yet these preferred embodiments are not to be used to limit the present invention.

The modulation plan

The outline of one tentering modulation plan is defined by following formula: $s\left(t\right)=\sqrt{\frac{2E}{T}}\cos [2\mathrm{\π}{f}_{0}t+\mathrm{\θ}(t,a)]$ Wherein s (t) represents modulating signal, and transmission information is homophase, $\mathrm{\θ}(t,a)=2\mathrm{\π}{f}_d\underset{i=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{a}_{i}q(t-\mathrm{iT}),$ Wherein $q\left(t\right)=\underset{-{\mathrm{\φ}}^{\mathrm{\τ}}}{\overset{1}{\∫}}g\left(\mathrm{\τ}\right)\mathrm{d\τ}$ In above-mentioned relation, J _dBe a phase deviation constant, and a _iBe non-return-to-zero (NRZ) relevant with M (M-ary) input data signal.G (t) represents the gauss low frequency filter pulse shaping signals.For instance, g (t) must (0≤t≤LT), wherein L be a pulse length, and E is the energy of signal s (t), and T is a signal period divided by a limited interval for a level and smooth pulse shaping signals.The present invention utilizes above fundamental relation.

Modulator of the present invention provides following feature: (1) one single channel is implemented, and saves the dup loop assembly; (2) three transmission modes; (3) symmetry identifications corresponding to the frequency locus of this transmission mode, its permission is used for the used memory size of a kind of more existing modulator and has reduced-size internal memory; (4) a kind of internal memory reduction loop, it utilizes aforementioned symmetry and access to this reduction internal memory is provided; And (5) one reductions in shaping filter output level quantity, its permission is used for the non-linear, digital analogue converter that the used digital to analog converter of a kind of more existing modulator has less bits.

Single channel is implemented

At first, modulator of the present invention is designed to operate in a single channel.By using single channel to make the unlikely repetition of loop assembly, so as to the saving of space and cost is provided electric power.

Fig. 2 is a calcspar according to the single channel modulator 20 of one embodiment of the invention configuration.Whole target at first for the autobiography transmission of data push away a frequency change track b (t), it describes in detail hereinafter, serve as basic generation modulating signal s (t) with b (t) then.Frequency change track b (t) is also referred to as pulse shaping filter output in this article.Single channel modulator 20 comprises a pulse shaping filter (PSF) 24, and it can be a gauss low frequency filter (GLPF).Pulse shaping filter 24 receives a clock signal and transmission data (a _i).Pulse shaping filter 24 is input as the basis with this and produces digital version pulse shaping filter output b (t).Transmission data (a _i) look its purposes data that provide by a personal computer (PC) or the sampling voice data that is provided by a loud speaker can be provided.Pulse shaping filter 24 must be implemented with simulated assembly or digital assembly.Use a numeral to implement in preferred embodiment, it describes in detail hereinafter.

Single channel modulator 20 further comprises a digital to analog converter 28 and pulse shaping filter 24 couplings, a simulation postfilter 60 and digital to analog converter 28 couplings and a voltage controlled oscillator (VCO) 32 and 60 couplings of simulation postfilter.The numeral output of digital to analog converter 28 received pulse shaping filters 24 is a corresponding analog signal with this output transform, and it is commonly referred to as pulse shaping filter output b (t).Filter 60 filters this analog signal and provides b (t) to voltage controlled oscillator 32.Voltage controlled oscillator 32 produces a modulating signal s (t) based on this pulse shaping filter output b (t) then.Because voltage controlled oscillator and be implemented as prior art is seldom done explanation to voltage controlled oscillator herein.Modulating signal s (t) one is suitable for high frequency signals transmitted.

The output of voltage controlled oscillator 32, modulating signal s (t); And the signal of input voltage controlled oscillator 32, frequency change trajectory signal b (t); Both are able to following formula and represent: $s\left(t\right)=\sqrt{\frac{2E}{T}}\cos [2\mathrm{\π}{f}_{0}t+2\mathrm{\π}{f}_d\underset{-\∞}{\overset{i}{\∫}}b\left(\mathrm{\τ}\right)\mathrm{d\τ}]$ $b\left(t\right)=\underset{-\∞}{\overset{\∞}{\mathrm{\Σ}}}{a}_{i}g(t-\mathrm{iT})$

As discussed previously, the present invention at first the autobiography transmission of data push away frequency change track b (t), serve as that the basis produces modulating signal s (t) with frequency change track b (t) then.Voltage controlled oscillator 32 produces continuous phase modulation (CPM) signal s (t) based on this frequency change trajectory signal b (t).Frequency change track b (t) is by this input data signal (a _i) produce with shaping pulse filter signal g (t) convolution.

The present invention can produce b (t) by the accumulation waveform that calculates during a sigtnal interval corresponding to the pulse shaping filter response of the input data signal that links up.For the various combination of the input data signal that links up, can obtain the difference accumulation waveform of the summation of different pulse shaping filter responses.The accumulation waveform that produces during a sigtnal interval is called " frequency change track (frequency variation trajectories) ", because this track changes the frequency of voltage controlled oscillator 32.

The symmetry of frequency locus

Fig. 9 one unit impulse response g (t) is to the figure of t/T, the unit impulse response of drawing a gauss low frequency filter among the figure.The level and smooth shaping filter that is applied to a Gaussian Minimum Shift Keying (GMSK) system is called a gauss low frequency filter (GLPF).Filter is defined by following formula the response g (t) of a unit rectangular pulse: $g\left(t\right)=\frac{1}{2}\left\{\mathrm{erf}\right[\sqrt{\frac{2}{\mathrm{<figure-callout\; id="2"\; label="ln"\; filenames="C0111714500161.png,C0111714500191.png"\; state="\{\{state\}\}">ln</figure-callout>}2}}\mathrm{\&pi;}{B}_{b}T(\frac{1}{2}-\frac{t}{T})]-\mathrm{erf}[\sqrt{\frac{2}{\mathrm{<figure-callout\; id="2"\; label="ln"\; filenames="C0111714500161.png,C0111714500191.png"\; state="\{\{state\}\}">ln</figure-callout>}2}}\mathrm{\&pi;}{B}_{b}T(-\frac{1}{2}-\frac{t}{T})\left]\right\}$ And $\mathrm{erf}\left(t\right)=\underset{\mathrm{<figure-callout\; id="0"\; label="t"\; filenames="C0111714500161.png,C0111714500201.png"\; state="\{\{state\}\}">t</figure-callout>}}{\overset{0}{\&Integral;}}\frac{1}{\sqrt{\mathrm{\&pi;}}}{e}^{-{\mathrm{<figure-callout\; id="2"\; label="y"\; filenames="C0111714500161.png,C0111714500191.png"\; state="\{\{state\}\}">y</figure-callout>}}^2}\mathrm{dy}$

B parameter bT system is in order to define the gauss low frequency filter of a particular type.For instance, Fig. 9 draws when BbT equals 0.5 a unit impulse response g (t) to the figure of t/T.This system utilizes an exemplary frequency deviation values (fd) that is chosen as 0.25fb, and wherein fb is a Bit Transmission Rate.Because this unit impulse response extends to about three bit periods, these three bit periods must produce effect to this unit impulse response.In other words, observed b (t) signal is started because of in three input data signals (existing transmission position (a during some bit period _n), a last transmission position (a _N-1), a back one transmission position (a _N+1)).

This existing, last and back transmission of data signals or potential energy flock together and constitute a binary code (a _N-1, a _n, a _N+1), wherein this last transmission position is a most significant bit, and should one transmission position, back be least significant bit.Assemble this transmission position by this mode, can know the true effect seen on arbitrary position (also be last and back produce effect to existing position).This binary code is referred to herein as one " transmission mode numeral (transmitting pattern number) ".This transmission mode numeral is from 0 to 7.In other words, have eight (0-7) different binary codes, this binary code all has three positions.It (also is a that this data-signal can be one one or one zero _i=1 or 0).Each transmission mode numeral has a corresponding frequency change track or impulse response (also being corresponding b (t) signal).

In addition, Figure 10 draw eight may frequency change tracks (also i.e. waveform in time domain), and in figure, should correspondence transmission data digital represent with " Tx Pattern No. ".The unit that is used for X-axis is the sample numeral during a bit period.As shown in figure 11, some track is to the X-axis symmetry.For instance, mode digital is that 0,1,2 and 3 track is respectively 7,6,5 and 4 track symmetry with mode digital.This symmetric identification causes further loop reduction, as hereinafter describing in detail with reference to Fig. 6 and 8B.

With reference to Fig. 3 A, when eight possibility frequency change track covers stack togather, can find that this track is to the X-axis symmetry.Point with a mark " o " expression is the output valve of gauss low frequency filter in the running of 12/T frequency.In above possibility gauss low frequency filter output valve, there are 68 clear and definite numerical value to be plotted among Fig. 3 C and and represent with a mark " o ".With reference to Fig. 3 C, clearly the output valve of gauss low frequency filter distributes and inhomogeneous (also being non-linear).Therefore as hereinafter detailed description, the present invention utilizes one to have the enforcement of the non-linear, digital analogue converter of limited level with the simplification modulator.For 68 varying levels, needing a kind of minimum input width that have is 7 digital to analog converter, presents 128 level because have 7 potential energies.

Have the modulator in internal memory reduction loop

Fig. 4 one draws the calcspar according to Fig. 2 single channel modulator of one embodiment of the invention configuration more in detail.Pulse shaping filter 24 can be implemented by the internal memory 80 that a counter 54, one offset buffers 58 and describe in detail hereinafter.Counter 54 is in order to the g that a high-resolution digital form is provided (t).Counter 54 comprises that one receives the input of a clock signal (CLK), and it is responded to provide at least one address bit to internal memory 80.Offset buffer 58 comprises a receiving input data signal (a _i) input, and one to be the basis with this input data signal provide the parallel output of output signal to internal memory reduction loop 74.This input data signal is displaced to offset buffer 58 with one with the synchronous speed (being known as input data signal speed) of this clock signal.The speed of this clock signal equals the numeral of section (J) divided by time cycle (T), and this clock signal has one to be the frequency (f of this input data signal speed multiple _s).

In this dated counter 54 and offset buffer 58 common formations one memory access loop, internal memory 80 is provided address signal and provides output signal to internal memory reduction loop 74.Each data-signal loads offset buffer 58 according to a synchronous signal rate clock in the operation.Then the output signal of offset buffer 58 as last address bit with addressing one have a corresponding frequency change track (also be among Figure 10 the track of being painted wherein one) or the zone of impulse response.Counter 54 provides the signal of address bit under the conduct to have the some in the zone of this selected pulse shaping response time sample with addressing.

Internal memory 80 comprises the input of several receiver address signals, and several provide the output that is stored in by the information of the address of this address signal appointment.Information access in the internal memory 80 by an address is provided.In a preferred embodiment, internal memory 80 is a read-only memory (ROM).Internal memory 80 stores the information that is beneficial to construction one frequency change track b (t).This information comprises pulse shaping filter 24 difference response to different input data signals during limit signal interval is as 3T.For instance, this information must be painted the numeral performance of eight possibility frequency change tracks for Figure 10.As the internal memory 80 preferable non-repetition values that only store b (t) hereinafter are described in detail in detail with reference to Fig. 6 and 8B.The output of read-only memory 80 supplies and digital to analog converter 44, the numeral of read-only memory 80 is exported be converted to a corresponding analogue value b (t).In preferred embodiment, digital to analog converter 44 comprises 7 and 68 level or 5 and 30 level.This analogue value supplies and b (t) signal of a postfilter 60 with filtration Fig. 2.One internal memory reduction loop 74 places 44 of internal memory 80 and digital to analog converters, and describes in detail with reference to Fig. 6 hereinafter.

The size of internal memory 80

Internal memory 80 is able to 1 and takes advantage of 7 read-only memorys to implement.In this example, sampling rate is 12/T.The sample storage of frequency change track is in an internal memory 80.For instance, 8 tracks are arranged in this embodiment, each track is got 12 samples, each sample is with 7 bit tables existing (also promptly needing 7 positions with identification between 68 gauss low frequency filter output levels).Therefore, the big or small of this internal memory must be 12 (sample/track) * 8 (track) *, 7 (position/samples), and it equals the 96*7 position.

The output width of reduction internal memory 80

In an another kind of embodiment, the output width of internal memory 80 is reduced to 5 from 7.With reference to Fig. 3 C, the inventor finds that when the output valve of this gauss low frequency filter is examined some contiguous numerical value is very approaching.For instance, in 0＜x＜10 and x＞55 o'clock, the y value is identical or very approaching.Therefore, some contiguous numerical value might be merged into one can be by the special value of non-linear, digital analogue converter 44 supports.In this embodiment, level quantity reduces to 30 from 68.Therefore, only need existing this 30 level of 5 bit tables.Fig. 3 D draws gauss low frequency filter output valve after these 30 modifications, and Fig. 3 B draws the intussusception frequency change track corresponding to reduction quantity gauss low frequency filter output valve.Because gauss low frequency filter output level number is reduced to 30 from 68, the width of internal memory 80 derives from 7 and is reduced to 5.Comparison diagram 3A and Fig. 3 B are found to the reduction of output level number and the not obvious waveform that influences the frequency change track.

The size of reduction internal memory 80

With reference to Fig. 3 B, as mentioned before, some frequency change track is to the X-axis symmetry.For instance, group 1 (mode digital 0,1,2,3) is a reverse signal symmetry (also being b=-a) with group 2 (mode digital 7,6,5,4).Therefore, only need store 4 tracks (corresponding to mode digital 0,1,2,3) in the internal memory 80, and sample value can be by 2 complement representation.In 2 complement code form, the most tangible position is a sign bits.In this embodiment, input data signal a _N-1Determine which track group should load in the digital to analog converter 44.Work as a _N-1Equal at 0 o'clock, track group 1 carries out access.Work as a _N-1Equal at 1 o'clock, track group 2 is by obtaining corresponding to the memory content of group 1 and transforming this content (also promptly changing the signal of this content) and access.

Therefore, after the symmetry feature of reduction of using the gauss low frequency filter output level and frequency change track, internal memory 80 must have following size: 12 (sample/track) * 4 (track) *, 5 (position/sample)=48*5 positions.

The frequency of this clock signal is 13.824 hundred outer hertz.Therefore event, counter 54 must be four the interpolation counters (also promptly this counter cycle counts up to state 11 (HLHH) from state 0 (LLLL)) that have a modulus 12 (N=12), to internal memory 80 provide down address bit (b3, b2, b1, b0).Offset buffer 58 must have triphasic triple motion position buffer for one, to internal memory 80 provide address bit (b6, b5, b4).Therefore might all can be stored in the internal memory 80 by the frequency change track in this embodiment.

As mentioned before, g (t) waveform is often to the X-axis symmetry.Therefore, the non-repetition absolute value of the present invention by only stored frequency variation track or impulse response is with the size of reduction internal memory 80 and an internal memory reduction plan is provided, and this plan is described in detail with reference to Fig. 6 and 8B hereinafter.

First framework of Fig. 4 single channel modulator.Fig. 5 is the calcspar of drawing according to first framework of Fig. 4 single channel modulator of one embodiment of the invention.For suitably the digital value of a response being reappeared in a pulse shaping filter, a kind of memory size reduction loop 74 is proposed at this with the non-repetition values of b (t).Memory size reduction loop 74 and offset buffer 58 couplings are with receiving input data signal, and with this input data signal serve as the basis produce for the some of the address signal of internal memory 80.In this embodiment, memory size reduction loop 74 produces and goes up address bit and provide address bit on this to internal memory 80.Following address bit is still provided by counter 54.Assembly with a same tag and digitized representation in Fig. 5 is similar to assembly described in Fig. 4, in this not repeat specification.

In this first framework, non-linear, digital analogue converter 44 comprises a decoder 104 and 74 couplings of internal memory reduction loop.Decoder 104 is from internal memory reduction loop 74 receiving inputted signals (K position), to this input signal decoding, and serves as that the basis produces control signal (L position) with this input signal.Digital to analog converter 44 1 comprises a limited level supply 120 and these decoder 104 couplings.The control signal that limited level supply 120 provides with decoder 104 is the level that the basis produces the non-linear, digital analogue converter.

The enforcement in internal memory reduction loop 74

Fig. 6 draws Fig. 5 internal memory reduction loop according to one embodiment of the invention configuration more in detail.With reference to as described in Figure 11, when may frequency change pattern covers stacking togather for eight, this pattern is to the X-axis symmetry as preamble.Therefore, only there are four to have and to be stored in the internal memory 80 in eight frequency change tracks.More particularly, 48 samples (also being 4 (track) *, 12 (sample/tracks)) are stored in the internal memory 80.Therefore, internal memory 80 is able to 1 and takes advantage of 5 read-only memorys enforcements.Put, internal memory 80 has an output that output signal K[4..0 is provided at this point].

Internal memory reduction loop 74 comprises one first mutual exclusion or (XOR) door 170, one second mutual exclusions or door 180, one multiplexers (MUX) 184, and signal counter-rotating loop 188.First mutual exclusion or door 170 have a back (a of one first input and offset buffer 58 _N+1) coupling, the existing position (a of one second input and offset buffer 58 _n) coupling, and an output provides an address signal (b4) to internal memory 80.Second mutual exclusion or door 180 have the existing position (a of one first input and offset buffer 58 _n) coupling, the last position (a of one second input and offset buffer 58 _N-1) coupling, and an output provides an address (b5) to internal memory 80.

Signal counter-rotating loop 188 and internal memory 80 couplings are to receive output K[4..0], and serve as that the basis produces an output with it, this output has same absolute with input but signal opposite (also be loop 188 its input is multiplied by bear).Multiplexer 184 comprises that one first input receives the output K[4..0 of internal memory 80], and the output in one second input received signal counter-rotating loop 188, and one the 3rd input is from the last position (a of offset buffer 58 _N-1) reception one selection signal (SEL).Be input as the basis with this, multiplexer 184 is exported (also be the output of internal memory 80 be multiplied by bear one) after selecting the output of internal memories 80 or internal memory 80 based on the modification of this selections signal.The output signal Q[4..0 of multiplexer 184] supply and non-linear, digital analogue converter 44.Multiplexer 184 and signal counter-rotating loop 188 must be synthetic by practising in the known integrated circuit of this skill person (IC) design tool.

Therefore, internal memory reduction loop 74 optionally provides the output of (1) internal memory 80 or (2) internal memory 80 last transmission (a with offset buffer 58 to digital to analog converter 44 _N-1) be multiplied by the output of (1) for the basis.Because other assembly is roughly with identical described in the previous Figure 4 and 5 among Fig. 6, same numbers is in order to representing above assembly, and this assembly is seldom done explanation at this.

Fig. 7 draws the non-linear, digital analogue converter 44 of Fig. 6 more in detail.Non-linear, digital analogue converter 44 comprises that a decoder 104 and multiplexer 184 are coupled with received signal Q[4..0], and a limited level supply 120 and decoder 104 couplings.104 pairs of received signal decodings of decoder also provide control signal B[(L-1) ..0].

Limited level supply 120 comprises that several voltages or current supply 284 are to supply voltage or electric current, several switches 288, and a summation loop 290.Each switch 288 and an individual voltages supply 284 couplings also produce an output.Each switch 288 a special control signal that is provided by decoder 104 also is provided and controlled by it.Summation loop 290 and the output of Voltage Supply Device 284 couplings with sum voltage supply 284.The present invention can utilize the L supply to produce digital to analog converter and export required Q level.For instance, 10 supplies (also being L=10) can be in order to produce 30 output levels.This output level must be heterogeneity (also reaching non-linear).

Second framework of Fig. 4 single channel modulator.Fig. 8 A one draws Fig. 4 modulator second framework according to the another kind of embodiment configuration of the present invention one more in detail.This second framework comprises that a counter 54, one offset buffers 58, one internal memories 100 are different with Fig. 5 internal memory 80, internal memory reduction loop 200, one limited level supplies 120, and a postfilter 160.Decoder 104 at this dated Fig. 5 is removed in this embodiment.Therefore, an internal memory 100 is in order to carry out a decoding function.Internal memory 100 comprises the non-repetition values of frequency change track, and also is designed to carry out a decoding operation at memory content.The design that internal memory 100 is carried out a decoding function is described in detail with reference to Figure 12 hereinafter.100 pairs of internal memory reductions of internal memory loop 200 provides L the position, and wherein L is more than or equal to K, referring to Fig. 5.Internal memory reduction loop 200 produces the output with L position to its response and supplies and limited level supply 120.Internal memory reduction loop 200 must utilize loop shown in Fig. 8 B to implement.

The enforcement in internal memory reduction loop 200

Fig. 8 B draws Fig. 8 A internal memory reduction loop 200 according to one embodiment of the invention configuration more in detail.The running in internal memory reduction loop 200 is similar with internal memory reduction loop 74, and its difference is in digital to analog converter 44 and replaces with a limited level supply 120, and internal memory 80 has the L position with one but not decoding internal memory 100 replacements of the output of K position.

Decoding internal memory 100 stores the information that is controlled at limited level supply 120 in frequency change track b (t) structure.This store information is the digital reproduction corresponding to the reduction of frequency change track shown in Fig. 3 D back 30 level.Each level of frequency change track must be reproduced to control the running of limited level supply 120 by the index value of a previous decoding.Put, the waveform of Fig. 3 D is able to a table and reproduces at this point.Figure 12 is the table of drawing corresponding to the frequency locus that must be stored in internal memory 100 transmitted data bits.More particularly, the table of Figure 12 is drawn each of transmitted data bits and corresponding to the relation between the frequency change track of an index value sample time.As shown in figure 12, when index value is thought of as range of waveforms, this index value shows symmetry.Therefore, must use this symmetry makes and only has half index value must be stored in the internal memory 100.In this embodiment, each index value reproduces with the L position.

Internal memory reduction loop 200 comprises one first mutual exclusion or door 270, one second mutual exclusions or door 280, one multiplexers 284, and signal counter-rotating loop 288.First mutual exclusion or door 270 have a back (a of one first input and offset buffer 58 _N+1) coupling, the existing position (a of one second input and offset buffer _n) coupling, and an output provides an address signal (b4) to internal memory 100.Second mutual exclusion or door 280 have the existing position (a of one first input and offset buffer 58 _n) coupling, the last position (a of one second input and offset buffer 58 _N-1) coupling, and an output provides an address (b5) to internal memory 100.

Signal counter-rotating loop 288 and internal memory 100 couplings are to receive output K[(L-1) ..0], and serve as that the basis produces an output with it, this output has same absolute with input but signal opposite (also be loop 288 its input is multiplied by bear).Multiplexer 284 comprises that one first input receives the output K[(L-1 of internal memory 100) ..0], and the output in one second input received signal counter-rotating loop 288, and one the 3rd input is from the last transmission position (a of offset buffer 58 _N-1) reception one selection signal.Be input as the basis with this, the output of multiplexer 284 selection internal memories 100 or signal counter-rotating loop 288 are based on the output (output that also is internal memory 100 is multiplied by negative one) of this selection signal.The output signal Q[(L-1 of multiplexer 284) ..0] supply and limited level supply 120.Multiplexer 284 and signal counter-rotating loop 288 are synthetic by the integrated circuit design tool of prior art.Limited level supply 120 gets as shown in Figure 7 to be implemented.Because other assembly is roughly with identical described in the previous Figure 4 and 5 among Fig. 8 B, same numbers is in order to representing this assembly, and this assembly is seldom done explanation at this.

Reach explanation shown in above accompanying drawing, modulator provided by the present invention has following advantage: (1) memory size reduces half, is reduced to 48 by 96 logins; (2) the internal memory width is reduced to 6 or 5 from 8; And (3) digital to analog converter is reduced to 6 or 5 from 8.Indicate a digital to analog converter at this and may have still less position, and decide on its application, the minimum number of bits of digital to analog converter only is subject to the performance parameter that requires, and can receive amount distortion in for example outer bands of a spectrum or modulating signal and the waveform.All aforementioned advantages provide a modulator that more has an economic benefit.Can consider with the invention process in software hardware, firmware or its combination.

In above specification, with reference to specific embodiment the present invention is illustrated already.Yet clearly also can make under than broad spirit and scope and manyly differently revise or change not breaking away from the present invention.Therefore this specification and accompanying drawing for illustration purposes only, tool is not of the present invention by restriction.Meaning.

Claims (20)

1. modulator is characterized in that it comprises:

One internal memory in order to store information, have an input in described in order to receiving several address signals, and an output is that the basis provides a digital output signal with institute's receiver address signal;

One access loop with the coupling of described internal memory, in order to described internal memory being provided a group address signal, and provides output signal to internal memory reduction loop;

One internal memory reduction loop, be coupled with described access loop, in order to receive the output signal in described access loop, described output signal responds described internal memory to provide address signal to described internal memory, and described internal memory reduction loop and the described digital output signal of described internal memory coupling reception, and be that the basis provides an output signal with described digital output signal; And

One digital to analog converter with described internal memory reduction loop coupling, is converted to an analogue value in order to the output with described internal memory reduction loop, this analogue value for a postfilter to filter the frequency change trajectory signal.

2. modulator as claimed in claim 1 is characterized in that, described digital to analog converter comprises a non-linear, digital analogue converter.

3. modulator as claimed in claim 2 is characterized in that, described non-linear, digital analogue converter comprises:

One decoder, with described internal memory reduction loop coupling with receiving inputted signal, to described input signal decoding, and serve as that the basis produces control signal with described input signal; And

One finite value supply serves as that the basis produces a corresponding analogue value to described non-linear, digital analogue converter with described decoder coupling with described control signal.

4. modulator as claimed in claim 3 is characterized in that, described finite value supply comprises: several Voltage Supply Devices; Several switches, each switch are coupled to produce an output with a Voltage Supply Device respectively; And a summation loop, it and described Voltage Supply Device are coupled with the output of the described Voltage Supply Device of summation.

5. modulator as claimed in claim 3 is characterized in that, described finite value supply comprises: several current supplies; Several switches, each switch are coupled to produce an output with a current supply respectively; And a summation loop, it and described current supply are coupled with the output of the described current supply of summation.

6. modulator as claimed in claim 1 is characterized in that, described internal memory comprises non-repeatability frequency change track.

7. modulator as claimed in claim 1, it is characterized in that, described digital to analog converter comprises a finite value supply, it and described internal memory reduction loop are coupled, in order to receiving inputted signal, and produce a corresponding analogue value, wherein based on this input signal, described internal memory comprises decoding non-repeatability frequency change track, and described internal memory is carried out a decoding function.

8. modulator as claimed in claim 7 is characterized in that, described finite value supply comprises: several Voltage Supply Devices; Several switches, each switch are coupled to produce an output with a Voltage Supply Device respectively; And a summation loop, it and described Voltage Supply Device are coupled with the output of the described Voltage Supply Device of summation.

9. modulator as claimed in claim 7 is characterized in that, described finite value supply comprises: several current supplies; Several switches, each switch are coupled to produce an output with a current supply respectively; And a summation loop, it and described current supply are coupled with the output of the described current supply of summation.

10. modulator as claimed in claim 1 is characterized in that, described memory access loop further comprises:

One counter is with described internal memory coupling, in order to described internal memory is provided a group address signal; And

One offset buffer is with described internal memory reduction loop coupling, in order to described output signal to be provided.

11. modulator as claimed in claim 10 is characterized in that, described internal memory reduction loop further comprises:

One signal counter-rotating loop has an input and described internal memory coupling, in order to described input is multiplied by negative one;

One multiplexer, have one first input and described internal memory coupling, one second input and described signal counter-rotating loop coupling, one the 3rd input and described offset buffer coupling, and an output and the coupling of described digital to analog converter, one of them is exported as this in order to select this first input and this second input according to the 3rd input;

One first mutual exclusion or door are with described offset buffer and internal memory coupling, in order to described internal memory is provided one first address signal; And

One second mutual exclusion or door are with described offset buffer and internal memory coupling, in order to described internal memory is provided one second address signal.

12. modulator as claimed in claim 7 is characterized in that, described internal memory reduction loop further comprises:

One signal counter-rotating loop has an input and described internal memory coupling, in order to described input is multiplied by negative one;

One multiplexer, have one first input and described internal memory coupling, one second input and described signal counter-rotating loop coupling, one the 3rd input and offset buffer coupling, and an output and the coupling of described digital to analog converter, one of them is exported as this in order to select first input and this second input according to the 3rd input;

One first mutual exclusion or door are with described offset buffer and internal memory coupling, in order to described internal memory is provided one first address signal; And

One second mutual exclusion or door are with described offset buffer and internal memory coupling, in order to described internal memory is provided one second address signal.

13. modulator as claimed in claim 1 is characterized in that, further comprises a simulation postfilter and described digital to analog converter coupling, is output as basic modulating signal in order to produce one with this postfilter.

14. modulator as claimed in claim 13 is characterized in that, further comprise a voltage controlled oscillator and described postfilter the coupling, in order to produce one with this postfilter be output as the basis modulating signal.

15. modulator as claimed in claim 1 is characterized in that, described digital to analog converter comprises 7 and 68 output valves.

16. modulator as claimed in claim 1 is characterized in that, described digital to analog converter comprises 5 and 30 output valves.

17. modulator as claimed in claim 10 is characterized in that, described counter is the interpolation counter of a modulus 12.

18. modulator as claimed in claim 10 is characterized in that, described offset buffer was one 3 stages, 3 bit shift buffers.

19. modulator as claimed in claim 1 is characterized in that, saves as 1 in described to take advantage of 7 read-only memorys.

20. modulator as claimed in claim 1 is characterized in that, saves as 1 in described to take advantage of 5 read-only memorys.

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