CN114093996B - Semiconductor light emitting device - Google Patents
Semiconductor light emitting device Download PDFInfo
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- CN114093996B CN114093996B CN202111383845.XA CN202111383845A CN114093996B CN 114093996 B CN114093996 B CN 114093996B CN 202111383845 A CN202111383845 A CN 202111383845A CN 114093996 B CN114093996 B CN 114093996B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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Abstract
The application relates to the field of light emitting diodes, and discloses a semiconductor light emitting device, which comprises a substrate, an epitaxial layer, a first electrode layer, a first insulating layer and a second electrode layer which are sequentially arranged from bottom to top; the first electrode layer comprises at least one first P-type electrode and a second N-type electrode; the second electrode layer comprises at least one second P-type electrode and a second N-type electrode; the first P-type electrode is electrically connected with the second P-type electrode, and the first N-type electrode is electrically connected with the second N-type electrode; at least one concave part for reducing the area of the second electrode layer is arranged on the outer side surface of the second P-type electrode, which is close to the outer edge of the N-type semiconductor layer; the total area of each concave part accounts for 5-20% of the area of the second electrode layer. Under the condition of ensuring normal electrical connection of the first and second P-type electrodes, the application reduces the area of the second electrode layer and improves the reflectivity of the chip by arranging the concave part on the outer side surface of the second P-type electrode adjacent to the outer edge of the N-type semiconductor layer, thereby improving the overall brightness of the chip.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor light emitting device.
Background
A light emitting diode (LED for short) is a commonly used light emitting device, and has advantages of low voltage, low power consumption, small volume, long service life, etc., and is widely used in fields of illumination, display, etc. LEDs are widely used as a new generation light source in the fields of lighting, display, backlight, optical communication, and the like. Flip chips have become increasingly popular in the market as products with higher light efficiency, and have more structures and complex process steps, thus having higher requirements and challenges for reliability.
At present, the design pattern area of the PN-Metal layer of the second electrode layer of the flip LED high-light-efficiency chip is larger, and the area of about 80% of the first insulating layer is covered, as shown in figures 1 to 3, the reflectivity of the second electrode layer is lower than that of a traditional bracket, and the reflectivity of the chip is reduced due to the larger area of the second electrode layer, so that the overall brightness of the chip is affected.
In view of this, the present invention has been made.
Disclosure of Invention
The invention aims to: in order to solve the problems in the prior art, the invention provides a semiconductor light-emitting device, which is characterized in that under the condition of ensuring normal electrical connection of a first P-type electrode and a second P-type electrode, an inner concave part is arranged on the outer side surface of the second P-type electrode, which is close to the outer edge of an N-type semiconductor layer, so that the area of the second electrode layer is reduced, the reflectivity of a chip is improved, and the overall brightness of the chip is improved.
The technical scheme is as follows: the invention provides a semiconductor light-emitting device, which comprises a substrate, an epitaxial layer with PN steps, a first electrode layer, a first insulating layer and a second electrode layer, wherein the substrate, the epitaxial layer with PN steps, the first electrode layer, the first insulating layer and the second electrode layer are sequentially arranged from bottom to top; the first electrode layer comprises at least one first P-type electrode and at least one first N-type electrode; the second electrode layer comprises at least one second P-type electrode and at least one second N-type electrode; the first P-type electrode is electrically connected with the second P-type electrode through a first through hole formed in the first insulating layer, and the first N-type electrode is electrically connected with the second N-type electrode through a second through hole formed in the first insulating layer; the second P-type electrode is provided with an outer side surface which is connected with the upper surface and the lower surface of the second P-type electrode and is close to the outer edge of the N-type semiconductor layer; the outer side surface is provided with at least one concave part for reducing the area of the second electrode layer; the total area of the concave parts accounts for 5-20% of the area of the second electrode layer.
Preferably, the concave portion is disposed between two adjacent first P-type electrodes.
Preferably, the length L1 of the concave portion is smaller than the maximum distance L2 between two first P-type electrodes adjacent thereto. The design is to increase the length of the concave part as much as possible on the premise of not influencing the electrical connection of the first P-type electrode and the second P-type electrode, shrink the area of the second electrode layer and improve the reflectivity of the chip, thereby improving the overall brightness of the chip.
Preferably, the width W of the concave portion is greater than or equal to the diameter d of the first P electrode.
Preferably, if the light emitting element is square as a whole, the outer side surface is a square outer side surface; the outer side surface of at least one side of the square outer side surface is provided with the continuous concave part; or the square outer side surface is provided with continuous concave parts on at least two opposite outer side surfaces; or the four outer side surfaces are provided with the continuous concave parts. The arrangement of the concave part is to remove the second electrode layer between at least one pair of adjacent second P-type electrodes at the edge of the second electrode layer, so as to realize the purpose of shrinking and reducing the area of the second electrode layer, thereby achieving the purposes of improving the reflectivity of the chip and improving the overall brightness of the chip.
Preferably, each of the continuous concave portions is located between every two of the first P-type electrodes. The concave parts are arranged between every two adjacent first P-type electrodes, so that the number of the concave parts can be increased to the greatest extent, the area of the second electrode layer is reduced, the reflectivity of the chip is improved to the greatest extent, and the overall brightness of the chip is improved; theoretically, the more the concave parts are arranged, the larger the strength for reducing the area of the second electrode layer is, and the more obvious the effects of improving the reflectivity of the chip and improving the overall brightness of the chip are; however, in practical application, if the area of the concave portion is too large, that is, the area of the second electrode layer is too much reduced, the electric connection effect of the second P-type electrode and the first P-type electrode is affected, and if the area of the concave portion is smaller, the area reduction of the second electrode layer is not obvious, the reflectivity of the chip is improved, and the effect of improving the overall brightness of the chip is not obvious, so that the area of the concave portion is controlled to be 5-15% of the area of the first insulating layer, the electric connection of the second P-type electrode and the first P-type electrode is ensured, the effect of reducing the area of the second electrode layer is achieved, and the purposes of improving the reflectivity of the chip and the overall brightness of the chip are achieved.
Further, the semiconductor light emitting device further includes a pad electrode layer on the second electrode layer, the pad electrode layer including a P pad electrode electrically connected to the second P-type electrode and an N pad electrode electrically connected to the second N-type electrode.
Further, the semiconductor light emitting device further includes a second insulating layer between the second electrode layer and the pad electrode layer to insulate the second P-type electrode from the second N-type electrode; the P pad electrode is electrically connected with the second P type electrode through a third through hole formed in the second insulating layer, and the N pad electrode is electrically connected with the second N type electrode through a fourth through hole formed in the second insulating layer.
Further, a support layer and a third insulation layer are further provided between the second insulation layer and the pad electrode layer, the support layer is located between the second insulation layer and the third insulation layer, and the third insulation layer is located between the support layer and the pad electrode layer. In the conventional light emitting device structure, as shown in fig. 1, the second P-type electrode extends below the N-pad electrode, and is separated from the second P-type electrode by a second insulating layer, so as to form a region shown by a dotted line box. When the second insulating layer is broken or cracked due to some reasons, the second P-type electrode and the N pad electrode are possibly communicated, so that electric leakage occurs, and the reliability of the existing light-emitting element in use is reduced; the application has the advantages that the supporting layer which is not connected with the second electrode layer and the bonding pad electrode and the third insulating layer which is isolated with the bonding pad electrode are added, so that the insulation effect of isolating the second electrode and the third electrode is realized, the electric leakage phenomenon caused by the breakage of the second insulating layer is avoided, and the reliability of the luminous element is improved. The support layer is preferably a metal layer or a metal oxide layer or a DBR reflection layer, and the metal layer comprises a metal monolayer of Cr, ni, ti, pt and Au or a composite metal layer formed by a plurality of metal monolayers.
Further, the semiconductor light emitting device further comprises a current blocking layer and a current expansion layer positioned between the epitaxial layer and the first electrode layer, and the current expansion layer is positioned on the current blocking layer.
The beneficial effects are that: under the condition of ensuring normal electrical connection of the first P-type electrode and the second P-type electrode, the application realizes obviously reducing the area of the second electrode layer, improving the reflectivity of the chip and improving the overall brightness of the chip by arranging the concave parts on the outer side surface of the second P-type electrode adjacent to the outer edge of the N-type semiconductor layer and limiting the sum of the areas of the concave parts to be 5-20% of the area of the second electrode layer.
Drawings
FIG. 1 is a schematic plan view of a flip-chip light emitting device according to the prior art;
FIG. 2 is a schematic diagram of a flip-chip light emitting device according to the prior art;
FIG. 3 is a mask pattern plan view of a second electrode layer according to the prior art;
Fig. 4 is a schematic plan view of a light-emitting element in embodiment mode 1;
fig. 5 is a schematic structural view of a light-emitting element in embodiment mode 1;
fig. 6 is a mask pattern plan view of the second electrode layer in embodiment 1;
fig. 7 is a schematic structural view of a light-emitting element in embodiment mode 1;
fig. 8 is a schematic plan view of a light-emitting element in embodiment mode 2;
fig. 9 is a schematic structural view of a light-emitting element in embodiment mode 2;
Fig. 10 is a mask pattern plan view of the second electrode layer in embodiment 3;
Reference numerals:
| 100-a substrate; | a 210-N type semiconductor layer; | 211-PN steps; |
| 220-a multiple quantum well active layer; | 230-P-type semiconductor layer; | 300-a current blocking layer; |
| 400-a current spreading layer; | 510-a first P-type electrode; | 511-a first via; |
| 520-a first N-type electrode; | 521-second through holes; | 600-a first insulating layer; |
| 710-a second P-type electrode; | 720-a second N-type electrode; | 800-a second insulating layer; |
| 900-a support layer; | 1000-a third insulating layer; | 1100-a third via; |
| 1200-fourth through holes; | 1310-P pad electrodes; | 1320-N pad electrodes; |
| 1410-an inner recess; | 711-outer side. |
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
Embodiment 1:
As shown in fig. 4 and 5, the light emitting element provided by the embodiment of the present invention includes a substrate 100, an epitaxial layer, a current blocking layer 300, a current spreading layer 400, a first electrode layer, a first insulating layer 600, a second electrode layer, a second insulating layer 800, and a pad electrode layer sequentially disposed from bottom to top; the first electrode layer includes at least one first P-type electrode 510 and at least one first N-type electrode 520; the second electrode layer includes at least one second P-type electrode 710 and at least one second N-type electrode 720; the pad electrode layer includes at least one P-type pad 1310 and at least one N-type pad 1320. The second P-type electrode 710 has an outer side 711 connected to the upper and lower surfaces thereof and adjacent to the outer edge of the N-type semiconductor layer 210.
As shown in fig. 6, in the present embodiment, the light emitting element is square overall, and the outer side 711 of the second P-type electrode 710 is square outer side; in order to reduce the area of the second electrode layer with lower reflectivity, to increase the reflectivity of the chip and thus the overall brightness of the chip, a pair of opposite outer sides 711 of the second P-type electrode 710 have continuous concave portions 1410; each continuous concave portion 1410 is located between every two first P-type electrodes 510. That is, the concave portions 1410 are formed by removing the second electrode layer between two adjacent second P-type electrodes 710 on the outer side 711 of the second P-type electrode 710, and the sum of the areas of the concave portions 1410 is 7.7% of the area of the second electrode layer.
In practical applications, a square concave portion 1410 may be formed, where the length L1 of the concave portion 1410 is smaller than the maximum distance L2 between two adjacent first P-type electrodes 510; the width W of the recess 1410 is greater than or equal to the diameter d of the first P-type electrode 510 (see fig. 7). The design is to increase the length of the concave 1410 as much as possible without affecting the electrical connection between the first P-type electrode 510 and the second P-type electrode 710, shrink the area of the second electrode layer, and increase the reflectivity of the chip, thereby increasing the overall brightness of the chip.
Other structures of the light-emitting element in this embodiment mode are provided as a conventional light-emitting element. The method comprises the following steps:
The epitaxial layer is disposed on the surface of the substrate 100, and includes an N-type semiconductor layer 210, a light emitting layer 220, and a P-type semiconductor layer 230 sequentially stacked on the surface of the substrate 100; the semiconductor device further comprises a PN step 211, wherein the upper step surface of the PN step 211 is a P-type semiconductor layer 230, the lower step surface of the PN step 211 is an N-type semiconductor layer 210, and the upper step surface and the lower step surface are connected to form the side surface of the PN step 211; an N-type semiconductor layer 210 formed on the substrate 100 to cover the substrate; a P-type semiconductor layer 230 formed to cover a region on the N-type semiconductor layer 210 other than the region for the N electrode on the N-type semiconductor layer 210 for emitting light in cooperation with the N-type semiconductor layer 210; the current blocking layer 300 and the current spreading layer 400 are sequentially disposed on the surface of the P-type semiconductor layer 230;
The first electrode layer includes a first P-type electrode 510 formed on the P-type semiconductor layer 230 and a first N-type electrode 520 for an N-electrode region formed on the N-type semiconductor layer 210; the first P-type electrode 510 is connected to the current spreading layer 400; the first N-type electrode 520 is connected with the lower step surface of the PN step 211; the first P-type electrode 510 and the first N-type electrode 520 are isolated from each other; the first insulating layer 600 covers the first N-type electrode 520, the current spreading layer 400, the side surface of the PN step 211, the first P-type electrode 510, and the lower step surface between the first N-type electrode 520 and the side surface of the PN step 211; the first insulating layer 600 is used for insulating the first N electrode from the first P electrode, and a first through hole 511 penetrating through the first P-type electrode 510 and a second through hole 521 penetrating through the first N-type electrode 520 are formed on the first insulating layer 600;
The second electrode layer includes a second P-type electrode 710 and a second N-type electrode 720, the second P-type electrode 710 and the second N-type electrode 720 being insulated from each other; the second P-type electrode 710 is connected to the first P-type electrode 510 through the first via 511; the second N-type electrode 720 is connected to the first N-type electrode 520 through the second through hole 521; the second insulating layer 800 is disposed on the surface of the second electrode layer;
The third via 1100 and the fourth via 1200 penetrate through the second insulating layer 800 and are respectively connected through the second P-type electrode 710 and the second N-type electrode 720;
The pad electrode layer includes a P pad electrode 1310 and an N pad electrode 1320, the P pad electrode 1310 and the N pad electrode 1320 being isolated from each other; the P-pad electrode 1310 and the second P-type electrode 710 are electrically connected through the third via 1100, and the N-pad electrode 1320 and the second N-type electrode 720 are electrically connected through the fourth via 1200.
Wherein the substrate 100 may include, but is not limited to, a sapphire substrate. In addition, a patterned substrate may also be selected.
The material of the N-type semiconductor layer 210 may be N-type doped gallium nitride, and the material of the P-type semiconductor layer 230 may be P-type doped gallium nitride, but is not limited to these two semiconductor types.
Among them, the light emitting layer 220 includes quantum wells and quantum barriers alternately stacked, but is not limited thereto. The light emitting layer 220 includes, but is not limited to, a red light emitting layer, a yellow light emitting layer, a green light emitting layer, or a blue light emitting layer. Quantum wells include, but are not limited to, inGaN quantum wells or AlInGaN quantum wells.
Wherein the current blocking layer 300 includes, but is not limited to, siO 2, the thickness of the current blocking layer 300 is typically 1500-5000A. .
The current spreading layer 400 occupies 70% -90% of the area of the light emitting element, including but not limited to one of ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO and GZO. The thickness of the current spreading layer 400 is 100 a to 500 a, and may be, for example, 100 a, 150 a, 200 a, 300 a, 500 a. The current spreading layer 400 may be deposited by magnetron sputtering or evaporation.
Wherein the first through hole 511 and the second through hole 521 are separated from each other without any extending and crossing; as shown in fig. 5, the third through hole 1100 and the fourth through hole 1200 are separated from each other without any extending and crossing, thereby ensuring separation of the upper electrode and the lower hetero electrode and cutting off a possible leakage path.
The first insulating layer 600 is a DBR reflective layer, which may be formed by alternately depositing SiO 2 and Ti 3O5. The thickness of the first insulating layer 600 is 2 μm to 6 μm, with 3.5 μm to 5.5 μm being optimal.
Wherein the second insulating layer 800 and/or the third insulating layer 1000 include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The thickness of the second insulating layer 800 and/or the third insulating layer 1000 is 5K-15K, for example 6K A, 8K A, 13K A, 15K.
Among the pad electrode layers, the P pad electrode 1310 may be 1,2, or more; the N pad electrode 1320 may be 1,2, or more. The pad electrode includes a metal monolayer in Cr, ni, ti, pt and Au, or a composite layer of several metals and/or alloys. The thickness of Al is 5K-20K A, the thickness of Pt is 0.5K-3K A, the thickness of Ti is 0.5-3K A, the thickness of Ni is 3K-12K A, and the thickness of Au is 1K-5K A. The pad electrode is a Bump electrode including a Sn component, that is, the P pad electrode 1310 and the N pad electrode 1320 may be Bump electrodes, and the electrode component is Sn. The bump electrode can be prepared by printing, electroplating or vapor plating. The height of the Bump electrode is more than or equal to 5 mu m, and the height of the solder paste is more than or equal to 20 mu m.
The embodiment of the invention also provides a preparation method of the light-emitting element, which comprises the following steps:
s1, providing a substrate 100, and sequentially depositing an N-type semiconductor layer 210, a light-emitting layer 220 and a P-type semiconductor layer 230 on the substrate 100 to form an epitaxial layer;
S2, forming patterns of an MESA layer by using photoresist, performing ICP etching on the epitaxial layer by taking the MESA layer as a mask, forming PN steps 211 by etching depths 10000-14000A, and removing the photoresist;
S3, depositing SiO 2 on the epitaxial layer, obtaining a current blocking layer 300 through photoetching, and removing photoresist; the current blocking layer 300 is located between the P-type semiconductor layer 230 and the current spreading layer 400, and functions to assist current spreading, and the thickness of the current blocking layer 300 is typically 1500-5000A.
S4, depositing a current expansion layer 400 on the epitaxial layer, photoetching the current expansion layer 400 by using photoresist to form a required current expansion layer, etching the current expansion layer 400 by using the current expansion layer as a mask, and removing photoresist to leak out of the bottom current expansion layer 400, wherein the thickness of the current expansion layer 400 is 100-500A;
S5, photoetching is carried out by using photoresist, a first electrode layer is manufactured by deposition, the first electrode layer comprises a first P-type electrode 510 and a first N-type electrode 520, the first P-type electrode 510 is covered on a film layer formed by overlapping a current blocking layer 300 and a current expansion layer 400, the photoresist is removed, the material of the first electrode layer is one metal or a combination of several metals such as Cr, ni, al, ti, au and Pt, and the thickness of the first electrode layer can be 2-5 mu m;
S6, depositing DBR Bragg reflection layers formed by alternately SiO2 and Ti3O5, namely a first insulation layer 600, wherein the thickness of the first insulation layer 600 is generally 2-6 mu m, the reflection effect is lacking when the first insulation layer 600 is too thin, the etching time is too long when the first insulation layer 600 is too thick, and the thickness of the whole first insulation layer 600 is 3-8 mu m;
S7, performing photoetching on the first insulating layer 600 by using photoresist, forming a first insulating layer pattern on the photoresist, performing ICP etching, and performing photoetching above the first P-type electrode 510 and the first N-type electrode 520 to respectively obtain a first through hole 511 and a second through hole 521;
s8, removing the photoresist after depositing the second electrode layer; wherein the second P-type electrode 710 is communicated with the first P-type electrode 510 through the first through hole 511, and the second N-type electrode 720 is communicated with the first N-type electrode 520 through the second through hole 521; the second electrode layer is designed to be as small as possible in area while ensuring normal connection to the first electrode layer. The second electrode layer is made of one or a combination of several metals such as Cr, ni, al, ti, au and Pt, and the thickness of the second electrode layer can be 2-5 mu m.
S9, a second insulating layer 800 is covered on the second P-type electrode 710 and the second N-type electrode 720. The second insulating layer 800 is deposited with an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride by PECVD, and the thickness of the second insulating layer 800 is 5000-15000A.
S10, etching to obtain a third through hole 1100 and a fourth through hole 1200 which penetrate through the second insulating layer 800;
S11, preparing a pad electrode through yellow light and deposition, and forming a P pad electrode 1310 and an N pad electrode 1320; wherein, the P-pad electrode 1310 is connected to the second P-type electrode 710 through the third via 1100, and the N-pad electrode 1320 is connected to the second N-type electrode 720 through the fourth via 1200; the pad electrode is one metal or a combination of several metals such as Cr, ni, al, ti, au, pt, etc., and the thicknesses of the P pad electrode 1310 and the N pad electrode 1320 may be 2-5 μm.
Embodiment 2:
This embodiment is a further improvement of embodiment 1, and the main improvement is that in embodiment 1, the second P-type electrode 710 extends below the N-pad electrode 1320, and the two electrodes are isolated from each other by the second insulating layer 800, so as to form a region as shown by a dashed box in fig. 4. When the second insulating layer 800 is broken or cracked for some reason, the second P-type electrode 710 and the N-pad electrode 1320 may be connected, resulting in occurrence of leakage current, which may reduce reliability when the conventional light emitting element is used. In the present embodiment, a support layer 900 which is not connected to the second electrode layer and the pad electrode layer, and a third insulating layer 1000 which is isolated from the pad electrode layer are added between the second insulating layer 800 and the pad electrode.
As shown in fig. 8 and 9, the support layer 900 is disposed between the second insulating layer 800 and the pad electrode layer; the third insulating layer 1000 entirely covers the surface formed by the second insulating layer 800 and the supporting layer 900; the support layer 900 is insulated from the second electrode layer by the second insulating layer 800; and the support layer 900 is insulated from the pad electrode layer by the third insulating layer 1000. The support layer 900 includes a P-region support layer and an N-region support layer; the P-region supporting layer covers the region of the second P-type electrode 710 and serves to block the second P-type electrode 710; the N-region supporting layer covers the region of the second N-type electrode 720, and serves to block the second N-type electrode 720. The third via 1100 and the fourth via 1200 penetrate through the second insulating layer 800 and the third insulating layer 1000 at the same time and then pass through the second P-type electrode 710 and the second N-type electrode 720, respectively.
The supporting layer 900 may be made of any material, and in order to ensure a better supporting effect, and to be suitable for a mature chip manufacturing process, the material of the supporting layer 900 is preferably a metal layer, and the metal layer includes a metal monolayer of Cr, ni, ti, pt and Au or a composite metal layer formed by several metal monolayers. The material of the supporting layer 900 is preferably a metal oxide with better conductivity, such as indium tin oxide, zinc oxide, and tin oxide. The material of the support layer 900 is preferably a DBR reflective layer having insulating properties, such as SiO 2/TiO2 DBR reflective layer. The thickness of the supporting layer 900 is less than 2 μm, the area of the supporting layer 900 accounts for 50% -80% of the area of the light-emitting element, the reflectivity of the electrode is 60% -95%, and the angle of the metal electrode is required to be 30-75 ° in order to ensure the subsequent film coverage.
The present embodiment adds the support layer 900 and the third insulating layer 1000 such that the P pad electrode 1310 and the N pad electrode 1320 of the pad electrode layer are not connected to the support layer 900, the support layer 900 and the second electrode layer, and are insulated from each other, and the pad electrode layer is electrically connected to the second electrode layer through a via hole penetrating the second insulating layer 800 and the third insulating layer 1000. And the third insulating layer 1000 and the second insulating layer 800 adopt the same photoetching to carry out open pore etching, so that the supporting layer 900 is wrapped in an insulating SiO 2 film from each surface, the supporting layer 900 and each layer of electrode are not connected with each other, the insulating isolation effect of the opposite electrode is achieved, the electric leakage of the light-emitting element caused by the breakage of the insulating layer is effectively avoided, and the reliability of the light-emitting element is improved.
The method of manufacturing the light emitting element according to this embodiment is also substantially the same as that of embodiment 1, except that in S10, before etching the second insulating layer 800 to obtain the third via 1100 and the fourth via 1200, the supporting layer 900 and the third insulating layer 1000 are sequentially deposited on the second insulating layer 800, and then the second insulating layer 800 and the third insulating layer 1000 are etched to obtain the third via 1100 and the fourth via 1200 at the same time in the region where the supporting layer 900 is not present above the second P-type electrode 710 and the second N-type electrode 720. The minimum distance between the third via 1100 and the fourth via 1200 and the edge of the support layer 900 is greater than 5 μm, so that each surface of the support layer 900 is completely wrapped in the second insulating layer 800 and the third insulating layer 1000, and the support layer 900 is isolated from conductive communication with any metal electrode.
The reliability of the light-emitting element in this embodiment mode is significantly improved as compared with embodiment mode 1 (test results are shown in table 1 below).
Otherwise, this embodiment is identical to embodiment 1, and a description thereof will be omitted.
Embodiment 3:
The present embodiment is substantially the same as embodiment 1, except that, in the second electrode layer, four outer surfaces of the second P-type electrode 710 each have a continuous concave portion, and the sum of the areas of the concave portions 1410 is 12.5% of the area of the second electrode layer. As shown in fig. 10, i.e., as many second electrode layers between two adjacent second p-type electrodes 710 at the edge position as possible are removed. The reflectance of the light-emitting element in this embodiment was further improved as compared with embodiment 1, and the overall brightness was further improved (the test results are shown in table 1 below).
Otherwise, this embodiment is identical to embodiment 1, and a description thereof will be omitted.
Comparative example
The difference between this comparative example and embodiment 1 is that, in the second electrode layer, no concave portion 1410 for reducing the area of the second electrode layer is formed in each of the four outer sides of the second P-type electrode 710, and the mask plan view of the second electrode layer is shown in fig. 3.
The light emitting elements described in embodiments 1, 2 and 3 and the comparative example were subjected to comparative tests under the same test conditions in which the test current was 65mA, and the light emitting elements provided in embodiments 1, 2 and 3 of the present invention had an increase in light emitting luminance of 0.2% and 0.3%, respectively, as compared with the comparative example. The number of impact cycles to turn off the lamp under each condition was confirmed by testing the condition of-45 to 125 c for 15min cold and hot impact each time, and the reliability of the light emitting element described in test embodiments 1, 2 and 3 and comparative example was found to be the highest, and thus the light emitting element in embodiment 2 was the highest.
TABLE 1
| Brightness (mw) | Reliability (cycle) | |
| Embodiment 1 | 168.1 | 3250 |
| Embodiment 2 | 168.2 | 4130 |
| Embodiment 3 | 168.7 | 3320 |
| Comparative example | 167.8 | 3278 |
The foregoing embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and to implement the same, not to limit the scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be included in the scope of the present invention.
Claims (9)
1. A semiconductor light emitting device includes a substrate (100), an epitaxial layer having PN steps, a first electrode layer, a first insulating layer (600), and a second electrode layer disposed in this order from bottom to top; the first electrode layer includes at least one first P-type electrode (510) and at least one first N-type electrode (520); the second electrode layer includes at least one second P-type electrode (710) and at least one second N-type electrode (720); the first P-type electrode (510) is electrically connected with the second P-type electrode (710) through a first through hole (511) formed in the first insulating layer (600), and the first N-type electrode (520) is electrically connected with the second N-type electrode (720) through a second through hole (521) formed in the first insulating layer (600); it is characterized in that the method comprises the steps of,
The second P-type electrode (710) has an outer side (711) connected to the upper and lower surfaces thereof and adjacent to the outer edge of the N-type semiconductor layer (210); the outer side surface (711) is provided with at least one concave part (1410) for reducing the area of the second electrode layer; the total area of the concave parts (1410) accounts for 5-20% of the area of the second electrode layer;
A second insulating layer (800), a supporting layer (900), a third insulating layer (1000) and a bonding pad electrode layer are sequentially arranged on the second electrode layer; the second insulating layer (800) is used for insulating the second P-type electrode (710) from the second N-type electrode (720); the third insulating layer (1000) completely covers the surface formed by the second insulating layer (800) and the supporting layer (900); the support layer (900) is insulated from the second electrode layer by the second insulating layer (800); and the support layer (900) is insulated from the pad electrode layer by the third insulating layer (1000).
2. The semiconductor light emitting device according to claim 1, wherein the recessed portion (1410) is provided between two adjacent first P-type electrodes (510).
3. The semiconductor light emitting device according to claim 1, wherein a length L1 of the concave portion (1410) is smaller than a maximum distance L2 between two first P-type electrodes (510) adjacent thereto;
and/or, the width W of the concave portion (1410) is greater than or equal to the diameter d of the first P-type electrode (510).
4. The semiconductor light-emitting device according to claim 1, wherein if the light-emitting element is square as a whole, the outer side surface (711) is a square outer side surface;
-said exterior side (711) of at least one side of the square has said recess (1410) continuous thereto;
or a square outer side surface, wherein at least two opposite outer side surfaces (711) are provided with continuous concave parts (1410);
Or the four outer side surfaces (711) of the square outer side surfaces each have the continuous concave portion (1410).
5. The semiconductor light emitting device according to claim 4, wherein each of the continuous concave portions (1410) is located between two of the first P-type electrodes (510), respectively.
6. The semiconductor light emitting device according to any one of claims 1to 5, wherein the pad electrode layer includes a P pad electrode (1310) electrically connected to the second P-type electrode (710) and an N pad electrode (1320) electrically connected to the second N-type electrode (720).
7. The semiconductor light emitting device according to claim 6, wherein the P-pad electrode (1310) is electrically connected to the second P-type electrode (710) through a third via (1100) formed in the second insulating layer (800), and the N-pad electrode (1320) is electrically connected to the second N-type electrode (720) through a fourth via (1200) formed in the second insulating layer (800).
8. The semiconductor light emitting device of claim 7, wherein the support layer comprises a P-region support layer, an N-region support layer; the P-region support layer covers an area of the second P-type electrode (710); the N-region support layer covers a region of the second N-type electrode (720).
9. A semiconductor light emitting device according to any of claims 1to 5, further comprising a current blocking layer (300) and a current spreading layer (400) between the epitaxial layer and the first electrode layer, the current spreading layer (400) being located above the current blocking layer (300).
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