CN114093932B - Integrated circuit packaging structure and preparation method thereof - Google Patents

Integrated circuit packaging structure and preparation method thereof Download PDF

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Publication number
CN114093932B
CN114093932B CN202210069497.7A CN202210069497A CN114093932B CN 114093932 B CN114093932 B CN 114093932B CN 202210069497 A CN202210069497 A CN 202210069497A CN 114093932 B CN114093932 B CN 114093932B
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semiconductor die
semiconductor
adhesive material
layer
dies
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CN114093932A (en
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张琳
王训朋
李华文
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Weihai Idencoder Electronic Technology Co ltd
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Weihai Idencoder Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/042—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention relates to an integrated circuit packaging structure and a preparation method thereof, relating to the field of semiconductor packaging. By forming a plurality of first recesses on the first and second sides of the first semiconductor die respectively, thereby forming a plurality of first bumps on the first and second sides of the second semiconductor die, respectively, thereby embedding the first bumps on the first side of the second semiconductor die into the first grooves on the first side of the corresponding first semiconductor die, through similar process means, the first, second, third and fourth semiconductor dies are mutually embedded together, the integration level of the integrated circuit packaging structure is improved, and simultaneously the volume of the whole integrated circuit packaging structure is reduced, meanwhile, the four semiconductor tube cores are bonded together to provide enough space for the preparation of a subsequent capacitor structure, so that the capacitor structure with large capacitance capacity is conveniently formed, and a capacitor element does not need to be additionally arranged.

Description

Integrated circuit packaging structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor packaging, in particular to an integrated circuit packaging structure and a preparation method thereof.
Background
Integrated circuit packaging is advancing with the development of integrated circuits. With the continuous development of various industries such as aerospace, aviation, machinery, light industry, chemical industry and the like, the whole machine also changes towards multifunction and miniaturization. Thus, the integrated circuit is required to have higher integration and more complex functions. Accordingly, the packaging density of the integrated circuit is required to be higher and higher, the number of leads is required to be higher and higher, the size is smaller and smaller, the weight is lighter and lighter, the updating is faster and faster, and the rationality and the scientificity of the packaging structure directly influence the quality of the integrated circuit. In the conventional integrated circuit package structure, a semiconductor chip is usually required to be disposed on a circuit substrate, and a capacitor, an inductor, a resistor, and other passive elements are also required to be additionally disposed, which increases the volume of the integrated circuit package, and is further not favorable for the technical trend of the integrated circuit package towards miniaturization development.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned deficiencies in the prior art and providing an integrated circuit package structure and a method for fabricating the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method for preparing an integrated circuit packaging structure comprises the following steps:
step (1): providing a first semiconductor die, and etching a first side and a second side of the first semiconductor die to form a plurality of first grooves on the first side and the second side of the first semiconductor die respectively.
Step (2): and providing a second semiconductor die, and etching the first side and the second side of the second semiconductor die to form a plurality of first bulges on the first side and the second side of the second semiconductor die respectively.
And (3): the first bumps on the first side of the second semiconductor die are then respectively embedded into the first recesses on the first side of the corresponding first semiconductor die.
And (4): and then providing a third semiconductor die, and etching the first side and the second side of the third semiconductor die to form a plurality of second grooves on the first side and the second side of the third semiconductor die respectively.
And (5): the first bumps on the second sides of the second semiconductor dies are then respectively embedded into the second grooves on the first sides of the corresponding third semiconductor dies.
And (6): and providing a fourth semiconductor die, and etching the first side and the second side of the fourth semiconductor die to form a plurality of second bulges on the first side and the second side of the fourth semiconductor die respectively.
And (7): the second bumps on the first side of the fourth semiconductor die are then respectively embedded into the second recesses on the second side of the corresponding third semiconductor die, and the second bumps on the second side of the fourth semiconductor die are respectively embedded into the first recesses on the second side of the corresponding first semiconductor die.
And (8): and forming a resin sealing layer which wraps the first, second, third and fourth semiconductor dies.
And (9): and then forming a cavity on the upper surface of the resin sealing layer, forming a plurality of first through holes on the bottom of the cavity, and forming a plurality of second through holes at one end of the resin sealing layer.
Step (10): then depositing a conductive material to form a first conductive layer covering the bottom of the cavity and filling the first through hole, then depositing a dielectric material on the first conductive layer to form a first dielectric layer, then depositing a conductive material on the first dielectric layer to form a second conductive layer covering the first dielectric layer and filling the second through hole, the first conductive layer, the first dielectric layer and the second conductive layer forming a capacitor structure.
Step (11): a redistribution layer is then formed on a lower surface of the resin encapsulation layer, the redistribution layer being electrically connected to the first, second, third, and fourth semiconductor die and the first and second conductive layers.
In a more preferred embodiment, the first groove, the first protrusion, the second groove, and the second protrusion are formed by one or more of wet etching, cutting, and laser ablation.
In a more preferred embodiment, in the step (3), an adhesive material is first disposed in the first groove on the first side of the first semiconductor die, and an adhesive material is disposed on the first side of the second semiconductor die, so that the first semiconductor die and the second semiconductor die are fixed together by the adhesive material.
In a more preferred embodiment, in the step (5), an adhesive material is first disposed in the second groove on the first side of the third semiconductor die, and an adhesive material is disposed on the second side of the second semiconductor die, so that the third semiconductor die and the second semiconductor die are fixed together by the adhesive material.
In a more preferred embodiment, in the step (7), an adhesive material is first disposed in the second groove on the second side of the third semiconductor die, then an adhesive material is disposed in the first groove on the second side of the first semiconductor die, then an adhesive material is disposed on the first and second sides of the fourth semiconductor die, and then the fourth semiconductor die is fixed to the first and third semiconductor dies by using the adhesive material.
In a more preferred embodiment, in the step (9), a first sidewall of the cavity exceeds edges of the first and fourth semiconductor dies, a second sidewall of the cavity exceeds edges of the first and second semiconductor dies, a third sidewall of the cavity exceeds edges of the second and third semiconductor dies, and a fourth sidewall of the cavity exceeds edges of the third and fourth semiconductor dies.
In a more preferred embodiment, in the step (9), a thickness of the resin sealing layer between the bottom surface of the cavity and the top surface of the first semiconductor die is 10 to 100 μm.
In a more preferred embodiment, in the step (10), the material of the first conductive layer and the second conductive layer is one or an alloy of two or more of copper, aluminum, tungsten, titanium, nickel, and silicon. The first dielectric layer is made of one or more of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide and hafnium oxide.
In a more preferred embodiment, in step (11), a conductive array is formed on the redistribution layer.
In a more preferable technical solution, the invention further provides an integrated circuit package structure formed by the above manufacturing method.
Compared with the prior art, the integrated circuit packaging structure and the preparation method thereof have the following beneficial effects:
a plurality of first grooves are respectively formed on the first side and the second side of the first semiconductor die, a plurality of first bulges are respectively formed on the first side and the second side of the second semiconductor die, the first bulges on the first side of the second semiconductor die are respectively embedded into the corresponding first grooves on the first side of the first semiconductor die, the second semiconductor die, the third semiconductor die and the fourth semiconductor die are mutually embedded through similar process means, the bonding stability among a plurality of chips is effectively improved, the integration level of the integrated circuit packaging structure is improved, meanwhile, because the four semiconductor dies are bonded together, enough space is provided for the preparation of a subsequent capacitor structure, and the formation of the capacitor structure with large capacitor capacity is facilitated, further, no additional capacitor is required. In the subsequent preparation process, only the concave cavity is formed on the upper surface of the resin sealing layer, and then only the capacitor element is arranged in the concave cavity and does not contact with the semiconductor dies, so that the influence of the preparation process of the capacitor element on the performance of the semiconductor dies is avoided, the stability of the capacitor element is effectively protected by the arrangement of the concave cavity, and the miniaturization and light and thin design of the integrated circuit packaging structure are facilitated.
Drawings
Fig. 1-11 are schematic structural diagrams of steps in the fabrication process of the integrated circuit package structure of the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a preparation method of an integrated circuit packaging structure, which comprises the following steps:
step (1): providing a first semiconductor die, and etching a first side and a second side of the first semiconductor die to form a plurality of first grooves on the first side and the second side of the first semiconductor die respectively.
Step (2): and providing a second semiconductor die, and etching the first side and the second side of the second semiconductor die to form a plurality of first bulges on the first side and the second side of the second semiconductor die respectively.
And (3): the first bumps on the first side of the second semiconductor die are then respectively embedded into the first recesses on the first side of the corresponding first semiconductor die.
And (4): and then providing a third semiconductor die, and etching the first side and the second side of the third semiconductor die to form a plurality of second grooves on the first side and the second side of the third semiconductor die respectively.
And (5): the first bumps on the second sides of the second semiconductor dies are then respectively embedded into the second grooves on the first sides of the corresponding third semiconductor dies.
And (6): and providing a fourth semiconductor die, and etching the first side and the second side of the fourth semiconductor die to form a plurality of second bulges on the first side and the second side of the fourth semiconductor die respectively.
And (7): the second bumps on the first side of the fourth semiconductor die are then respectively embedded into the second recesses on the second side of the corresponding third semiconductor die, and the second bumps on the second side of the fourth semiconductor die are respectively embedded into the first recesses on the second side of the corresponding first semiconductor die.
And (8): and forming a resin sealing layer which wraps the first, second, third and fourth semiconductor dies.
And (9): and then forming a cavity on the upper surface of the resin sealing layer, forming a plurality of first through holes on the bottom of the cavity, and forming a plurality of second through holes at one end of the resin sealing layer.
Step (10): then depositing a conductive material to form a first conductive layer covering the bottom of the cavity and filling the first through hole, then depositing a dielectric material on the first conductive layer to form a first dielectric layer, then depositing a conductive material on the first dielectric layer to form a second conductive layer covering the first dielectric layer and filling the second through hole, the first conductive layer, the first dielectric layer and the second conductive layer forming a capacitor structure.
Step (11): a redistribution layer is then formed on a lower surface of the resin encapsulation layer, the redistribution layer being electrically connected to the first, second, third, and fourth semiconductor die and the first and second conductive layers.
Further, the first groove, the first protrusion, the second groove and the second protrusion are formed by one or more of wet etching, cutting and laser ablation.
Further, in the step (3), an adhesive material is firstly disposed in the first groove on the first side of the first semiconductor die, and an adhesive material is disposed on the first side of the second semiconductor die, so that the first semiconductor die and the second semiconductor die are fixed together by the adhesive material.
Further, in the step (5), an adhesive material is firstly disposed in the second groove on the first side of the third semiconductor die, and an adhesive material is disposed on the second side of the second semiconductor die, so that the third semiconductor die and the second semiconductor die are fixed together by the adhesive material.
Further, in the step (7), an adhesive material is firstly disposed in the second groove on the second side of the third semiconductor die, then an adhesive material is disposed in the first groove on the second side of the first semiconductor die, then an adhesive material is disposed on the first and second sides of the fourth semiconductor die, and then the fourth semiconductor die is fixed to the first and third semiconductor dies by using the adhesive material.
Further, in the step (9), a first sidewall of the cavity exceeds edges of the first and fourth semiconductor dies, a second sidewall of the cavity exceeds edges of the first and second semiconductor dies, a third sidewall of the cavity exceeds edges of the second and third semiconductor dies, and a fourth sidewall of the cavity exceeds edges of the third and fourth semiconductor dies.
Further, in the step (9), a thickness of the sealing resin layer between the bottom surface of the cavity and the top surface of the first semiconductor die is 10 to 100 μm.
In the step (10), the material of the first conductive layer and the second conductive layer is one or an alloy of two or more of copper, aluminum, tungsten, titanium, nickel, and silicon. The first dielectric layer is made of one or more of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide and hafnium oxide.
Further, in step (11), a conductive array is formed on the redistribution layer.
The invention also provides an integrated circuit packaging structure which is formed by adopting the preparation method.
As shown in fig. 1 to 11, the present embodiment provides a method for manufacturing an integrated circuit package structure, the method comprising the following steps:
as shown in fig. 1, in step (1), a first semiconductor die 100 is provided, and a first side and a second side of the first semiconductor die 100 are etched to form a plurality of first grooves 101 on the first side and the second side of the first semiconductor die 100, respectively.
In a specific embodiment, the first semiconductor die 100 may be an active device such as a photodiode, a phototransistor, a microprocessor, a power chip, a digital signal processing chip, an application specific integrated circuit chip, a memory, and the like.
In a specific embodiment, a temporary carrier may be disposed, the first semiconductor die 100 is disposed on the temporary carrier, a hard mask layer is formed, a photoresist, more specifically, a positive photoresist or a negative photoresist, is coated on the hard mask layer, a patterned mask is formed through an exposure and development process, a pattern of the patterned mask is transferred to the hard mask layer to form a patterned hard mask, and the patterned hard mask is used to perform one or more of wet etching, cutting, and laser ablation on the first semiconductor die 100 to form the plurality of first grooves 101.
In a specific embodiment, the specific number of the first grooves 101 is three, four, five or six.
As shown in fig. 2, in step (2), a second semiconductor die 200 is provided, and a first side and a second side of the second semiconductor die 200 are etched, so as to form a plurality of first bumps 201 on the first side and the second side of the second semiconductor die 200, respectively.
In a specific embodiment, the second semiconductor die 200 may be a device that cooperates with the first semiconductor die 100, and further, the second semiconductor die 200 may be a photodiode, a phototransistor, a microprocessor, a power chip, a digital signal processing chip, an application specific integrated circuit chip, a memory, or the like.
In a particular embodiment, another temporary carrier board may be provided, on which the second semiconductor die 200 is then disposed, then forming a hard mask layer, coating a photoresist on the hard mask layer, more specifically a positive photoresist or a negative photoresist, and forming a patterned mask by exposure and development process, then transferring the pattern of the patterned mask plate to the hard mask layer to form a patterned hard mask, the second semiconductor die 200 is then subjected to one or more of wet etching, dicing, and laser ablation using a patterned hard mask to form a plurality of first bumps 201, the first protrusions 201 on the first side of the second semiconductor die 200 and the first grooves 101 on the first side of the first semiconductor die 100 are respectively disposed in a one-to-one correspondence.
As shown in fig. 3, in step (3), the first protrusions 201 on the first side of the second semiconductor die 200 are then respectively embedded into the first grooves 101 on the first side of the corresponding first semiconductor die 100.
Wherein, in the step (3), an adhesive material is firstly disposed in the first groove 101 on the first side of the first semiconductor die 100, and an adhesive material is disposed on the first side of the second semiconductor die 200, and then the first semiconductor die 100 and the second semiconductor die 200 are fixed together by the adhesive material.
In a specific embodiment, the bonding stability between the first protrusion 201 and the first groove 101 can be improved by disposing an adhesive material in the first groove 101, and the bonding of the first side of the first semiconductor die 100 to the first side of the second semiconductor die is facilitated by disposing an adhesive material on the first side of the second semiconductor die 200.
In a specific embodiment, the adhesive material may be an organic adhesive material suitable for epoxy-based adhesive, acrylic-based adhesive, silicone adhesive, and the like, so as to facilitate the bonding stability between the first semiconductor die 100 and the second semiconductor die 200, and due to the arrangement of the first groove and the first protrusion, the mechanical stress may be absorbed in the die bonding process, so as to avoid cracking, and further improve the bonding stability between the two.
As shown in fig. 4, in step (4), a third semiconductor die 300 is provided, and a first side and a second side of the third semiconductor die 300 are etched to form a plurality of second grooves 301 on the first side and the second side of the third semiconductor die 300, respectively.
In a particular embodiment, the second recess 301 may be formed using a similar process as the first recess 101.
As shown in fig. 5, in step (5), the first bumps 201 on the second sides of the second semiconductor dies 200 are then respectively embedded into the second grooves 301 on the first sides of the corresponding third semiconductor dies 300.
Wherein, in the step (5), an adhesive material is firstly disposed in the second groove 301 on the first side of the third semiconductor die 300, and an adhesive material is disposed on the second side of the second semiconductor die 200, so that the third semiconductor die 300 and the second semiconductor die 200 are fixed together by the adhesive material.
In a specific embodiment, the bonding stability between the first bump 201 and the second groove 301 can be improved by disposing an adhesive material in the second groove 301, and the bonding of the first side of the third semiconductor die 300 to the second side of the second semiconductor die is facilitated by disposing an adhesive material on the first side of the third semiconductor die 300.
In a specific embodiment, the adhesive material may be an organic adhesive material suitable for epoxy-based adhesive, acrylic-based adhesive, silicone adhesive, and the like, so as to facilitate the bonding stability between the third semiconductor die 300 and the second semiconductor die 200, and due to the arrangement of the second groove 301 and the first protrusion 201, the mechanical stress may be absorbed during the die bonding process, so as to avoid cracking, and further improve the bonding stability between the two.
As shown in fig. 6, in step (6), a fourth semiconductor die 400 is provided, and a first side and a second side of the fourth semiconductor die 400 are etched to form a plurality of second protrusions 401 on the first side and the second side of the fourth semiconductor die 400, respectively.
In a particular embodiment, the second bump 401 may be formed using a process similar to that used to form the first bump 201.
As shown in fig. 7, in step (7), the second bumps 401 on the first side of the fourth semiconductor die 400 are then respectively embedded into the second grooves 301 on the second side of the corresponding third semiconductor die 300, and the second bumps 401 on the second side of the fourth semiconductor die 400 are respectively embedded into the first grooves 101 on the second side of the corresponding first semiconductor die 100.
Wherein in step (7), an adhesive material is first disposed in the second recess 301 on the second side of the third semiconductor die 300, then an adhesive material is disposed in the first recess 101 on the second side of the first semiconductor die 100, then an adhesive material is disposed on the first and second sides of the fourth semiconductor die 400, and then the fourth semiconductor die 400 is fixed to the first and third semiconductor dies 100 and 300 by the adhesive material.
In a specific embodiment, the bonding stability between the second protrusion 401 and the first and second grooves 101 and 301 can be improved by disposing an adhesive material in the first and second grooves 101 and 301, and by disposing an adhesive material on the first and second sides of the fourth semiconductor die 400, the first and second sides of the fourth semiconductor die 400 are conveniently bonded to the second side of the third semiconductor die 300 and the second side of the first semiconductor die 100, respectively.
In a specific embodiment, the adhesive material may be an organic adhesive material suitable for epoxy-based adhesive, acrylic-based adhesive, silicone adhesive, etc., so as to facilitate the bonding stability between the fourth semiconductor die 400 and the first and third semiconductor dies, and due to the arrangement of the second protrusion 401, the first groove 101, and the second groove 201, the mechanical stress may be absorbed during the die bonding process, so as to avoid cracking, and further improve the bonding stability between the three.
As shown in fig. 8, in step (8), an encapsulant resin layer 500 is formed, wherein the encapsulant resin layer 500 encapsulates the first, second, third and fourth semiconductor dies 100, 200, 300 and 400.
In a specific embodiment, the sealing resin layer may be an epoxy material.
In a specific embodiment, the sealing layer of resin is formed by a suitable process such as transfer molding, injection molding, coating, heat press bonding, and the like.
As shown in fig. 9, in step (9), a cavity 501 is formed on the upper surface of the resin sealing layer 500, a plurality of first through holes 502 are formed in the bottom of the cavity 501, and a plurality of second through holes 503 are formed at one end of the resin sealing layer 500.
Wherein, in step (9), a first sidewall of the cavity 501 exceeds the edges of the first and fourth semiconductor dies 100 and 400, a second sidewall of the cavity 501 exceeds the edges of the first and second semiconductor dies 100 and 200, a third sidewall of the cavity 501 exceeds the edges of the second and third semiconductor dies 200 and 300, and a fourth sidewall of the cavity 501 exceeds the edges of the third and fourth semiconductor dies 300 and 400.
Wherein, in the step (9), the thickness of the sealing resin layer between the bottom surface of the cavity 501 and the top surface of the first semiconductor die 100 is 10 to 100 μm.
In a specific embodiment, the cavity 501 is formed by a laser ablation process.
In a specific embodiment, since the four sidewalls of the cavity 501 exceed the edges of four semiconductor dies, a large-sized cavity 501 can be formed, and a large-sized capacitor can be integrated in the resin encapsulation layer 500.
As shown in fig. 10, in step (10), a conductive material is then deposited to form a first conductive layer 601, the first conductive layer 601 covers the bottom of the cavity 501 and fills the first through hole 502, a dielectric material is then deposited on the first conductive layer 601 to form a first dielectric layer 602, a conductive material is then deposited on the first dielectric layer 602 to form a second conductive layer 603, the second conductive layer 603 covers the first dielectric layer 602 and fills the second through hole 503, and the first conductive layer 601, the first dielectric layer 602 and the second conductive layer 603 constitute a capacitor structure.
In the step (10), the first conductive layer 601 and the second conductive layer 603 are made of one or an alloy of two or more of copper, aluminum, tungsten, titanium, nickel, and silicon. The first dielectric layer 602 is made of one or more of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and hafnium oxide.
In a specific embodiment, the first conductive layer 601 and the second conductive layer 603 are formed by electroplating, thermal evaporation, magnetron sputtering, electroless plating, chemical vapor deposition, or other suitable processes. The first dielectric layer 602 is formed by a chemical vapor deposition process.
As shown in fig. 11, in step (11), a redistribution layer 700 is formed on the lower surface of the resin sealing layer 600, and the redistribution layer 700 is electrically connected to the first, second, third and fourth semiconductor dies 100 and 400 and the first and second conductive layers 601 and 603.
Further, in step (11), a conductive array 800 is formed on the redistribution layer 700.
As shown in fig. 11, the present invention further provides an integrated circuit package structure formed by the above-mentioned manufacturing method.
Compared with the prior art, the integrated circuit packaging structure and the preparation method thereof have the following beneficial effects:
a plurality of first grooves are respectively formed on the first side and the second side of the first semiconductor die, a plurality of first bulges are respectively formed on the first side and the second side of the second semiconductor die, the first bulges on the first side of the second semiconductor die are respectively embedded into the corresponding first grooves on the first side of the first semiconductor die, the second semiconductor die, the third semiconductor die and the fourth semiconductor die are mutually embedded through similar process means, the bonding stability among a plurality of chips is effectively improved, the integration level of the integrated circuit packaging structure is improved, meanwhile, because the four semiconductor dies are bonded together, enough space is provided for the preparation of a subsequent capacitor structure, and the formation of the capacitor structure with large capacitor capacity is facilitated, further, no additional capacitor is required. In the subsequent preparation process, only the concave cavity is formed on the upper surface of the resin sealing layer, and then only the capacitor element is arranged in the concave cavity and does not contact with the semiconductor dies, so that the influence of the preparation process of the capacitor element on the performance of the semiconductor dies is avoided, the stability of the capacitor element is effectively protected by the arrangement of the concave cavity, and the miniaturization and light and thin design of the integrated circuit packaging structure are facilitated.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A method for manufacturing an integrated circuit package structure is characterized in that: the method comprises the following steps:
step (1): providing a first semiconductor die, and etching a first side and a second side of the first semiconductor die to form a plurality of first grooves on the first side and the second side of the first semiconductor die respectively;
step (2): providing a second semiconductor die, and etching a first side and a second side of the second semiconductor die to form a plurality of first bulges on the first side and the second side of the second semiconductor die respectively;
and (3): then embedding the first bumps on the first side of the second semiconductor die into the first grooves on the first side of the corresponding first semiconductor die, respectively;
and (4): then providing a third semiconductor die, and etching the first side and the second side of the third semiconductor die to form a plurality of second grooves on the first side and the second side of the third semiconductor die respectively;
and (5): then embedding the first bumps on the second sides of the second semiconductor dies into the second grooves on the first sides of the corresponding third semiconductor dies, respectively;
and (6): providing a fourth semiconductor die, and etching a first side and a second side of the fourth semiconductor die to form a plurality of second bulges on the first side and the second side of the fourth semiconductor die respectively;
and (7): then embedding the second bumps on the first sides of the fourth semiconductor dies into the second grooves on the second sides of the corresponding third semiconductor dies, respectively, and embedding the second bumps on the second sides of the fourth semiconductor dies into the first grooves on the second sides of the corresponding first semiconductor dies, respectively;
and (8): then forming a resin sealing layer which wraps the first, second, third and fourth semiconductor dies;
and (9): forming a cavity on the upper surface of the resin sealing layer, forming a plurality of first through holes at the bottom of the cavity, and forming a plurality of second through holes at one end of the resin sealing layer;
step (10): then depositing a conductive material to form a first conductive layer, wherein the first conductive layer covers the bottom of the cavity and fills the first through hole, then depositing a dielectric material on the first conductive layer to form a first dielectric layer, then depositing a conductive material on the first dielectric layer to form a second conductive layer, wherein the second conductive layer covers the first dielectric layer and fills the second through hole, and the first conductive layer, the first dielectric layer and the second conductive layer form a capacitor structure;
step (11): a redistribution layer is then formed on a lower surface of the resin encapsulation layer, the redistribution layer being electrically connected to the first, second, third, and fourth semiconductor die and the first and second conductive layers.
2. The method of claim 1, wherein: and forming the first groove, the first protrusion, the second groove and the second protrusion by using a wet etching process.
3. The method of claim 1, wherein: in the step (3), an adhesive material is first disposed in the first recess on the first side of the first semiconductor die, and an adhesive material is disposed on the first side of the second semiconductor die, and the first semiconductor die and the second semiconductor die are fixed together by the adhesive material.
4. The method of claim 1, wherein: in the step (5), an adhesive material is firstly disposed in the second groove on the first side of the third semiconductor die, and an adhesive material is disposed on the second side of the second semiconductor die, so that the third semiconductor die and the second semiconductor die are fixed together by the adhesive material.
5. The method of claim 1, wherein: in the step (7), an adhesive material is first disposed in the second groove on the second side of the third semiconductor die, then an adhesive material is disposed in the first groove on the second side of the first semiconductor die, then an adhesive material is disposed on the first and second sides of the fourth semiconductor die, and then the fourth semiconductor die is fixed to the first and third semiconductor dies by the adhesive material.
6. The method of claim 1, wherein: in step (9), a first sidewall of the cavity exceeds edges of the first and fourth semiconductor dies, a second sidewall of the cavity exceeds edges of the first and second semiconductor dies, a third sidewall of the cavity exceeds edges of the second and third semiconductor dies, and a fourth sidewall of the cavity exceeds edges of the third and fourth semiconductor dies.
7. The method of claim 6, wherein: in the step (9), a thickness of the sealing resin layer between the bottom surface of the cavity and the top surface of the first semiconductor die is 10 to 100 μm.
8. The method of claim 1, wherein: in the step (10), the first conductive layer and the second conductive layer are made of one or an alloy of two or more of copper, aluminum, tungsten, titanium, nickel, and silicon, and the first dielectric layer is made of one or more of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and hafnium oxide.
9. The method of claim 1, wherein: in step (11), a conductive array is formed on the redistribution layer.
10. An integrated circuit package structure formed by the method of any one of claims 1-9.
CN202210069497.7A 2022-01-21 2022-01-21 Integrated circuit packaging structure and preparation method thereof Active CN114093932B (en)

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