CN114077512A

CN114077512A - Exception reset processing method, exception handling device and storage medium

Info

Publication number: CN114077512A
Application number: CN202010850120.6A
Authority: CN
Inventors: 刘利民; 霍瑞
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-08-21
Filing date: 2020-08-21
Publication date: 2022-02-22

Abstract

The embodiment of the application discloses an exception reset processing method, an exception processing device and a storage medium, which not only solve the problem that exception reset information is emptied after an SRAM is initialized, but also write the exception reset information into a flash memory before being emptied, and can provide a basis for subsequently positioning an exception and solving the exception. The method comprises the following steps: acquiring abnormal reset information after the first chip is reset and before the SRAM is initialized; and writing abnormal reset information into the flash memory through the initialized minimum system, wherein the minimum system runs on the first chip and is a necessary running driver of the flash memory.

Description

Exception reset processing method, exception handling device and storage medium

Technical Field

The embodiment of the application relates to the technical field of computers, in particular to an exception reset processing method, an exception handling device and a storage medium.

Background

At present, wearable devices, internet of things (IoT) and other devices all use Micro Control Unit (MCU) chips to achieve functions such as low power consumption. In the running process of the software program based on the MCU chip, the software program at the moment can not identify the system abnormality due to the phenomena of running jamming and the like of the software program, so that the reset recovery of the MCU chip can not be carried out by means of active restart and the like.

The MCU chip supports the watchdog technology, namely, the watchdog can overflow a trigger pulse to trigger the MCU chip to reset if the pulse timer is not cleared and other operations are not carried out in the preset time of the software program. After the MCU chip is reset, the software program can be recovered to normal operation. Please refer to fig. 1, which is a flowchart illustrating resetting of an MCU chip by a watchdog in the prior art. As can be seen from fig. 1, the MCU chip initializes a Static Random Access Memory (SRAM) and clears data based on a system Reset Handler (Reset Handler), and after the initialization of the SRAM is completed, the system is normally started by running a main function (main). After the system is normally started, the MCU chip enables the watchdog and feeds the watchdog regularly, and the timed feeding dog can be understood as a software program to clear the pulse timer in preset time and other operations. However, once the watchdog is enabled by the MCU chip, the software program is jammed during operation, but the data in the SRAM is cleared and initialized, which results in that the system cannot locate and solve the abnormal phenomena such as jamming after restarting, resulting in poor stability of the device.

Therefore, how to locate and solve the abnormal problems such as the dead software program card after the system is restarted becomes a problem which needs to be solved urgently.

Disclosure of Invention

The embodiment of the application provides an exception reset processing method, an exception processing device and a storage medium, which not only solve the problem that exception reset information is emptied after an SRAM is initialized, but also write the exception reset information into a flash memory before being emptied, and can provide a basis for subsequently positioning an exception and solving the exception.

In a first aspect, an embodiment of the present application provides a method for handling exception resetting, where the method may include: acquiring abnormal reset information after the first chip is reset and before the SRAM is initialized; and writing the abnormal reset information into a flash memory through an initialized minimum system, wherein the minimum system runs on the first chip and is a necessary running driver of the flash memory. Through the mode, the initialized minimum system is used for writing the abnormal reset information into the flash memory, and the purpose is not only to activate the flash memory by using less resources so that the flash memory can be in a basic normal operation state, but also to store the abnormal reset information in the flash memory in the operation state, so that the abnormal reset information is ensured not to be lost even under the condition of power failure, and the acquirability of the abnormal reset information during subsequent positioning and solving the abnormal reset problem is ensured.

Optionally, with reference to the first aspect, in a first possible implementation manner, the method further includes: clearing an abnormal reset mark, wherein the abnormal reset mark is used for indicating that the first chip is abnormally reset; after the abnormal reset mark is cleared, the state of a system interrupt module, the state of a system real-time clock, the state of system universal input and output, the state of a flash memory drive, the state of the flash memory and the state of a file system are adjusted to be corresponding running states in sequence so as to obtain the initialized minimum system, wherein the system interrupt module, the system real-time clock and the system universal input and output correspond to the first chip, and the flash memory drive corresponds to the flash memory.

Optionally, with reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner, the method further includes: and setting a header mark for the abnormal reset information, wherein the header mark is used for reflecting the abnormal condition of the abnormal reset information. By the mode, the header mark is arranged in the abnormal resetting information, so that a quick and convenient positioning mode can be provided for subsequent positioning and solving the problem of abnormal resetting.

Optionally, with reference to the first aspect or the first to the second possible implementation manners, in a third possible implementation manner, the obtaining of the abnormal reset information includes: acquiring the running state of the first chip; and when the running state of the first chip reflects that the first chip is reset based on the watchdog and is abnormal, acquiring abnormal reset information.

Optionally, with reference to the first aspect or the first to the second possible implementation manners, in a fourth possible implementation manner, before the obtaining of the abnormal reset information, the method further includes: judging whether the value of a preset zone bit is changed into a first value, wherein the first value is used for indicating that the current starting state of the first chip is identified; correspondingly, the acquiring the abnormal reset information includes: and when the value of the preset zone bit is not changed into the first value, acquiring abnormal reset information.

Optionally, with reference to the first to fourth possible implementation manners of the first aspect, in a fifth possible implementation manner, after the writing the abnormal reset information into the flash memory, the method further includes: resetting the first chip again based on a system reset handling function.

Optionally, with reference to the first to fourth possible implementation manners of the first aspect, in a sixth possible implementation manner, after the writing the abnormal reset information into the flash memory, the method further includes: and triggering a normal starting process of the system based on a system resetting processing function.

In a second aspect, an embodiment of the present application provides an exception handling apparatus, which may include:

the acquisition unit is used for acquiring abnormal reset information after the first chip is reset and before the Static Random Access Memory (SRAM) is initialized;

and the writing unit is used for writing the abnormal reset information into the flash memory through the initialized minimum system, wherein the minimum system runs on the first chip and is a necessary running driver of the flash memory.

Optionally, with reference to the second aspect, in a first possible implementation manner, the exception handling apparatus further includes:

the clearing unit is used for clearing an abnormal reset mark, and the abnormal reset mark is used for indicating that the first chip is abnormally reset;

and the adjusting unit is used for adjusting the state of a system interrupt module, the state of a system real-time clock, the state of system universal input and output, the state of a flash memory drive, the state of the flash memory and the state of a file system into corresponding running states in sequence after the abnormal reset mark is cleared so as to obtain the initialized minimum system, wherein the system interrupt module, the system real-time clock and the system universal input and output correspond to the first chip, and the flash memory drive corresponds to the flash memory.

Optionally, with reference to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner, the exception handling apparatus further includes:

and the setting unit is used for setting a header mark for the abnormal reset information, and the header mark is used for reflecting the abnormal condition of the abnormal reset information.

Optionally, with reference to the second aspect or the first to second possible implementation manners, in a third possible implementation manner, the obtaining unit includes:

the first acquisition module is used for acquiring the running state of the first chip;

the first obtaining module is configured to obtain abnormal reset information when the operating state of the first chip reflects that the first chip is reset based on the watchdog and an abnormality occurs.

Optionally, with reference to the second aspect or the first to second possible implementation manners of the second aspect, in a fourth possible implementation manner, the exception handling apparatus further includes:

a judging unit, configured to judge whether a value of a preset flag is changed to a first value before the abnormal reset information is obtained, where the first value is used to indicate that a current start state of the first chip is identified;

correspondingly, the obtaining unit includes:

and the second acquisition module is used for acquiring abnormal reset information when the value of the preset zone bit is not changed into the first value.

Optionally, with reference to the first to fourth possible implementation manners of the second aspect, in a fifth possible implementation manner, the exception handling apparatus further includes:

and the resetting unit is used for resetting the first chip again based on a system reset processing function after the abnormal reset information is written into the flash memory.

Optionally, with reference to the first to fourth possible implementation manners of the second aspect, in a sixth possible implementation manner, the exception handling apparatus further includes:

and the triggering unit is used for triggering a system normal starting process based on a system reset processing function after the abnormal reset information is written into the flash memory.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which includes instructions that, when executed on a computer, cause the computer to perform the method according to the first aspect or any one of the possible implementation manners of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer program product containing instructions that, when executed on a computer, cause the computer to perform a method according to the first aspect or any one of the possible implementations of the first aspect.

In a fifth aspect, an embodiment of the present application provides a chip system, where the chip system includes a processor, configured to support an exception handling apparatus to implement the functions in the first aspect or any one of the possible implementation manners of the first aspect. In one possible design, the system-on-chip further includes a memory for storing program instructions and data necessary for the information generating device. The chip system may be constituted by a chip, or may include a chip and other discrete devices.

According to the technical scheme, the embodiment of the application has the following advantages:

in the embodiment of the present application, if the first chip has been abnormally reset before the SRAM is initialized, the abnormal reset information needs to be obtained first, and then the necessary operation driver that operates on the first chip and is the flash memory is further initialized, so that the flash memory can be in the basic operation state, and thus the abnormal reset information can be written into the flash memory through the initialized minimum system. By the mode, abnormal reset information generated when the first chip is subjected to abnormal reset before the SRAM is initialized is avoided, and the first chip is emptied after the SRAM is initialized; and because the emptying of the SRAM and the data initialization are invisible by default, the abnormal reset information is written into the flash memory before being emptied, so that a basis can be provided for subsequently positioning the abnormality and solving the abnormality.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present application.

Fig. 1 is a flowchart of resetting an MCU chip by a watchdog in the prior art;

fig. 2 is a schematic diagram of an embodiment of a method for handling an exception reset according to an embodiment of the present application;

fig. 3 is a schematic diagram of another embodiment of a processing method for exception resetting according to an embodiment of the present application;

FIG. 4 is a flow diagram of exception reset processing provided in an embodiment of the present application;

fig. 5 is a schematic hardware structure diagram of a communication device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of an exception handling apparatus according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of another exception handling apparatus according to an embodiment of the present application.

Detailed Description

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The technical solution in the present application will be described below with reference to the accompanying drawings.

In the industry at present, the reset of the MCU chip with abnormal phenomena can be triggered by the watchdog technology. Initializing the SRAM and clearing data based on a system reset processing function by the MCU chip, and after the initialization of the SRAM is completed, normally starting the system by running a main function. After the system is normally started, the MCU chip enables the watchdog and feeds the watchdog regularly, and after the MCU chip enables the watchdog, once the software program has abnormal phenomena such as running deadlock and the like, the abnormal phenomena such as deadlock and the like are generated, but because the data in the SRAM is emptied and initialized, the abnormal phenomena such as deadlock and the like cannot be positioned and solved after the system is restarted, and the stability of the equipment is poor.

Therefore, in order to solve the above technical problem, in the embodiment of the present application, an exception reset processing method is provided, in which exception reset information is acquired after a reset of a first chip occurs and before an SRAM is initialized, and then the exception reset information is written into a flash memory based on a minimum system after the initialization, so that the exception reset information can be saved into the flash memory without data loss due to power failure before the SRAM is initialized, and a basis is provided for subsequently locating an exception and solving the exception. It should be understood that the first chip described above may include, but is not limited to, an MCU chip, a Global Positioning System (GPS) chip, or other main chip including an SRAM. Therefore, the above-described processing method for abnormal reset can be applied to an MCU chip, a GPS chip, or other main chips including an SRAM, and is not specifically limited in this embodiment of the present application. In the embodiment of the present application, only the MCU chip is taken as an example for description.

The processing method of the exception reset in the present application will be described below from the viewpoint of the method. Referring to fig. 2, a schematic diagram of an embodiment of a method for handling an exception reset according to an embodiment of the present application is shown, where the method includes:

201. after the first chip is reset and before the SRAM is initialized, acquiring abnormal reset information.

The described abnormal reset information can indicate that the first chip has undergone an abnormal stuck reset after reset. Therefore, it is necessary to acquire the abnormal reset information before the SRAM in the first chip is initialized, so as to provide a basis for subsequently locating and solving the abnormal reset problem.

For example, in some embodiments, when a watchdog resets a first chip or a software program cannot recognize a system boot state, the first chip may have an abnormal reset problem. Therefore, for obtaining the abnormal reset information, the abnormal reset information can be obtained in two ways:

the first method comprises the following steps: acquiring the running state of the first chip; and when the running state of the first chip reflects that the first chip is reset based on the watchdog and is abnormal, acquiring abnormal reset information.

In the embodiment, the operation condition of the first chip in the operation process can reflect the operation state of the first chip in the operation process. For example: the running speed is too slow, the running power consumption exceeds a normal range value, or the clock configuration exceeds a main frequency working range of the first chip, and the like, so that the running state of the first chip can be reflected to be abnormal, and the running state of the first chip can also be reflected to be that the first chip is reset based on the watchdog to be abnormal. In other words, an abnormal reset occurs during the reset of the first chip based on the watchdog, and the abnormal operation state of the first chip at this time is caused by the abnormal reset of the first chip by the watchdog. Therefore, by acquiring the operating state of the first chip and when the operating state of the first chip reflects that the watchdog resets the first chip, the abnormal reset information can be acquired.

And the second method comprises the following steps: before the obtaining of the abnormal reset information, the method further comprises: judging whether the value of a preset zone bit is changed into a first value, wherein the first value is used for indicating that the current starting state of the first chip is identified; correspondingly, the acquiring the abnormal reset information includes: and when the value of the preset zone bit is not changed into the first value, acquiring abnormal reset information.

In an embodiment, if the software program cannot recognize the current startup state of the first chip, it indicates that the first chip is also abnormally reset. Therefore, whether the current starting state of the first chip is identified by the software program is judged by setting the preset zone bit and using whether the value in the preset zone bit is changed into the first value as a judgment basis. If the value of the preset flag bit is not changed to the first value, it indicates that the current start-up state of the first chip is not recognized by the software program, and the abnormal reset information may be obtained. It can also be understood that, whether the preset flag is set is determined, and once the preset flag is not set, it indicates that the current start state of the first chip is not recognized by the software program, and further indicates that the first chip is abnormally reset, and at this time, the abnormal reset information can be acquired.

It should be understood that the first value described above may be "1", "2", etc., and is not limited in particular, as long as the first value can be used to indicate that the current activation state of the first chip is recognized. In addition, in practical application, the abnormal reset information may be obtained in other manners, which is not limited herein.

Optionally, in other embodiments, the method further comprises: and setting a header mark for the abnormal reset information, wherein the header mark is used for reflecting the abnormal condition of the abnormal reset information.

In an embodiment, after the exception reset information is obtained, a header flag may be set to the exception reset information, so that the header flag may be used to reflect an exception condition of the exception reset information, such as: the location where the abnormal reset occurred or specific detailed information, etc. By setting the header mark in the abnormal resetting information, a quick and convenient positioning mode can be provided for subsequent positioning and solving the problem of abnormal resetting.

202. And writing abnormal reset information into the flash memory through the initialized minimum system, wherein the minimum system runs on the first chip and is a necessary running driver of the flash memory.

In an embodiment, the flash memory includes a memory device inside the first chip and an external memory device, and has a characteristic that data is not lost even when power is lost. The minimum system described above can be understood as running on the first chip and as a necessary running driver in the flash memory. The abnormal reset information is written into the flash memory by utilizing the initialized minimum system, and the aim is not only to activate the flash memory by using less resources so that the flash memory can be in a basic normal operation state, but also to store the abnormal reset information in the flash memory in the operation state, so that the abnormal reset information is ensured not to be lost even under the condition of power failure, and the acquirability of the abnormal reset information during subsequent positioning and solving of the abnormal reset problem is ensured.

For convenience of understanding, referring to fig. 3 on the basis of the embodiment described in fig. 2, another embodiment of the exception reset processing method provided in the embodiment of the present application is schematically illustrated, and the method may include:

301. after the first chip is reset and before the SRAM is initialized, acquiring abnormal reset information.

In an embodiment, step 301 may be understood by referring to the content described in step 201 in fig. 2, which is not described herein again.

302. And clearing an abnormal reset mark, wherein the abnormal reset mark is used for indicating that the first chip is abnormally reset.

In an embodiment, since the abnormal reset flag can be used to indicate that the first chip is abnormally reset, regardless of whether the abnormal reset is caused by the abnormality that is described in the first step 201 in fig. 2 and is caused by the watchdog resetting the first chip, or the abnormality that is described in the second step and is caused by the software program failing to recognize the current start state of the first chip, the abnormal reset flag needs to be cleared after the abnormal reset information is obtained.

303. After the abnormal reset mark is cleared, the state of a system interrupt module, the state of a system real-time clock, the state of system universal input and output, the state of a flash memory drive, the state of a flash memory and the state of a file system are adjusted to be corresponding running states in sequence to obtain the initialized minimum system, wherein the system interrupt module, the system real-time clock and the system universal input and output correspond to a first chip, and the flash memory drive corresponds to the flash memory.

In an embodiment, the minimum system may be understood as being composed of a system interrupt module, a real-time clock (RTC), a general-purpose input/output (GPIO), a flash memory driver, a flash memory, and a File System (FS). For different types of first chips, the system interrupt module, the system real-time clock and the system general input/output in the minimum system are different, so that the system interrupt module, the system real-time clock and the system general input/output in the minimum system correspond to the first chip, and the minimum system can stably operate on different first chips.

In addition, after the abnormal reset flag is cleared, the state of the system interrupt module, the state of the system real-time clock, the state of the system universal input/output, the state of the flash memory driver, the state of the flash memory, and the state of the file system need to be adjusted to the corresponding operating states in sequence. This is done primarily to initialize the minimal system so that the initialized minimal system can be activated and thus be in a running state.

304. And writing the abnormal reset information into the flash memory through the initialized minimum system.

In an embodiment, the file system runs on the first chip and is used for managing data in the flash memory. Therefore, after the initialized minimum system is obtained, the abnormal reset information can be written into the flash memory through the initialized minimum system, so that the file system can manage the abnormal reset information.

305. The first chip is reset again based on the system reset handling function.

It is understood that, after the abnormal reset information is saved to the file system in step 304, the first chip may be reset again based on the system reset processing function, so as to enter a system normal starting process to recover the normal operation of the first chip.

Optionally, 306, triggering a normal system start-up process based on the system reset processing function.

Alternatively, after the abnormal reset information is saved in the file system in step 304, the normal system startup process may be triggered directly based on the system reset processing function.

It should be noted that the above mentioned normal system start-up process can be understood as follows: initializing the SRAM based on the system reset function, and operating the main function after the initialization of the SRAM is completed, so that the system is normally started to recover the normal operation of the first chip.

In addition, please refer to fig. 4, which is a flowchart illustrating an exception reset process according to an embodiment of the present application. As can be seen from fig. 4, when the first chip is reset based on the system reset processing function, it is first determined whether an abnormal reset caused by a watchdog reset or an abnormal reset that is not recognized by the software program occurs; if abnormal reset caused by watchdog reset or abnormal reset which is not identified by software program occurs, acquiring abnormal reset information and initializing a minimum system; then writing the abnormal reset information into the flash memory based on the initialized minimum system; finally, resetting the system again or entering a normal starting process of the system. Otherwise, if the abnormal reset caused by the reset of the watchdog or the abnormal reset which is not identified by the software program does not occur, the system directly enters the normal starting process.

As can also be seen from fig. 4, the initialization minimization system described above can be understood as: clearing abnormal reset mark → initializing system interrupt module → configuring system clock → initializing system real time clock → initializing system general input and output → initializing flash memory drive → initializing flash memory → initializing file system. Where initializing the system interrupt module may be understood as registering all system interrupt modules-14 to-1 as restart interfaces and redirecting the system interrupt vector table to the system interrupt table.

In addition, writing the abnormal reset information into the flash memory may also be understood as unlocking the file system, then opening a file handle of the abnormal reset information, and writing the abnormal reset information into the file system according to clock information of a system real-time clock.

In the embodiment of the application, the initialized minimum system is used for writing the abnormal reset information into the flash memory, and the purpose is not only to activate the flash memory by using less resources so that the flash memory can be in a basic normal operation state, but also to store the abnormal reset information in the flash memory in the operation state, so that the abnormal reset information is ensured not to be lost even under the condition of power failure, and the acquirability of the abnormal reset information during subsequent positioning and solving of the abnormal reset problem is ensured.

The scheme provided by the embodiment of the application is mainly introduced from the perspective of a method. It is to be understood that the above-described exception handling apparatus includes hardware structures and/or software modules for performing the respective functions in order to implement the above-described functions. Those skilled in the art will readily appreciate that the functions described in connection with the embodiments disclosed herein may be implemented as hardware or a combination of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

Described from the perspective of an entity device, the exception handling apparatus may be an MCU chip or other main chip including an SRAM, and may be specifically implemented by one entity device, may also be implemented by multiple entity devices together, and may also be a logic function unit in one entity device, which is not specifically limited in this embodiment of the present application.

For example, the above-described exception handling apparatus may be implemented by the communication device in fig. 5. Fig. 5 is a schematic hardware structure diagram of a communication device according to an embodiment of the present application. The communication device comprises at least one processor 501, a memory 502 and an input device 503.

The processor 501 may be a general purpose central processing unit CPU, microprocessor, application-specific integrated circuit (server IC), or one or more ICs for controlling the execution of programs in accordance with the teachings of the present application. The processor 501 is able to determine whether the abnormal reset is caused by a watchdog or a software program not recognizing the current startup state, and write the abnormal reset information into the flash memory.

The input device 503 may be any device, such as a transceiver, for communicating with other devices or communication networks, such as ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc. An input device 503 may be connected to the processor 501, and the input device 503 may acquire abnormal reset information or the like after the first chip is reset and before the SRAM is initialized.

Memory 502 may be a non-volatile memory such as: NOR flash or NAND flash, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 502 may be separate or may be connected to the processor 501. The memory 502 may also be integrated with the processor 501. The memory 502 can store exception reset information.

The memory 502 is used for storing computer-executable instructions for executing the present application, and is controlled by the processor 501 for execution. The processor 501 is configured to execute the computer-executable instructions stored in the memory 502, so as to implement the exception reset processing method provided by the above-described method embodiment of the present application.

In a possible implementation manner, the computer execution instruction in the embodiment of the present application may also be referred to as an application program code, which is not specifically limited in the embodiment of the present application.

In particular implementations, processor 501 may include one or more CPUs such as CPU0 and CPU1 in fig. 5 as an example.

From the perspective of functional units, the present application may divide the functional units of the exception handling apparatus according to the above method embodiments, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one functional unit. The integrated functional unit can be realized in a form of hardware or a form of software functional unit.

For example, in a case where each functional unit is divided in an integrated manner, fig. 6 shows a schematic structural diagram of an exception handling apparatus provided in an embodiment of the present application. As shown in fig. 6, an embodiment of an exception handling apparatus 60 of the present application may include:

an obtaining unit 601, configured to obtain abnormal reset information after the first chip is reset and before the SRAM is initialized;

a writing unit 602, configured to write the abnormal reset information into a flash memory through an initialized minimum system, where the minimum system runs on the first chip and is a necessary running driver of the flash memory.

Optionally, on the basis of the embodiment described in fig. 6, fig. 7 shows a schematic structural diagram of another exception handling device provided in the embodiment of the present application. As shown in fig. 7, the exception handling apparatus 60 of the present application may further include:

a clearing unit 603, configured to clear an exception reset flag, where the exception reset flag is used to indicate that an exception reset occurs in the first chip;

an adjusting unit 604, configured to adjust a state of a system interrupt module, a state of a system real-time clock, a state of a system universal input/output, a state of a flash memory driver, a state of the flash memory, and a state of a file system to corresponding operating states in order to obtain the initialized minimum system, after the abnormal reset flag is cleared, where the system interrupt module, the system real-time clock, and the system universal input/output correspond to the first chip, and the flash memory driver corresponds to the flash memory.

In some embodiments of the present application, the exception handling apparatus 60 further comprises: and the setting unit is used for setting a header mark for the abnormal reset information, and the header mark is used for reflecting the abnormal condition of the abnormal reset information.

In some embodiments of the present application, the obtaining unit 601 includes: the first acquisition module is used for acquiring the running state of the first chip; the first obtaining module is configured to obtain abnormal reset information when the operating state of the first chip reflects that the first chip is reset based on the watchdog and an abnormality occurs.

In some embodiments of the present application, the exception handling apparatus 60 further includes: a judging unit, configured to judge whether a value of a preset flag is changed to a first value before the abnormal reset information is obtained, where the first value is used to indicate that a current start state of the first chip is identified; correspondingly, the obtaining unit 601 includes: and the second acquisition module is used for acquiring abnormal reset information when the value of the preset zone bit is not changed into the first value.

In some embodiments of the present application, the exception handling apparatus 60 further includes: and the resetting unit is used for resetting the first chip again based on a system reset processing function after the abnormal reset information is written into the flash memory.

In some embodiments of the present application, the exception handling apparatus 60 further includes: and the triggering unit is used for triggering a system normal starting process based on a system reset processing function after the abnormal reset information is written into the flash memory. The exception handling apparatus provided in the embodiment of the present application is used to execute the method in the corresponding method embodiment in fig. 2 to 4, so that the embodiment of the present application can be understood by referring to the relevant parts in the corresponding method embodiment in fig. 2 to 4.

In the embodiment of the present application, the exception handling apparatus is presented in a form of dividing each functional unit in an integrated manner. "functional unit" herein may refer to an application-specific integrated circuit (ASIC), a processor and memory that execute one or more software or firmware programs, an integrated logic circuit, and/or other devices that may provide the described functionality. In a simple embodiment, one skilled in the art will appreciate that the display device may take the form shown in FIG. 5.

For example, the processor 501 of fig. 5 may cause the display device to execute the method performed by the exception handling device in the method embodiment corresponding to fig. 2-4 by calling a computer stored in the memory 502 to execute the instructions.

Specifically, the functions/implementation processes of the writing unit 602 in fig. 6, the clearing unit 603, the adjusting unit 604, the setting unit, the judging unit, the resetting unit, and the triggering unit in fig. 7 may be implemented by the processor 501 in fig. 5 invoking a computer execution instruction stored in the memory 502.

The function/implementation process of the acquisition unit 601 in fig. 6 may be implemented by the input device 503 in fig. 5.

In the device of fig. 5, the respective components are communicatively connected, i.e., the processing unit (or processor), the storage unit (or memory) and the transceiving unit (transceiver) communicate with each other via internal connection paths, and control and/or data signals are transmitted. The above method embodiments of the present application may be applied to a processor, or the processor may implement the steps of the above method embodiments. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method embodiments may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The various methods, steps, and logic blocks disclosed in this application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in this application may be directly implemented by a hardware decoding processor, or may be implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor. Although only one processor is shown in the figure, the apparatus may comprise a plurality of processors or a processor may comprise a plurality of processing units. Specifically, the processor may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.

The memory is used for storing computer instructions executed by the processor. The memory may be a non-volatile memory. The non-volatile memory may be a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, or a flash memory. The memory may be independent of the processor, or may be a storage unit in the processor, which is not limited herein. Although only one memory is shown in the figure, the apparatus may comprise a plurality of memories or the memory may comprise a plurality of memory units.

The transceiver is used for enabling the processor to interact with the content of other elements or network elements. Specifically, the transceiver may be a communication interface of the apparatus, a transceiving circuit or a communication unit, and may also be a transceiver. The transceiver may also be a communication interface or transceiving circuitry of the processor. Alternatively, the transceiver may be a transceiver chip. The transceiver may also include a transmitting unit and/or a receiving unit. In one possible implementation, the transceiver may include at least one communication interface. In another possible implementation, the transceiver may also be a unit implemented in software. In embodiments of the application, the processor may interact with other elements or network elements via the transceiver. For example: the processor obtains or receives content from other network elements through the transceiver. If the processor and the transceiver are physically separate components, the processor may interact with other elements of the apparatus without going through the transceiver.

In one possible implementation, the processor, the memory, and the transceiver may be connected to each other by a bus. The bus may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the embodiments of the present application, various illustrations are made for the convenience of understanding. However, these examples are merely examples and are not meant to be the best mode of carrying out the present application.

The above-described embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof, and when implemented using software, may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. The processes or functions according to the embodiments of the present application are generated in whole or in part when the computer-executable instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, e.g., the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium may be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The technical solutions provided by the present application are introduced in detail, and the present application applies specific examples to explain the principles and embodiments of the present application, and the descriptions of the above examples are only used to help understand the method and the core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A processing method for exception resetting is characterized by comprising the following steps:

acquiring abnormal reset information after the first chip is reset and before the SRAM is initialized;

and writing the abnormal reset information into a flash memory through an initialized minimum system, wherein the minimum system runs on the first chip and is a necessary running driver of the flash memory.

2. The method of claim 1, further comprising:

clearing an abnormal reset mark, wherein the abnormal reset mark is used for indicating that the first chip is abnormally reset;

after the abnormal reset mark is cleared, the state of a system interrupt module, the state of a system real-time clock, the state of system universal input and output, the state of a flash memory drive, the state of the flash memory and the state of a file system are adjusted to be corresponding running states in sequence so as to obtain the initialized minimum system, wherein the system interrupt module, the system real-time clock and the system universal input and output correspond to the first chip, and the flash memory drive corresponds to the flash memory.

3. The method of claim 1 or 2, further comprising:

and setting a header mark for the abnormal reset information, wherein the header mark is used for reflecting the abnormal condition of the abnormal reset information.

4. The method according to any one of claims 1-3, wherein the obtaining exception reset information comprises:

acquiring the running state of the first chip;

and when the running state of the first chip reflects that the first chip is reset based on the watchdog and is abnormal, acquiring abnormal reset information.

5. The method according to any of claims 1-3, wherein prior to said obtaining exception reset information, the method further comprises:

judging whether the value of a preset zone bit is changed into a first value, wherein the first value is used for indicating that the current starting state of the first chip is identified;

correspondingly, the acquiring the abnormal reset information includes:

and when the value of the preset zone bit is not changed into the first value, acquiring abnormal reset information.

6. The method of any of claims 1-5, wherein after writing the exception reset information to the flash memory, the method further comprises:

resetting the first chip again based on a system reset handling function.

7. The method of any of claims 1-5, wherein after writing the exception reset information to the flash memory, the method further comprises:

and triggering a normal starting process of the system based on a system resetting processing function.

8. An exception handling apparatus, comprising:

9. The exception handling apparatus according to claim 8, further comprising:

10. The exception handling apparatus according to claim 8 or 9, further comprising:

11. The exception handling apparatus according to any one of claims 8 to 10, wherein the obtaining unit includes:

12. The exception handling apparatus according to any one of claims 8 to 10, further comprising:

correspondingly, the obtaining unit includes:

13. The exception handling apparatus according to any one of claims 8 to 12, further comprising:

14. The exception handling apparatus according to any one of claims 8 to 12, further comprising:

15. An exception handling apparatus, comprising:

a processor, a memory; the processor and the memory are communicated with each other;

the memory is to store instructions;

the processor is configured to execute the instructions in the memory to perform the method of any of claims 1-7.

16. A computer-readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1 to 7.