CN114076851B - 用于检测tsv的寄生电容的测试电路 - Google Patents

用于检测tsv的寄生电容的测试电路 Download PDF

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CN114076851B
CN114076851B CN202110947268.6A CN202110947268A CN114076851B CN 114076851 B CN114076851 B CN 114076851B CN 202110947268 A CN202110947268 A CN 202110947268A CN 114076851 B CN114076851 B CN 114076851B
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node
state
electrical path
coupled
transistor
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CN114076851A (zh
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眞壁晴空
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Micron Technology Inc
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Abstract

本申请案涉及用于检测TSV的寄生电容的测试电路。本文中公开一种包含第一半导体芯片及穿透所述第一半导体芯片的第一TSV的设备。所述第一半导体芯片包含耦合在第一电源与第一节点之间的第一电阻器、耦合在所述第一节点与所述第一TSV之间的开关电路、可操作地耦合到所述第一节点的衬垫电极及可操作地耦合到所述第一节点及所述衬垫电极中的任一者的恒定电流源。

Description

用于检测TSV的寄生电容的测试电路
技术领域
本申请案涉及半导体装置，尤其涉及一种用于检测TSV的寄生电容的测试电路。
背景技术
在一些情况中，在存储器装置(例如，HBM(高带宽存储器))中使用的半导体芯片包含设置为穿透半导体衬底的许多TSV(穿硅通路)。设置在每一半导体芯片上的TSV使用微凸块分别连接到设置在另一半导体芯片上且定位在相同平面位置处的TSV，借此形成穿透多个半导体衬底的信号路径。因为通过TSV传输的信号的信号质量根据TSV的寄生电容而变化，所以需要准确测量TSV的寄生电容的方法。
发明内容
本公开的实施例提供一种设备，所述设备包括：第一半导体芯片；及第一TSV，其穿透所述第一半导体芯片，其中所述第一半导体芯片包含：第一电阻器，其耦合在第一电源与第一节点之间；开关电路，其耦合在所述第一节点与所述第一TSV之间；衬垫电极，其可操作地耦合到所述第一节点；及恒定电流源，其可操作地耦合到所述第一节点及所述衬垫电极中的任一者。
本公开的另一实施例提供一种用于测量TSV电容的方法，所述方法包括：在外部衬垫与电流源之间提供第一电路径；在第一电压节点与所述电流源之间提供第二电路径，所述第二电路径包含具有第一节点的电阻器，所述第二电路径在切断所述第一电路径的情况下耦合所述电流源；在提供所述第二电路径的时间的至少一部分期间在所述第一节点与所述外部衬垫之间提供第三电路径；及响应于切断所述第一及第二电路径且提供所述第三电路径而在所述第一电压节点与第二电压节点之间提供第四电路径，所述第四电路径包含所述电阻器及TSV。
本公开的又另一实施例提供一种设备，所述设备包括：参考电阻器；电容性元件；衬垫电极；开关电路，其耦合在所述参考电阻器与所述电容性元件之间；第一及第二晶体管，其串联耦合在所述衬垫电极与介于所述参考电阻器与所述开关电路之间的第一节点之间；及恒定电流源，其耦合到所述第一与第二晶体管之间的第二节点，其中所述第一及第二晶体管经配置以排他性地进入接通状态。
附图说明
图1是展示根据本申请案的半导体装置的配置的示意图。
图2A是用于说明测试电路和TSV之间的连接关系的电路图。
图2B是图2A中展示的电路的等效电路图。
图3是测试电路的电路图。
图4A是第一校准操作的说明性图。
图4B是第二校准操作的说明性图。
图4C是测量操作的说明性图。
图5是另一测试电路的电路图。
具体实施方式
下文将参考附图详细解释本发明的各种实施例。以下详细描述参考附图，所述附图通过说明的方式展示其中可实践本发明的特定方面及实施例。足够详细地描述这些实施例以使所属领域的技术人员能够实践本发明。可利用其它实施例，且可在不背离本发明的范围的情况下进行结构、逻辑及电改变。本文中所公开的各种实施例不一定是互斥的，因为一些所公开实施例可与一或多个其它所公开实施例组合以形成新实施例。
图1中展示的半导体装置是具有其中八个存储器核心芯片20到27堆叠在接口芯片10上的配置的HBM。然而，本发明可适用的半导体装置不限于HBM。存储器核心芯片20到27各自是其中集成包含存储器单元阵列的存储器核心的半导体芯片。接口芯片10是控制存储器核心芯片20到27的半导体芯片。接口芯片10及存储器核心芯片20到26各自具有设置为穿透半导体衬底的多个TSV 30。所有接口芯片10及存储器核心芯片20到27以面向下方式(即，以具有形成在其上的晶体管及布线图案(两者均未展示)的主表面面向下的方式)堆叠。因此，定位在最上层中的存储器核心芯片27中不需要TSV 30。然而，定位在最上层中的存储器核心芯片27可具有TSV 30。设置在存储器核心芯片20到26中的几乎所有TSV 30分别连接到定位在相同平面位置处的前表面TSV衬垫31A。同时，设置在接口芯片10中的大多数TSV 30及设置在接口芯片10上的大多数前表面TSV衬垫31A存在于彼此不同的平面位置处。在设置在接口芯片10及存储器核心芯片20到26中的TSV 30当中，定位在相同平面位置处的TSV 30经由前表面TSV衬垫31A、TSV凸块31B及后表面TSV衬垫31C以级联连接彼此连接。以此方式，形成多个信号路径32。从接口芯片10输出的命令及写入数据经由信号路径32供应到存储器核心芯片20到27。从存储器核心芯片20到27输出的读取数据经由信号路径32供应到接口芯片10。外部端子33设置在接口芯片10上，通过外部端子33执行向/从外部电路的信号传输及接收。
一些TSV 34未耦合到前衬垫31A且因此未耦合到定位在其它芯片的相同平面位置处的TSV 34。
接口芯片10包含用于测量TSV的寄生电容的测试电路40、50及60。测试电路40耦合到构成信号路径32的TSV 30且测试电路50耦合到未被分配微凸块31B的TSV 34。与此相对照，测试电路60未耦合到任何TSV。测试电路50及60也设置在存储器核心芯片20到26中。测试电路40、50及60具有相同电路配置。
如图2A中展示，测试电路40及TSV 30经由开关电路41彼此耦合。TSV 30由设置为穿透半导体衬底的柱形导体制成且具有主要关于半导体衬底的电容分量。TSV 30还具有关于电源线等的电容分量。因此，当通过CTSV表示TSV 30的寄生电容分量时，可通过图2B中展示的等效电路表示图2A中展示的电路。开关电路41具有节点a、b及c且节点a耦合到节点b及c中的任一者。节点a耦合到TSV 30，节点b耦合到测试电路40，且节点c耦合到半导体衬底或接地线。开关电路41在处于节点a及节点b彼此耦合的状态时处于接通状态且在处于节点a及节点c彼此耦合的状态时处于断开状态。测试电路40耦合到衬垫电极42。衬垫电极42是测试器的探针在根据本实施例的半导体装置的测试过程中与其接触的端子。因此，衬垫电极42的平面大小大于前衬垫31A或后衬垫31C。
图3是测试电路40的电路图。如图3中展示，除开关电路41及衬垫电极42以外，测试电路40还包含参考电阻器43、恒定电流源44、控制电路45及晶体管M0到M2。举例来说，参考电阻器43由钨丝制成且耦合在供应电源电势VDD的电源线LV与内部节点N2之间。内部节点N2耦合到开关电路41的节点b。将参考电阻器43的电阻值设置为R0。晶体管M0耦合在内部节点N2与衬垫电极42之间。类似地，晶体管M1及M2串联耦合在内部节点N2与衬垫电极42之间。晶体管M0到M2全都是P沟道MOS晶体管，但本发明不限于此。由控制电路45控制晶体管M0到M2的操作。晶体管M1与晶体管M2之间的耦合点组成内部节点N0。
恒定电流源44耦合在内部节点N0与供应电源电势VSS的电源线LS之间。恒定电流源44包含串联耦合在内部节点N0与电源线LS之间的晶体管46及电阻器47、及运算放大器48。运算放大器48的输出节点耦合到晶体管46的栅极电极，参考电势Vref供应到运算放大器48的非反相输入节点(+)，且运算放大器48的反相输入节点(-)耦合到内部节点N1。因此，内部节点N1的电势基本上匹配参考电势Vref且当电阻器47的电阻值由R2表示时由Vref/R2表示的恒定电流流过晶体管46。然而，因为运算放大器48存在一些特性变动，所以内部节点N1的电势有时无法完全匹配参考电势Vref。
通过第一校准操作、第二校准操作及测量操作执行TSV 30的寄生电容分量CTSV的测量。第一校准操作是测量由恒定电流源44产生的恒定电流的操作。第二校准操作是测量参考电阻器43的电阻值R0的操作。
在第一校准操作中，切断开关电路41，且控制电路45切断晶体管M0及M1且接通晶体管M2，如图4A中展示。因此，恒定电流源44连接到衬垫电极42且内部节点N2与衬垫电极42及恒定电流源44断开连接。当测试器70的探针在此状态下与衬垫电极42接触时，由恒定电流44产生的恒定电流Iref流过衬垫电极42。通过测试器70中的电流计71测量流过衬垫电极42的恒定电流Iref的量。因此，即使在内部节点N1的电势归因于运算放大器48的特性变动而偏移到参考电势Vref+Vamp的值时，也可测量恒定电流Iref的实际量。
在第二校准操作中，切断开关电路41，且控制电路45接通晶体管M0及M1且切断晶体管M2，如图4B中展示。如由第一及第二校准操作展示(对于第一校准操作，晶体管M1切断且晶体管M2接通；对于第二校准操作，晶体管M1接通且晶体管M2切断)，晶体管M1及M2不会同时接通。即，晶体管M1及M2排他性地进入接通状态。在晶体管M0及M1接通且晶体管M2切断的情况下，恒定电流源44连接到内部节点N2且与衬垫电极42断开连接。因此，恒定电流Iref流过参考电流源43且内部节点N2的电平由电源电势VDD的电平、参考电阻器43的电阻值R0及恒定电流Iref的量确定。当测试器70的探针在此状态下与衬垫电极42接触时，通过测试器70中的电压计72测量出现在衬垫电极42处的输出电压Vout的电平。通过下式确定输出电压Vout的电平
Vout＝VDD-R0·Iref。
因此，可通过下式计算参考电阻器43的电阻值R0
R0＝(VDD-Vout)/Iref。
因为电源电势VDD的电平是已知的且已在第一校准操作中测量恒定电流Iref的量，所以在第二校准操作中测量输出电压Vout使能够准确计算参考电阻器43的实际电阻值R0。
在测量操作中，以预定频率f接通及切断开关电路41且控制电路45接通晶体管M0且切断晶体管M1及M2，如图4C中展示。运用此操作，恒定电流源44与内部节点N2及衬垫电极42断开连接，且内部节点N2及衬垫电极42相互连接。在以预定频率f接通/切断开关电路41的情况下，可通过等效电阻R1近似计算TSV 30的寄生电容分量CTSV。因此，通过电源电势VDD的电平、参考电阻器43的电阻值R0及等效电阻R1确定出现在衬垫电极42处的输出电压Vout的电平。当测试器70的探针在此状态下与衬垫电极42接触时，通过测试器70中的电压计72测量出现在衬垫电极42处的输出电压Vout的电平。输出电压Vout具有通过下式确定的电平
Vout＝VDD/(1+R0·CTSV·f)。
因此，可通过下式计算TSV 30的寄生电容分量CTSV
CTSV＝(VDD-Vout)/(Vout·R0·f)。
因为电源电势VDD的电平及切换频率f是已知的且已在第二校准操作中测量参考电阻器43的电阻值R0，所以在测量操作中测量输出电压Vout使能够准确测量TSV 30的寄生电容分量CTSV。
以此方式，根据本实施例，即使在参考电阻器43的电阻值R0存在制造变动的情况中，也可通过使测试器70的探针与单个衬垫电极42接触而准确测量TSV 30的寄生电容分量CTSV而无需使用多个衬垫电极42。因此，当上文描述的测试电路40安装在图1中展示的接口芯片10上时，可测量图1中展示的整个信号路径32的寄生电容。当具有与上文描述的测试电路40相同的电路配置的测试电路50安装在图1中展示的接口芯片10或存储器核心芯片20到26上时，可测量TSV 34的一个层的寄生电容。
进一步来说，当图5中展示的测试电路60安装在图1中展示的接口芯片10或存储器核心芯片20到26上时，可测量测试电路60本身的寄生电容。图5中展示的测试电路60与图3中展示的测试电路40的不同之处在于开关电路41的节点a处于断开状态而不耦合到任何TSV。节点a的寄生电容Cp经设计以具有与将节点a耦合到测试电路40及50中的TSV 30或34的导线相同的电容值。当使用具有上文描述的配置的测试电路60来测量测试电路40、50或60本身的寄生电容且从由测试电路40或50测量的寄生电容的值减去由测试电路60测量的寄生电容的值时，可仅更准确地测量作为测量目标的TSV的寄生电容而不包含测试电路40、50或60本身的寄生电容分量。
尽管已在某些优选实施例及实例的上下文中公开本发明，但所属领域的技术人员将理解，本发明超出特定公开的实施例延伸到本发明的其它替代实施例及/或用途及其明显修改及等效物。另外，所属领域的技术人员将基于本公开容易地明白本发明范围内的其它修改。还预期，可对实施例的特定特征及方面进行各种组合或子组合，且其仍落入本发明的范围内。应理解，所公开实施例的各种特征及方面可彼此组合或替代以形成本发明的变化模式。因此，希望本文中公开的本发明的至少一些内容的范围不应受上文描述的特定公开实施例限制。

Claims (20)

1.一种设备，其包括：
第一半导体芯片；及
第一TSV，其穿透所述第一半导体芯片，
其中所述第一半导体芯片包含：
第一电阻器，其耦合在第一电源与第一节点之间；
开关电路，其耦合在所述第一节点与所述第一TSV之间；
衬垫电极，其可操作地耦合到所述第一节点；及
恒定电流源，其可操作地耦合到所述第一节点及所述衬垫电极中的任一者。
2.根据权利要求1所述的设备，其中所述第一半导体芯片进一步包含耦合在所述第一节点与所述恒定电流源之间的第一晶体管。
3.根据权利要求2所述的设备，
其中所述第一晶体管经配置以在第一操作期间进入接通状态且所述开关电路经配置以在第一操作期间进入断开状态，使得校准电压出现在所述衬垫电极处，且
其中所述第一晶体管经配置以在第二操作期间进入断开状态且所述开关电路经配置以在第二操作期间以一定频率进入接通状态及断开状态，使得测量电压出现在所述衬垫电极处。
4.根据权利要求3所述的设备，其中所述第一半导体芯片进一步包含：
第二晶体管，其耦合在所述第一节点与所述衬垫电极之间；及
第三晶体管，其耦合在第二节点与所述衬垫电极之间，其中所述第二节点在所述第一晶体管与所述恒定电流源之间。
5.根据权利要求4所述的设备，其中所述第二及第三晶体管经配置以在所述第一及第二操作期间分别进入接通状态及断开状态。
6.根据权利要求5所述的设备，其中所述第一、第二及第三晶体管经配置以在第三操作期间分别进入断开状态、断开状态及接通状态，使得恒定电流在所述衬垫电极处流动。
7.根据权利要求4所述的设备，其中所述恒定电流源包含：
第四晶体管及第二电阻器，其串联耦合在所述第二节点与第二电源线之间；及
放大器，其具有耦合到所述第四晶体管的控制电极的输出节点、供应有参考电势的第一输入节点及耦合到所述第四晶体管与所述第二电阻器之间的第三节点的第二输入节点。
8.根据权利要求1所述的设备，其进一步包括：
第二半导体芯片，其堆叠在所述第一半导体芯片上；及
第二TSV，其穿透所述第二半导体芯片，
其中所述第一及第二TSV串联耦合。
9.一种用于测量TSV电容的方法，其包括：
在外部衬垫与电流源之间提供第一电路径；
在第一电压节点与所述电流源之间提供第二电路径，所述第二电路径包含具有第一节点的电阻器，所述第二电路径在切断所述第一电路径的情况下耦合所述电流源；
在提供所述第二电路径的时间的至少一部分期间在所述第一节点与所述外部衬垫之间提供第三电路径；及
响应于切断所述第一及第二电路径且提供所述第三电路径而在所述第一电压节点与第二电压节点之间提供第四电路径，所述第四电路径包含所述电阻器及TSV。
10.根据权利要求9所述的方法，其中所述第四电路径包含耦合在所述电阻器与所述TSV之间的开关电路。
11.根据权利要求10所述的方法，其进一步包括伴随提供所述第四电路径以预定频率接通及断开所述开关电路。
12.根据权利要求11所述的方法，其进一步包括伴随提供所述第四电路径测量所述外部衬垫的电势。
13.根据权利要求10所述的方法，其中所述开关电路经配置以伴随提供所述第一电路径进入断开状态。
14.根据权利要求10所述的方法，其中所述开关电路经配置以伴随提供所述第二电路径进入断开状态。
15.根据权利要求9所述的方法，
其中所述第一电路径包含耦合在所述外部衬垫与所述电流源之间的第一晶体管，
其中所述第一晶体管在提供所述第一电路径时进入接通状态，且
其中所述第一晶体管在切断所述第一电路径时进入断开状态。
16.根据权利要求9所述的方法，
其中所述第二电路径包含耦合在所述第一电压节点与所述电流源之间的第二晶体管，
其中所述第二晶体管在提供所述第二电路径时进入接通状态，且
其中所述第二晶体管在切断所述第二电路径时进入断开状态。
17.根据权利要求9所述的方法，
其中所述第三电路径包含耦合在所述第一节点与所述外部衬垫之间的第三晶体管，
其中所述第三晶体管在提供所述第三电路径时进入接通状态，且
其中所述第三晶体管在切断所述第三电路径时进入断开状态。
18.一种设备，其包括：
参考电阻器；
电容性元件；
衬垫电极；
开关电路，其耦合在所述参考电阻器与所述电容性元件之间；
第一及第二晶体管，其串联耦合在所述衬垫电极与介于所述参考电阻器与所述开关电路之间的第一节点之间；及
恒定电流源，其耦合到所述第一与第二晶体管之间的第二节点，
其中所述第一及第二晶体管经配置以排他性地进入接通状态。
19.根据权利要求18所述的设备，其进一步包括耦合在所述衬垫电极与所述第一节点之间的第三晶体管，
其中所述第三晶体管经配置以在测量操作中进入接通状态，且
其中所述第一及第二晶体管经配置以在所述测量操作中进入断开状态。
20.根据权利要求19所述的设备，
其中所述第一、第二及第三晶体管经配置以在第一校准操作中分别进入断开状态、接通状态及断开状态，且
其中所述第一、第二及第三晶体管经配置以在第二校准操作中分别进入接通状态、断开状态及接通状态。
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