CN114068684B

CN114068684B - Semiconductor memory device and method for manufacturing semiconductor memory device

Info

Publication number: CN114068684B
Application number: CN202110361218.XA
Authority: CN
Inventors: 李南宰
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2020-08-06
Filing date: 2021-04-02
Publication date: 2024-03-08
Anticipated expiration: 2041-04-02
Also published as: CN114068684A; US20220045045A1; CN118039677A; US12027511B2; KR20220018343A

Abstract

The present disclosure provides a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the engagement structure; a first gate contact structure including a first vertical portion penetrating the bonding structure and a first horizontal portion intersecting the first vertical portion and extending from the first vertical portion; and a first gate conductive pattern contacting the sidewall of the first horizontal portion and spaced apart from the first vertical portion, the first gate conductive pattern extending to surround the channel structure.

Description

Semiconductor memory device and method for manufacturing semiconductor memory device

Technical Field

The present disclosure relates generally to a semiconductor memory device and a method of manufacturing a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing a three-dimensional semiconductor memory device.

Background

The semiconductor memory device includes a memory cell array and peripheral circuits connected to the memory cell array. The memory cell array includes a plurality of memory cells capable of storing data, and the peripheral circuits are configured to perform various operations.

In order to increase the integration level of the semiconductor memory device, the memory cell array may include memory cells three-dimensionally arranged over peripheral circuits.

Disclosure of Invention

In one embodiment of the present disclosure, there may be provided a semiconductor memory device including: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the engagement structure; a first gate contact structure including a first vertical portion penetrating the bonding structure and a first horizontal portion intersecting the first vertical portion and extending from the first vertical portion; and a first gate conductive pattern in contact with a sidewall of the first horizontal portion and spaced apart from the first vertical portion, wherein the first gate conductive pattern extends to surround the channel structure.

In one embodiment of the present disclosure, there may be provided a semiconductor memory device including: a peripheral circuit layer including a first region and a second region; a bonding structure disposed on the peripheral circuit layer; a unit laminated structure overlapping the first region, wherein the unit laminated structure includes gate conductive patterns and interlayer insulating layers alternately laminated on the bonding structure; a channel structure penetrating the cell stack structure; a dummy laminated structure overlapping the second region, wherein the dummy laminated structure includes first material layers and second material layers alternately laminated on the bonding structure; a vertical contact structure penetrating the dummy laminated structure and the bonding structure to be connected to the peripheral circuit layer; and a dummy spacer insulating layer surrounding the sidewalls of the vertical contact structure, wherein the dummy spacer insulating layer includes a columnar portion extending along the sidewalls of the vertical contact structure, and a protruding portion protruding from the columnar portion toward the second material layer to fill a space between the first material layers.

In one embodiment of the present disclosure, a method of manufacturing a semiconductor memory device may be provided, the method including: forming a step structure on the sacrificial substrate, wherein the step structure includes first material layers stacked to be spaced apart from each other and surrounding a channel structure, second material layers surrounding the channel structure between the first material layers, and gap filling patterns disposed on sidewalls of the second material layers between the first material layers; forming a gap filling insulating layer covering the step structure; forming a contact hole intersecting the gap-fill pattern, wherein the contact hole penetrates the gap-fill insulating layer, the first material layer, and the second material layer; forming a spacer insulating layer on the sidewalls of the contact hole; forming a sacrificial post to fill a central region of the contact hole that passes through the spacer insulating layer opening; forming a first insulating layer extending to overlap the sacrificial post and the gap-fill insulating layer; bonding the first insulating layer to a second insulating layer covering the peripheral circuit layer; and replacing the sacrificial post and the gap fill pattern with a gate contact structure penetrating the first insulating layer and the second insulating layer.

In one embodiment of the present disclosure, a method of manufacturing a semiconductor memory device may be provided, the method including: forming a laminated structure on the sacrificial substrate, wherein the laminated structure includes a first material layer and a second material layer alternately laminated; forming a contact hole penetrating the laminated structure; etching a portion of each of the second material layers through the contact holes to open a gap between the first material layers; forming a spacer insulating layer filling the gap, wherein the spacer insulating layer extends along the side wall of the contact hole; forming a sacrificial post to fill a central region of the contact hole that passes through the spacer insulating layer opening; forming a first insulating layer extending to overlap the sacrificial post and the stacked structure; bonding a second insulating layer covering the peripheral circuit layer to the first insulating layer; and replacing the sacrificial post with a vertical contact structure penetrating the first insulating layer and the second insulating layer.

Drawings

Examples of embodiments will now be described below with reference to the drawings, however, these examples may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the size may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements may also be present. Like numbers refer to like elements throughout.

Fig. 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

Fig. 2A, 2B, and 2C are views illustrating peripheral circuit layers according to an embodiment of the present disclosure.

Fig. 3A and 3B are perspective views illustrating components overlapping a first region of a peripheral circuit layer according to embodiments of the present disclosure.

Fig. 4 is a circuit diagram of a memory cell array according to an embodiment of the present disclosure.

Fig. 5 is a plan view illustrating a unit laminated structure according to an embodiment of the present disclosure.

Fig. 6 is a cross-sectional view of a semiconductor memory device taken along line A-A' shown in fig. 5 according to an embodiment of the present disclosure.

Fig. 7 is a perspective view illustrating the first and second gate conductive patterns and the first and second gate contact structures shown in fig. 6.

Fig. 8A and 8B are perspective views illustrating the first and second gate interval insulating layers shown in fig. 6.

Fig. 9 is a cross-sectional view illustrating a dummy stacked structure and a vertical contact structure according to an embodiment of the present disclosure.

Fig. 10A, 10B, 10C, 10D, 10E, and 10F are process cross-sectional views illustrating a process of forming a step structure according to an embodiment of the present disclosure.

Fig. 11 is a perspective view showing a part of the step structure shown in fig. 10F.

Fig. 12 is a cross-sectional view illustrating a dummy stacked structure according to an embodiment of the present disclosure.

Fig. 13A, 13B, 14A and 14B are process cross-sectional views illustrating a process of forming a contact hole according to an embodiment of the present disclosure.

Fig. 15 is a perspective view illustrating a portion of the first contact hole shown in fig. 14A.

Fig. 16A, 16B, 17A and 17B are process cross-sectional views illustrating a process of forming a spacer insulating layer and a sacrificial post according to an embodiment of the present disclosure.

Fig. 18A and 18B are process cross-sectional views illustrating a process of forming a unit laminated structure according to an embodiment of the present disclosure.

Fig. 19 is a perspective view showing a part of the unit laminated structure shown in fig. 18B.

Fig. 20 is a cross-sectional view showing a structure formed on a second region of the sacrificial substrate when the unit laminated structure shown in fig. 19 is formed.

Fig. 21A and 21B are sectional views illustrating a bonding process according to an embodiment of the present disclosure.

Fig. 22A and 22B are cross-sectional views illustrating a process of exposing a sacrificial post according to an embodiment of the present disclosure.

Fig. 23A and 23B are cross-sectional views illustrating a process of exposing the conductive pad.

Fig. 24 is a perspective view illustrating a portion of the first vertical hole shown in fig. 23A.

Fig. 25 and 26 are perspective views illustrating a process of forming a gate contact structure according to an embodiment of the present disclosure.

Fig. 27A and 27B are cross-sectional views illustrating a gate contact structure and a vertical contact structure according to an embodiment of the present disclosure.

Fig. 28A and 28B are cross-sectional views illustrating embodiments of subsequent processes that continue after forming gate contact structures and vertical contact structures.

Fig. 29 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

Fig. 30 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure.

Detailed Description

The specific structural and functional descriptions disclosed herein are merely illustrative of the embodiments for purposes of describing the concepts according to the disclosure. Embodiments of the concepts according to the present disclosure may be embodied in various forms and should not be construed as limited to the specific embodiments set forth herein.

Hereinafter, the terms "first" and "second" are used to distinguish one component from another. These terms may be used to describe various elements, but the elements are not limited by these terms. Like numbers refer to like elements throughout. Accordingly, even if a certain reference numeral is not mentioned or described with reference to a certain drawing, the reference numeral may be mentioned or described with reference to another drawing. Further, even if a certain reference numeral is not shown in a certain drawing, the reference numeral may be mentioned or described with reference to another drawing.

Embodiments provide a semiconductor memory device capable of improving operational reliability and a method of manufacturing the semiconductor memory device.

Fig. 1 is a block diagram illustrating a semiconductor memory device 50 according to an embodiment of the present disclosure.

Referring to fig. 1, a semiconductor memory device 50 may include a peripheral circuit 40 and a memory cell array 10.

The peripheral circuit 40 may be configured to perform a program operation of storing data in the memory cell array 10, a read operation of outputting data stored in the memory cell array 10, and an erase operation of erasing data stored in the memory cell array 10. In one embodiment, the peripheral circuit 40 may include an input/output circuit 21, a control circuit 23, a voltage generating circuit 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

The memory cell array 10 may include a plurality of memory cells storing data. The memory cells may be arranged in three dimensions. The memory cell array 10 may be connected to at least one drain select line DSL, a plurality of word lines WL, at least one source select line SSL, a plurality of bit lines BL, and a common source line CSL.

The input/output circuit 21 may transmit the command CMD and the address ADD transmitted from an external device (e.g., a memory controller) of the semiconductor memory device 50 to the control circuit 23. The input/output circuit 21 may exchange DATA with an external device and the column decoder 35.

The control circuit 23 may output an operation signal op_s, a row address RADD, a source line control signal sl_s, a page buffer control signal pb_s, and a column address CADD in response to the command CMD and the address ADD.

The voltage generating circuit 31 may generate various operation voltages Vop for a program operation, a read operation, and an erase operation in response to the operation signal op_s. The voltage generating circuit 31 may selectively discharge the drain select line DSL, the word line WL, and the source select line SSL in response to the operation signal op_s.

The row decoder 33 may transmit the operation voltage Vop to the drain select line DSL, the word line WL, and the source select line SSL in response to the row address RADD.

The column decoder 35 may transmit the DATA input from the input/output circuit 21 to the page buffer 37 in response to the column address CADD, or may transmit the DATA stored in the page buffer 37 to the input/output circuit 21. The column decoder 35 may exchange DATA with the input/output circuit 21 through a column line CL. The column decoder 35 may exchange DATA with the page buffer 37 through the DATA line DL.

The page buffer 37 may temporarily store the DATA received through the bit line BL in response to the page buffer control signal pb_s. The page buffer 37 may sense the voltage or current of the bit line BL in a read operation.

The source line driver 39 may control a voltage applied to the common source line CSL in response to the source line control signal sl_s.

In order to improve the integration of the semiconductor memory device, the cell stack structure of the memory cell array 10 may overlap with a peripheral circuit layer including the peripheral circuit 40.

Fig. 2A, 2B, and 2C are views illustrating the peripheral circuit layer 45 according to an embodiment of the present disclosure.

Referring to fig. 2A, 2B, and 2C, the peripheral circuit layer 45 may extend in the first direction X and the second direction Y. The peripheral circuit layer 45 may include a first region overlapping the cell stack structure ST [ C ] and a second region overlapping the dummy stack structure ST [ D ]. Each of the cell stack structure ST [ C ] and the dummy stack structure ST [ D ] may include a plurality of layers stacked in the third direction Z over the peripheral circuit layer 45. The first direction X, the second direction Y, and the third direction Z may be directions in which X-axis, Y-axis, and Z-axis of the XYZ coordinate system face.

In one embodiment, the dummy stack structure ST [ D ] may be adjacent to the cell stack structure ST [ C ] in the first direction X, as shown in fig. 2A. In one embodiment, the dummy stack structure ST [ D ] may be adjacent to the cell stack structure ST [ C ] in the second direction Y, as shown in fig. 2B. In one embodiment, the dummy stack structure ST [ D ] may be surrounded by the cell stack structure ST [ C ], as shown in fig. 2C.

Fig. 3A and 3B are perspective views illustrating components overlapping the first region AR1 of the peripheral circuit layer 45 according to an embodiment of the present disclosure.

Referring to fig. 3A and 3B, the common source line CSL and the plurality of bit lines BL may overlap the first region AR1 of the peripheral circuit layer 45. The cell stack structure ST C may be disposed between the common source line CSL and the plurality of bit lines BL.

Referring to fig. 3A, in one embodiment, a common source line CSL may be disposed between the cell stack structure ST [ C ] and the peripheral circuit layer 45, and a bit line BL may overlap the common source line CSL with the cell stack structure ST [ C ] interposed therebetween.

Referring to fig. 3B, in one embodiment, a bit line BL may be disposed between the cell stack structure ST [ C ] and the peripheral circuit layer 45, and a common source line CSL may overlap the bit line BL with the cell stack structure ST [ C ] interposed between the common source line CSL and the bit line BL.

Referring to fig. 4, the memory cell array may include a plurality of memory cell strings CS respectively connected to a plurality of bit lines BL. The plurality of memory cell strings CS may be commonly connected to a common source line CSL.

Each memory cell string CS may include at least one source selection transistor SST, a plurality of memory cells MC, and at least one drain selection transistor DST stacked between a common source line CSL and a bit line BL.

The source select transistor SST may control electrical connection between the plurality of memory cells MC and the common source line CSL. The drain select transistor DST may control electrical connection between the plurality of memory cells MC and the bit line BL.

One source selection transistor SST may be disposed between the common source line CSL and the plurality of memory cells MC, or two or more source selection transistors connected in series may be disposed between the common source line CSL and the plurality of memory cells MC. One drain select transistor DST may be disposed between the bit line BL and the plurality of memory cells MC, or two or more drain select transistors connected in series may be disposed between the bit line BL and the plurality of memory cells MC.

Each memory cell MC may be connected to each word line WL, respectively. The operation of the memory cell MC may be controlled by a cell gate signal applied to the word line WL. The source select transistor SST may be connected to a source select line SSL. The operation of the source select transistor SST may be controlled by a source gate signal applied to a source select line SSL. The drain select line DST may be connected to the drain select line DSL. The operation of the drain select transistor DST may be controlled by a drain gate signal applied to the drain select line DSL.

The source select line SSL, the drain select line DSL, and the word line WL may be connected to a block select circuit BSC. The block selection circuit BSC may be included in the row decoder 33 described with reference to fig. 1. In one embodiment, the block selection circuit BSC may include pass transistors PT connected to the source selection line SSL, the drain selection line DSL, and the word line WL, respectively. A gate of the pass transistor PT may be connected to the block select line BSEL. The transfer transistor PT may transfer voltages applied to the global lines GSSL, GWL, and GDSL to the source, drain, and word lines SSL, DSL, and WL in response to a block selection signal applied to the block selection line BSEL.

The block selection circuit BSC may be connected to the source selection line SSL, the drain selection line DSL, and the word line WL via the gate contact structure GCT.

Fig. 5 is a plan view showing a unit laminated structure ST [ C ] according to an embodiment of the present disclosure.

Referring to fig. 5, the unit laminated structures ST [ C ] may be isolated from each other by the slits SI. As shown in fig. 6, each cell stack structure ST [ C ] may include a gate conductive pattern GCP. As shown in fig. 6, the gate conductive patterns GCP may be stacked to be spaced apart from each other in the third direction Z. Each of the cell stack structures ST C may surround the channel structure CH extending in the third direction Z. Fig. 5 shows a single gate conductive pattern GCP of each cell stack structure ST [ C ].

The sidewalls of the channel structure CH may be surrounded by the memory layer ML.

Each gate conductive pattern GCP may extend along the first direction X and the second direction Y.

Each gate conductive pattern GCP may be in contact with one gate contact structure GCT. Each gate contact structure GCT may include a vertical portion VP and a horizontal portion HP extending from the vertical portion VP.

The vertical portion VP may extend in the third direction Z. A gap G may be defined between the vertical portion VP of the gate contact structure GCT and the gate conductive pattern GCP. In other words, the vertical portion VP of the gate contact structure GCT may be spaced apart from the gate conductive pattern GCP by a gap G. Each gap G may be filled with the gate interval insulating layer 181A.

The horizontal portion HP may be disposed at the same height (level) as one gate conductive pattern GCP. The horizontal portion HP may extend from the vertical portion VP and penetrate the gate interval insulating layer 181A. The horizontal portion HP may extend parallel to sidewalls of the gate conductive pattern GCP disposed at the same height as the horizontal portion HP. The sidewalls 180 of the horizontal portion HP may contact the gate conductive pattern GCP disposed at the same height as the horizontal portion HP. The horizontal portion HP may be in contact with the gap-filling insulating layer 123. The horizontal portion HP may be disposed between the gap-filling insulating layer 123 and the gate conductive pattern GCP disposed at the same height as the horizontal portion HP. The gate interval insulating layer 181A may extend between the gap filling insulating layer 123 and the vertical portion VP.

Referring to fig. 6, the semiconductor memory device may include a peripheral circuit layer 45, a bonding structure 90 disposed on the peripheral circuit layer 45, a channel structure CH disposed on the bonding structure 90, a cell stack structure ST [ C ] penetrated by the channel structure CH on the bonding structure 90, a memory layer ML disposed between the cell stack structure ST [ C ] and the channel structure CH, and a gate contact structure GCT penetrating the bonding structure 90.

The peripheral circuit layer 45 may include a substrate 101, an interconnect structure 110 disposed on the substrate 101, and a conductive pad 117 connected to the interconnect structure 110. The substrate 101 may include an active region divided by an isolation layer 103. The substrate 101 may include a semiconductor substrate, such as a silicon substrate or a germanium substrate. Impurity regions 105A and 105B doped with at least one of a p-type impurity and an n-type impurity may be defined in the active region of the substrate 101. The impurity regions 105A and 105B may include the impurity region 105A serving as a junction of the transfer transistor PT shown in fig. 4. Each interconnect structure 110 may include conductive lines, contact plugs, and contact pads. Each conductive pad 117 may include a conductive barrier layer 113 and a metal layer 115.

The insulating structure 111 may cover the substrate 101 of the peripheral circuit layer 45. Interconnect structure 110 and conductive pad 117 may be buried in insulating structure 111. The insulating structure 111 may include a plurality of insulating layers each having two or more layers.

The bonding structure 90 may be disposed on the insulating structure 111 and the conductive pad 117. The bonding structure 90 may include a first insulating layer 121 and a second insulating layer 119 bonded to face each other. In accordance with the present disclosure, the gate contact structure GCT extends through the bonding structure 90 to contact the conductive pad 117 of the peripheral circuit layer 45. Therefore, in the present disclosure, even if the bonding structure 90 is not formed as a hybrid bonding structure including bonding between insulating layers and bonding between metal layers, but is simply formed as a bonding structure between the first insulating layer 121 and the second insulating layer 119, the peripheral circuit layer 45 may be electrically connected to the gate contact structure GCT.

The memory layer ML may include a tunnel insulating layer 145 surrounding the channel structure CH, a data storage layer 143 surrounding the tunnel insulating layer 145, and a first barrier layer 141 surrounding the data storage layer 143. The data storage layer 143 may be formed of a material layer capable of storing data changed using Fowler-Nordheim (Fowler-Nordheim) tunneling. In one embodiment, data storage layer 143 may include a charge trapping nitride layer. The first blocking insulating layer 141 may include an oxide layer capable of blocking charges. The tunnel insulating layer 145 may include a silicon oxide layer through which charges can tunnel.

The channel structure CH may protrude further in the third direction Z than the cell stack structure ST [ C ]. The channel structure CH may include a channel layer 151 and a core insulating layer 153. The channel layer 151 may surround sidewalls of the core insulating layer 153.

The core insulating layer 153 may include a first end E1 facing the peripheral circuit layer 45 and a second end E2 facing a direction opposite to the direction of the first end E1. The channel layer 151 may extend along a surface of the second end E2 to close the second end E2.

The channel layer 151 may serve as a channel region of a memory cell string. The channel layer 151 may include a semiconductor layer. In one embodiment, the channel layer 151 may include silicon. The channel layer 151 may protrude further toward the peripheral circuit layer 45 than the core insulating layer 153.

The channel layer 151 may be connected to the doped semiconductor layer 137 and the upper conductive layer 170. The doped semiconductor layer 173 may be disposed between the junction structure 90 and the channel structure CH. The doped semiconductor layer 137 may include a first pattern 137A and a second pattern 137B. The upper conductive layer 170 may overlap the doped semiconductor layer 137 with the channel structure CH interposed therebetween. The upper conductor layer 170 may include a conductive barrier layer 173A and a metal layer 175A. The conductive barrier layer 173A may extend along sidewalls and bottom surfaces of the metal layer 175A.

The first pattern 137A may be disposed between the core insulating layer 153 and the second pattern 137B, and the channel layer 151 may extend to surround sidewalls of the first pattern 137A. The second pattern 137B may extend from the first pattern 137A between the bonding structure 90 and the unit laminated structure ST C. In one embodiment, the first pattern 137A and the second pattern 137B may include an n-type doped silicon layer.

The upper conductive layer 170 may be connected to the channel layer 151 via a channel contact structure CCT. The channel contact structure CCT may penetrate the memory layer ML to contact the channel layer 151. The channel contact structure CCT may include a conductive barrier layer 163A and a metal layer 165A. The conductive barrier layer 163A of the channel contact structure CCT may be disposed between the channel layer 151 and the metal layer 165A of the channel contact structure CCT, and may extend along sidewalls of the metal layer 165A. In one embodiment, the conductive barrier layer 163A may include titanium and titanium nitride, which may provide ohmic contacts.

The portion of the channel layer 151 in contact with the doped semiconductor layer 137 and the portion of the channel layer 151 in contact with the channel contact structure CCT may be doped with impurities. In one embodiment, the portion of the channel layer 151 in contact with the doped semiconductor layer 137 and the portion of the channel layer 151 in contact with the channel contact structure CCT may be doped with n-type impurities.

The second pattern 137B of the doped semiconductor layer 137 may serve as a common source line CSL. Although a structure corresponding to the embodiment shown in fig. 3A is shown in fig. 6 as an example, the present disclosure is not limited thereto. In one embodiment, the second pattern 137B of the doped semiconductor layer 137 may be replaced with a conductive pattern for the bit line BL shown in fig. 3B, and the upper conductive layer 170 may be defined as a conductive pattern for the common source line CSL shown in fig. 3B.

The gate conductive pattern GCP and the interlayer insulating layer ILD of the cell stack structure ST [ C ] may surround the channel structure CH and may extend toward the gate contact structure GCT. The gate conductive patterns GCP are disposed between the interlayer insulating layers ILD adjacent to each other in the third direction Z to be insulated from each other by the interlayer insulating layers ILD. The gate conductive pattern GCP may serve as the source select line SSL, the drain select line DSL, and the word line WL described with reference to fig. 4.

The gate conductive pattern GCP may include various conductive materials. In one embodiment, each gate conductive pattern GCP may include a conductive barrier layer 133 and a metal layer 135. The conductive barrier layer 133 may extend along top and bottom surfaces of the metal layer 135 facing the interlayer insulating layer ILD and sidewalls of the metal layer 135 facing the channel structure CH and the gate contact structure GCT.

The second blocking insulating layer 131 may be formed between each gate conductive pattern GCP and the memory layer ML. The second blocking insulating layer 131 may have a higher dielectric constant than the first blocking layer 141. In one embodiment, the second blocking insulating layer 131 may include an aluminum oxide layer. The second barrier layer 131 may extend between the gate conductive pattern GCP and the interlayer insulating layer ILD and between the gate conductive pattern GCP and the gate interval insulating layer 181A. However, the present disclosure is not limited thereto. In one embodiment, the second blocking insulating layer 131 may extend along sidewalls of the memory layer ML.

The unit laminated structure ST C may include a step structure. The gap filling insulating layer 123 may be disposed between the step structure of the unit laminated structure ST C and the bonding structure 90. The gap filling insulating layer 123 may cover the step structure of the cell stack structure ST [ C ], and may extend up to a height at which the common source line CSL is disposed. The oxide layer 122 may be disposed between the gap-filling insulating layer 123 and the bonding structure 90, and may extend to overlap the unit laminated structure ST C.

The respective gate conductive patterns GCP may be connected to the respective gate contact structures GCT, respectively. Each gate contact structure GCT may include a conductive barrier layer 183A and a metal layer 185A.

The vertical portions VP of the gate contact structures GCT may respectively contact the conductive pads 117 overlapping the vertical portions VP, and may extend in the third direction Z to penetrate the bonding structure 90, the oxide layer 122, and the gap-filling insulating layer 123. The vertical portion VP may protrude further in the third direction Z than the unit laminated structure ST [ C ]. The sidewalls of the vertical portions VP may be surrounded by the gate interval insulating layer 181A. The vertical portion VP may protrude further toward the conductive pad 117 than the gate spacer insulating layer 181A.

The gate interval insulating layer 181A may include a bottom surface BS facing the peripheral circuit layer 145 and overlapping the bonding structure 90. The oxide layer 122 may extend between the bottom surface of each gate interval insulating layer 181A and the bonding structure 90. The gate interval insulating layer 181A may protrude toward the gate conductive pattern GCP to fill a gap between the interlayer insulating layers ILD. The gate interval insulating layer 181A may protrude further in the third direction Z than the cell stack structure ST [ C ].

In one embodiment, the first insulation pattern 169A may be disposed on the unit laminated structure ST [ C ]. The first insulating pattern 169A may be formed on a sidewall of the gate interval insulating layer 181A protruding further in the third direction Z than the cell stack structure ST [ C ].

The first upper insulating layer 161 may cover the vertical portion VP, the first insulating pattern 169A, and the unit laminated structure ST [ C ]. The channel contact structure CCT may penetrate the first upper insulating layer 161.

The second upper insulating layer 171 may be disposed on the first upper insulating layer 161. The upper conductive layer 170 serving as the bit line BL may penetrate the second upper insulating layer 171. The second upper insulating layer 171 may be penetrated by a first upper line UL1 spaced apart from the bit line BL, and the first upper line UL1 may overlap some of the gate contact structures GCT. The first upper line UL1 may include the same conductive material as the upper conductive layer 170. In one embodiment, the first upper line UL1 may include a conductive barrier layer 173B and a metal layer 175B.

The gate conductive pattern GCP may be spaced apart from the vertical portion of the gate contact structure GCT by a gate interval insulating layer 181A. As the gate conductive pattern GCP gets farther from the peripheral circuit layer 45, the gate conductive pattern GCP extends farther from the channel structure CH, thereby forming a step structure. As shown in fig. 5, the horizontal portion HP of the gate contact structure GCT may have sidewalls 180 contacting the sidewalls of the gate conductive pattern GCP.

For example, the gate conductive pattern GCP may include a first gate conductive pattern GCP1 on the bonding structure 90 and a second gate conductive pattern GCP2 between the first gate conductive pattern GCP1 and the bonding structure 90. The gate contact structure GCT may include a first gate contact structure GCT1 connected to the first gate conductive pattern GCP1 and a second gate contact structure GCT2 connected to the second gate conductive pattern GCP2.

The first and second gate conductive patterns GCP1 and GCP2 may surround the channel structure CH and may extend toward the first and second gate contact structures GCT1 and GCT 2. The first gate conductive pattern GCP1 may protrude further toward the first gate contact structure GCT1 than the second gate conductive pattern GCP 2. Accordingly, the first gate conductive pattern GCP1 may include a region overlapping the second gate conductive pattern GCP2 and a region not overlapping the second gate conductive pattern GCP 2. In addition, a step structure may be defined by the first gate conductive pattern GCP1 and the second gate conductive pattern GCP 2.

The first gate contact structure GCT1 may face a step structure defined by the first gate conductive pattern GCP1 and the second gate conductive pattern GCP 2. The second gate contact structure GCT2 may be disposed between the second gate conductive pattern GCP2 and the first gate contact structure GCT 1.

The first vertical portion VP1 of the first gate contact structure GCT1 may extend parallel to the channel structure CH. The first vertical portion VP1 may extend in the third direction Z from one conductive pad 117 overlapping the first vertical portion VP1 to penetrate the bonding structure 90, the oxide layer 122, and the gap-filling insulation layer 123. The first horizontal portion HP1 of the first gate contact structure GCT1 may extend from the first vertical portion VP1 at a height at which the first gate conductive pattern GCP1 is disposed, and may extend to intersect the first vertical portion VP 1.

The second vertical portion VP2 of the second gate contact structure GCT2 may extend parallel to the channel structure CH. The second vertical portion VP2 may be disposed between the second gate conductive pattern GCP2 and the first vertical portion VP 1. The second vertical portion VP2 may extend in the third direction Z from another conductive pad 117 overlapping the second vertical portion VP2 to penetrate the bonding structure 90, the oxide layer 122, the gap-fill insulating layer 123, and the first gate conductive pattern GCP1. The second horizontal portion HP2 of the second gate contact structure GCT2 may extend from the second vertical portion VP2 at a height at which the second gate conductive pattern GCP2 is disposed, and may extend to intersect the second vertical portion VP 2.

The interlayer insulating layer ILD may include a first interlayer insulating layer ILD1 and a second interlayer insulating layer ILD2. Each of the first and second interlayer insulating layers ILD1 and ILD2 may surround the channel structure CH and may extend toward the second gate contact structure GCT 2. The first interlayer insulating layer ILD1 may be disposed between the first gate conductive pattern GCP1 and the second gate conductive pattern GCP2, and the second interlayer insulating layer ILD2 may overlap the first interlayer insulating layer ILD1 with the first gate conductive pattern GCP1 interposed therebetween. The second interlayer insulating layer ILD2 may extend further away from the channel structure CH than the first interlayer insulating layer ILD 1.

Each of the gate interval insulating layers 181A may be formed in an asymmetric structure with respect to the horizontal portion HP. For example, each of the gate interval insulating layers 181A may have a first width W1 between the vertical portion VP and the gate conductive pattern GCP, and a second width W2 narrower than the first width W1 between the vertical portion VP and the gap filling insulating layer 123.

In one embodiment, the gate interval insulating layer 181A may include a first gate interval insulating layer 181A1 and a second gate interval insulating layer 181A2. The first gate interval insulating layer 181A1 may surround a sidewall of the first vertical portion VP1 of the first gate contact structure GCT1 and may be penetrated by the first horizontal portion HP1 of the first gate contact structure GCT 1. The second gate interval insulating layer 181A2 may surround a sidewall of the second vertical portion VP2 of the second gate contact structure GCT2 and may be penetrated by the second horizontal portion HP2 of the second gate contact structure GCT 2.

Each of the first and second gate interval insulating layers 181A1 and 181A2 may protrude toward the first gate conductive pattern GCP1 to fill a gap between the first and second interlayer insulating layers ILD1 and ILD 2. The second gate interval insulating layer 181A2 may protrude toward the second gate conductive pattern GCP2 between the second vertical portion VP2 and the second gate conductive pattern GCP 2.

Fig. 7 is a perspective view illustrating the first and second gate conductive patterns GCP1 and GCP2 and the first and second gate contact structures GCT1 and GCT2 illustrated in fig. 6.

Referring to fig. 7, the first vertical portion VP1 of the first gate contact structure GCT1 faces an end portion of the first gate conductive pattern GCP1 and may be spaced apart from the first gate conductive pattern GCP 1. The second vertical portion VP2 of the second gate contact structure GCT2 faces an end of the second gate conductive pattern GCP2 and may be spaced apart from the second gate conductive pattern GCP 2. The second vertical portion VP2 extends in the third direction Z to penetrate the first gate conductive pattern GCP1, and may be spaced apart from the first gate conductive pattern GCP 1. Accordingly, a gap G may be defined between the first vertical portion VP1 and the first gate conductive pattern GCP1, between the second vertical portion VP2 and the first gate conductive pattern GCP1, and between the second vertical portion VP2 and the second gate conductive pattern GCP 2.

The first horizontal portion HP1 of the first gate contact structure GCT1 may extend from the first vertical portion VP1 along a sidewall of the first gate conductive pattern GCP1, and may contact the sidewall of the first gate conductive pattern GCP 1. The second horizontal portion HP2 of the second gate contact structure GCT2 may extend from the second vertical portion VP2 along the sidewall of the second gate conductive pattern GCP2 and may contact the sidewall of the second gate conductive pattern GCP 2.

In one embodiment, the first and second horizontal portions HP1 and HP2 may penetrate the second blocking insulating layer 131. The first and second horizontal portions HP1 and HP2 may each have a sidewall 180. The sidewalls 180 may be in contact with sidewalls of the first gate conductive pattern GCP1 and sidewalls of the second gate conductive pattern GCP2, respectively.

In one embodiment, the conductive barrier layers 183A and 133 may form a common surface at each of the contact surfaces of the first horizontal portion HP1 and the first gate conductive pattern GCP1 and the contact surfaces of the second horizontal portion HP2 and the second gate conductive pattern GCP 2.

Fig. 8A and 8B are perspective views illustrating the first and second gate interval insulating layers 181A1 and 181A2 illustrated in fig. 6.

Referring to fig. 8A and 8B, each of the first and second gate interval insulating layers 181A1 and 181A2 may include a pillar portion PI and one or more protruding portions PR. In one embodiment, each of the gaps G as generally shown in fig. 5 may include not only the pillar portion PI but also a protrusion portion PR that spaces the vertical portion VP from the gate conductive pattern GCP.

Referring to fig. 8A, the pillar portion PI of the first gate interval insulating layer 181A1 may extend in the third direction Z, and a first hole H1 may be defined in a central region of the pillar portion PI. The first hole H1 may extend in the third direction Z, and may be filled with the first vertical portion VP1 shown in fig. 7.

The first gate interval insulating layer 181A1 may include a protrusion portion PR protruding from the pillar portion PI at a first height LV1 at which the first gate conductive pattern GCP1 shown in fig. 7 is disposed. The protruding portion PR of the first gate interval insulating layer 181A1 may fill a gap G between the first vertical portion VP1 and the first gate conductive pattern GCP1 as shown in fig. 7.

The first gate interval insulating layer 181A1 may include a first via portion TH1 penetrating the pillar portion PI at the first height LV 1. The first horizontal portion HP1 shown in fig. 7 may be inserted into the first through hole portion TH1. The first gate interval insulating layer 181A1 may be formed in an asymmetric structure with respect to the first horizontal portion HP1 shown in fig. 7.

Referring to fig. 8B, the pillar portion PI of the second gate interval insulating layer 181A2 may extend in the third direction Z, and a second hole H2 may be defined in a central region of the pillar portion PI. The second hole H2 may extend in the third direction Z and be filled with the second vertical portion VP2 shown in fig. 7.

The second gate interval insulating layer 181A2 may include a protrusion PR protruding from the pillar portion PI at a first height LV1 and a second height LV2 at which the second gate conductive pattern GCP2 shown in fig. 7 is disposed. The protruding portion PR of the second gate interval insulating layer 181A2 may fill a gap G between the second vertical portion VP2 and the first gate conductive pattern GCP1 and between the second vertical portion VP2 and the second gate conductive pattern GCP2 as shown in fig. 7.

The second gate interval insulating layer 181A2 may include a second via portion TH2 penetrating the pillar portion PI at the second height LV 2. The second horizontal portion HP2 shown in fig. 7 may be inserted into the second through hole portion TH2. The second gate interval insulating layer 181A2 may be formed in an asymmetric structure with respect to the second horizontal portion HP2 shown in fig. 7.

Fig. 9 illustrates a cross-sectional view of a dummy stacked structure ST D and a vertical contact structure VCT according to an embodiment of the present disclosure.

Referring to fig. 9, a dummy stacked structure ST [ D ] and a vertical contact structure VCT may be disposed on the second region AR2 of the peripheral circuit layer 45.

The first insulating layer 121 and the second insulating layer 119 may extend to overlap the second region AR2 of the peripheral circuit layer 45. In one embodiment, the transistor TR may be disposed in the second region AR2 of the peripheral circuit layer 145. The transistor TR may be included in one of other circuits of the peripheral circuit 40 other than the row decoder 33 shown in fig. 1. The transistor TR may include a gate insulating layer 107 and a gate electrode 109 stacked on an active region of the substrate 101, and impurity regions 105C formed in the active region on both sides of the gate electrode 109. The active region may be divided by an isolation layer 103. The impurity region 105C may be defined by doping at least one of a p-type impurity and an n-type impurity into the active region of the substrate 101. Some of the interconnect structures 110 may be connected to transistors TR.

The dummy laminated structure ST D may overlap the second region AR2 of the peripheral circuit layer 45. The dummy laminated structure ST D may include the first material layers 91 and the second material layers 93 alternately laminated on the bonding structure 90. The first material layer 91 may be disposed at substantially the same height as the interlayer insulating layer ILD shown in fig. 6, and include the same material as the interlayer insulating layer ILD. The second material layer 93 may be disposed at substantially the same height as the gate conductive pattern GCP shown in fig. 6. In one embodiment, the second material layer 93 may be formed of an insulating material having etching selectivity with respect to the first material layer 91. In one embodiment, the first material layer 91 may include an oxide layer, and the second material layer 93 may include a nitride layer. However, the present disclosure is not limited thereto. In one embodiment, the second material layer 93 may be formed of the same conductive material as each of the gate conductive patterns GCP described with reference to fig. 6.

The gap filling insulating layer 123 and the oxide layer 122 may extend between the dummy stack structure ST [ D ] and the bonding structure 90.

The vertical contact structure VCT may penetrate the dummy laminated structure ST [ D ], the gap-fill insulating layer 123, the oxide layer 122, and the bonding structure 90, and may be connected to the peripheral circuit layer 45. In one embodiment, the vertical contact structure VCT may extend to contact one conductive pad 117 overlapping the vertical contact structure VCT, and may be connected to the transistor TR via the conductive pad 117.

According to one embodiment of the present disclosure, the vertical contact structure VCT may extend to penetrate the bonding structure 90 and may be in direct contact with the conductive pad 117 of the peripheral circuit layer 45. Therefore, in the present disclosure, even when the bonding structure 90 is simplified to a bonding structure between the first insulating layer 121 and the second insulating layer 119, the vertical contact structure VCT can be electrically connected to the peripheral circuit layer 45.

The vertical contact structure VCT may include the same conductive material as the gate contact structure GCT shown in fig. 6. In one embodiment, the vertical contact structure VCT may include a conductive barrier layer 183B and a metal layer 185B.

The vertical contact structure VCT may be connected to the second upper line UL2 via a via plug (via plug) 160. The first upper insulating layer 161 and the second upper insulating layer 171 may extend to cover the vertical contact structure VCT and the dummy stack structure ST [ D ].

The via plug 160 penetrates the first upper insulating layer 161 to connect the vertical contact structure VCT and the second upper line UL2. The via plug 160 may comprise the same conductive material as the channel contact structure shown in fig. 6. In one embodiment, the via plug 160 may include a conductive barrier layer 163B and a metal layer 165B.

The second upper line UL2 may penetrate the second upper insulating layer 171 and may be connected to the via plug 160. The second upper line UL2 may include the same conductive material as the first upper line UL1 shown in fig. 6. In one embodiment, the second upper line UL2 may include a conductive barrier layer 173C and a metal layer 175C.

The sidewalls of the vertical contact structure VCT may be surrounded by the dummy spacer insulating layer 181B. Therefore, even when the second material layer 93 is formed of a conductive material, the vertical contact structure VCT may be insulated from the second material layer 93 by the dummy spacer insulating layer 181B.

The vertical contact structure VCT may extend further toward the peripheral circuit layer 45 than the dummy spacer insulating layer 181B, and may include a sidewall in contact with the bonding structure 90.

The dummy spacer insulating layer 181B may include a dummy pillar portion DPI and a dummy protruding portion DPR. The dummy pillar portion DPI may include a bottom surface DBS that faces the peripheral circuit layer 45 and overlaps the bonding structure 90. The dummy protruding portions DPR may protrude toward the second material layer 93 to fill the space between the first material layers 91.

The dummy columnar portion DPI and the vertical contact structure VCT of the dummy spacer insulating layer 181B may protrude further in the third direction Z than the dummy laminated structure ST [ D ]. In one embodiment, the second insulation pattern 169B may be disposed on the dummy laminated structure ST [ D ]. The second insulating pattern 169B may be formed on a sidewall of the dummy pillar portion DPI that protrudes further than the dummy stacked structure ST [ D ] in the third direction Z.

Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described.

Referring to fig. 10A, a first protective layer 203 and a second protective layer 205 may be sequentially stacked on the sacrificial substrate 201 including the first region A1. The first protective layer 203 may be formed of a material that may serve as a barrier in a subsequent process of removing the sacrificial substrate 201. The second protective layer 205 may be formed of a material different from that of the first protective layer 203. In one embodiment, the sacrificial substrate 201 may include silicon, the first protective layer 203 may include nitride, and the second protective layer 205 may include oxide.

Subsequently, a third protective layer 207 including a first insulating pattern 209A may be formed on the second protective layer 205. Subsequently, the first material layers 211 and the second material layers 213 may be alternately stacked on the third protective layer 207.

The first insulating pattern 209A may be formed of the same material as the second protective layer 205. In one embodiment, the first insulating pattern 209A may include an oxide. The third protective layer 207 may be formed of a material that may be used as an etch stop layer in a subsequent process of etching the first material layer 211 and the second material layer 213. The third protective layer 207 may include silicon.

The second material layer 213 may include a material having etching selectivity with respect to the first material layer 211. The first material layer 211 may be formed of an insulating material capable of insulating between the gate conductive patterns. In one embodiment, the first material layer 211 may include an oxide layer such as silicon oxide, and the second material layer 213 may include a nitride layer such as silicon nitride.

Subsequently, the channel hole 220 penetrating the first material layer 211 and the second material layer 213 may be formed by etching the first material layer 211 and the second material layer 213. The third protective layer 207 may serve as an etch stop layer during an etching process of the first material layer 211 and the second material layer 213 to form the channel hole 220. After the first material layer 211 and the second material layer 213 are etched, the channel hole 220 may extend to the inside of the third protective layer 207 by etching a portion of the third protective layer 207.

Subsequently, the channel hole 220 may be filled with the memory layer 221 and the channel structure 230. The memory layer 221 may be formed by sequentially stacking a first barrier insulating layer 223, a data storage layer 225, and a tunnel insulating layer 227 on the surface of the channel hole 220. The process of forming the channel structure 230 may include a process of forming the channel layer 231 on the surface of the memory layer 221, a process of filling a central region of the channel hole 220 opened by the channel layer 231 with the core insulating layer 233, and a process of removing a portion of the core insulating layer 233 to define a recess region 235 on top of the core insulating layer 233. The channel layer 231 may include a semiconductor layer capable of functioning as a channel region of a memory string.

The channel structure 230 may penetrate the first material layer 211 and the second material layer 213, and may be spaced apart from the first material layer 211 and the second material layer 213 by the memory layer 221.

Referring to fig. 10B, a doped semiconductor layer 241 connected to the channel structure 230 may be formed. The doped semiconductor layer 241 may include a first pattern 241A filling the recess region 235 shown in fig. 10A and a second pattern 241B extending from the first pattern 241A. The second pattern 241B may extend to cover the stacked structure including the first material layer 211 and the second material layer 213. A portion of the doped semiconductor layer 241 may be etched to expose a portion of the stacked structure including the first material layer 211 and the second material layer 213 overlapping the first insulating pattern 209A. In one embodiment, the doped semiconductor layer 241 may be etched into a pattern for the common source line CSL shown in fig. 3.

Referring to fig. 10C, the preliminary structure 210A may be formed by etching the first material layer 211 and the second material layer 213 exposed by the doped semiconductor layer 241. The preliminary step structure 210A may include a plurality of steps ST. Each step ST may include one second material layer 213 and one first material layer 211 on the second material layer 213. The sidewalls of the steps ST may overlap the first insulating patterns 209A, respectively.

Referring to fig. 10D, a portion of each of the second material layers 213 may be selectively etched from the sidewalls of the preliminary step structure 210A. Accordingly, a first gap 215 may be defined between the first material layers 211. Each of the first gaps 215 may overlap each of the first insulating patterns 209A, respectively.

Referring to fig. 10E, an liner layer 243 may be formed along the surface of the doped semiconductor layer 241. The inner liner 243 may be a natural oxide or may be an oxide formed by an oxidation process.

Subsequently, a gap filling layer 245L filling the first gap 215 may be formed. The gap filling layer 245L may include a material having etching resistance with respect to an etching material for selectively removing the second material layer 213. In one embodiment, the second material layer 213 formed of the nitride layer may be selectively removed by using phosphoric acid, and the gap filling layer 245L may include a material having high etching resistance to phosphoric acid as compared to the nitride layer. In one embodiment, the gap filling layer 245L may include any one of silicon, metal, titanium nitride layer (TiN), and silicon carbonitride layer (SiCN).

Referring to fig. 10F, a portion of the gap filling layer 245L may be etched through an etch back process, thereby separating the gap filling layer 245L shown in fig. 10E into the gap filling patterns 245. Thus, the step structure 217 may be defined.

Each gap filling pattern 245 may be respectively remained in each first gap 215 shown in fig. 10E. Each gap filling pattern 245 may overlap each first insulating pattern 209A, respectively.

The doped semiconductor layer 241 may be protected by the liner layer 243 during an etching process for the gap-fill pattern 245. After the gap-fill pattern 245 is formed, the liner layer 243 may be removed.

Fig. 11 is a perspective view showing a part of the step structure 217 shown in fig. 10F.

Referring to fig. 11, the step structure 217 may include first material layers 211 stacked to be spaced apart from each other, second material layers 213 disposed between the first material layers 211, and gap filling patterns 245 disposed on sidewalls of the second material layers 213.

Each of the first material layer 211 and the second material layer 213 may extend in the first direction X and the second direction Y to surround the channel structure 230 and the memory layer 221. The first material layer 211 and the second material layer 213 may extend toward the gap filling pattern 245.

Each gap filling pattern 245 may be in contact with a sidewall of each second material layer 213, respectively, and may extend parallel to the sidewall of the second material layer 213. The gap filling pattern 245 may be disposed between the first material layers 211.

Fig. 12 is a cross-sectional view illustrating a dummy stacked structure 210B according to an embodiment of the present disclosure.

Referring to fig. 12, the sacrificial substrate 210 may include a second region A2 in addition to the first region A1 shown in fig. 10A and 10F. The first protective layer 203, the second protective layer 205, the third protective layer 207, the first material layer 211, and the second material layer 213 may extend onto the second region A2 of the sacrificial substrate 210.

The second insulating pattern 209B may penetrate the third protective layer 207 on the second region A2 of the sacrificial substrate 201. The second insulating pattern 209B may be formed of the same material as the first insulating pattern 209A shown in fig. 10A.

The doped semiconductor layer 241 shown in fig. 10B may be removed on the second region of the sacrificial substrate 201.

The first material layers 211 and the second material layers 213 alternately stacked on the second region A2 of the sacrificial substrate 201 may form a dummy stacked structure 210B. When the processes shown in fig. 10C to 10F are performed, the dummy stack structure 210B may be protected by a mask pattern (not shown). After the process shown in fig. 10F is completed, the mask pattern may be removed.

Referring to fig. 13A and 13B, a gap-filling insulating layer 249 may be formed to cover the step structure 217 and the dummy stack structure 210B. The gap-fill insulating layer 249 may be planarized such that a top surface of the gap-fill insulating layer 249 is at a height at which a top surface of the doped semiconductor layer 241 is disposed. The gap-fill insulating layer 249 may include an oxide.

Subsequently, a mask pattern 251 may be formed on the gap-filling insulating layer 249. The mask pattern 251 may include a first opening OP1 and a second opening OP2. Each of the first openings OP1 may overlap each of the gap filling patterns 245 and each of the first insulating patterns 209A. The second opening OP2 may overlap the second insulation pattern 209B.

Referring to fig. 14A and 14B, the contact holes 253A and 253B may be formed by etching the gap-filling insulating layer 249, the first material layer 211, the second material layer 213, the first insulating pattern 209A, and the second insulating pattern 209B exposed through the first and second openings OP1 and OP2. The contact holes 253A and 253B may penetrate the second protective layer 205, and may expose the first protective layer 203. Since the gap filling pattern 245 is formed of a material having etching selectivity with respect to the gap filling insulating layer 249, the first material layer 211, the second material layer 213, the first insulating pattern 209A, the second insulating pattern 209B, and the second protective layer 205, the gap filling pattern 245 is not removed but may remain.

The contact holes 253A and 253B may include a first contact hole 253A overlapping the first region A1 of the sacrificial substrate 201 and a second contact hole 253B overlapping the second region A2 of the sacrificial substrate 201. The first contact holes 253A may be defined through the first openings OP1, and may expose the gap filling patterns 245, respectively. Each of the first contact holes 253A may penetrate each of the first insulating patterns 209A, respectively. The second contact hole 253B may be defined through the second opening OP2 and may penetrate the second insulation pattern 209B.

Fig. 15 is a perspective view illustrating a portion of the first contact hole 253A illustrated in fig. 14A. Fig. 15 shows only a portion of the gap-filling insulating layer 249 to help understand the structure of each of the first contact holes 253A and the gap-filling patterns 245.

Referring to fig. 15, the first contact hole 253A may overlap the gap filling pattern 245. The first contact hole 253A may extend in a third direction Z intersecting a plane extending in the first direction X and the second direction Y to intersect the gap filling pattern 245. In other words, the first contact hole 253A may penetrate the first material layer 211 and the second material layer 213 disposed under the gap-fill pattern 245.

The first contact hole 253A may include a first sidewall SW1 and a second sidewall SW2. The first sidewall SW1 may form a common surface with the sidewall of the gap-filling insulating layer 249 at one side of the gap-filling pattern 245. The second sidewall SW2 may extend from the first sidewall SW1 and form a common surface with sidewalls of the first material layer 211 and the second material layer 213 at the other side of the gap-fill pattern 245.

Referring to fig. 16A and 16B, a portion of each of the second material layers 213 may be etched through the first contact hole 253A and the second contact hole 253B. Accordingly, gaps 255A and 255B may be defined between the first material layers 211.

The second material layer 213 may be selectively etched. In one embodiment, the second material layer 213 formed of the nitride layer may be selectively etched by phosphoric acid.

The gaps 255A and 255B may include a second gap 255A overlapping the first region A1 of the sacrificial substrate 201 and a third gap 255B overlapping the second region A2 of the sacrificial substrate 201. The second gap 255A may be connected to the first contact hole 253A and may extend between the first material layers 211. The third gap 255B may be connected to the second contact hole 253B and may extend between the first material layers 211.

Referring to fig. 17A and 17B, the spacing insulating layers 261A and 261B may be formed on sidewalls of the first and second contact holes 253A and 253B. The interval insulating layers 261A and 261B may be formed of an insulating material having etching selectivity with respect to the second material layer 213. In one embodiment, each of the spacing insulating layers 261A and 261B may include an oxide layer.

The process of forming the interval insulating layers 261A and 261B may include a process of forming an insulating layer on the surfaces of the first and second contact holes 253A and 253B, and a process of removing a portion of the insulating layer by an etch-back process to expose the surface of the gap filling pattern 245.

The interval insulating layers 261A and 261B may include a gate interval insulating layer 261A disposed on sidewalls of the respective first contact holes 253A and a dummy interval insulating layer 261B disposed on sidewalls of the second contact holes 253B, respectively. The gate interval insulating layer 261A may be open to a central region of the first contact hole 253A, and may extend between the first material layers 211 to fill the second gap 255A. The dummy spacer insulating layer 261B may be open to a central region of the second contact hole 253B, and may extend between the first material layers 211 to fill the third gap 255B.

Subsequently, sacrificial columns 263A and 263B may be formed. The sacrificial columns 263A and 263B may be formed of a material having etching selectivity with respect to the gate interval insulating layer 261A and the dummy interval insulating layer 261B. In one embodiment, the sacrificial columns 263A and 263B may comprise at least one of silicon, metal, titanium nitride layer (TiN), and silicon carbonitride layer (SiCN). The sacrificial columns 263A and 263B may be formed of the same material as the gap-fill pattern 245.

The sacrificial columns 263A and 263B may comprise a first sacrificial column 263A and a second sacrificial column 263B. The first sacrificial post 263A may be formed to fill a central region of the first contact hole 253A that is opened through the gate interval insulating layer 261A. Each first sacrificial post 263A may be connected to each gap-fill pattern 245, respectively. The second sacrificial post 263B may be formed to fill a central region of the second contact hole 253B that is opened through the dummy spacer insulating layer 261B.

Referring to fig. 18A, an oxide layer 265 may be formed on the gap-filling insulating layer 249 penetrated by the first sacrificial post 263A and the first spacing insulating layer 261A. The oxide layer 265 may extend to cover the doped semiconductor layer 241. Subsequently, slits may be formed by etching the first and second material layers 211 and 265 overlapping the first region A1 of the sacrificial substrate 201. The slit may correspond to the slit SI shown in fig. 5.

Subsequently, the second material layer overlapping the first region A1 of the sacrificial substrate 201 may be selectively removed through the slit. Accordingly, the horizontal space 267 may be exposed between the first material layers 211 overlapping the first region A1 of the sacrificial substrate 201.

Subsequently, a second blocking insulating layer 269 may be formed on the surface of each of the horizontal spaces 267. In one embodiment, the second blocking insulating layer 269 may include an aluminum oxide layer. However, the present disclosure is not limited thereto. In one embodiment, the second blocking insulating layer 269 may be excluded from the horizontal space 267 and may be formed on the surface of the channel hole 220 before the first blocking insulating layer 223 shown in fig. 10A is formed.

Referring to fig. 18B, the horizontal space 267 shown in fig. 18A may be filled with a gate conductive pattern 271G. Thus, the unit laminated structure 270C may be formed. The cell stack structure 270C may include the first material layer 211 and the gate conductive pattern 271G surrounding the channel structure 230 and alternately stacked on the first region A1 of the sacrificial substrate 201.

In one embodiment, the process of forming the gate conductive pattern 271G may include a process of forming a conductive barrier layer 273 on the second blocking insulating layer 269, a process of forming a metal layer 275 on the conductive barrier layer 273 to fill the horizontal space 267 shown in fig. 18A, and a process of separating the conductive barrier layer 273 and the metal layer 275 into the gate conductive pattern 271G.

The gate conductive pattern 271G of the present disclosure is not limited to the embodiment including the conductive barrier layer 273 and the metal layer 275, and the conductive material of the gate conductive pattern 271G may be various.

Fig. 19 is a perspective view showing a part of the unit laminated structure 270C shown in fig. 18B. Fig. 19 shows only a portion of the gap-fill insulating layer 249 to aid in understanding the structure of each of the first sacrificial post 263A, the first spacer insulating layer 261A, and the gap-fill pattern 245.

Referring to fig. 19, the cell stack structure 270 may include gate conductive patterns 271G spaced apart from each other by the first material layer 211. The gate conductive pattern 271G may surround the channel structure 230 and the memory layer 221, and may extend toward the first sacrificial post 263A and the gap-fill pattern 245.

The gate conductive pattern 271G may be spaced apart from the first sacrificial post 263A by a gate interval insulating layer 261A.

In one embodiment, the second blocking insulating layer 269 may extend between the gate conductive pattern 271G and the gap filling pattern 245. In one embodiment, the conductive barrier layer 273 of each gate conductive pattern 271G may extend between the gap-fill pattern 245 and the metal layer 275.

Fig. 20 is a cross-sectional view showing a structure formed on the second region A2 of the sacrificial substrate 201 when the unit laminated structure 270C shown in fig. 19 is formed.

Referring to fig. 20, the oxide layer 265 shown in fig. 18A may extend to overlap the second region A2 of the sacrificial substrate 201. In other words, the oxide layer 265 may overlap the dummy stack structure 210B. When the second material layer overlapping the first region of the sacrificial substrate 201 is replaced with the gate conductive pattern, the second material layer 211 of the dummy stack structure 210B is not removed but may remain.

The shape of the slit SI shown in fig. 5 may be variously designed to replace only the second material layer overlapping the first region of the sacrificial substrate 201 with the gate conductive pattern.

Referring to fig. 21A and 21B, a first insulating layer 281 may be formed on the oxide layer 265 before performing the bonding process. The first insulating layer 281 may extend to overlap the cell stack structure 270C, the dummy stack structure 210B, the first sacrificial post 263A, and the second sacrificial post 263B.

The first insulating layer 281 may be bonded to the second insulating layer 321 covering the peripheral circuit layer 300 through a bonding process. The peripheral circuit layer 300 covered by the second insulating layer 321 may be disposed before the bonding process is performed.

As described with reference to fig. 6 and 9, the peripheral circuit layer 300 may include: a substrate 301 including an isolation layer 303 and impurity regions 305A, 305B, and 305C; a gate insulating layer 307 and a gate electrode 309 stacked on the substrate 301; an interconnect structure 310; and conductive pads 317. The gate electrode 309, the interconnect structure 310, and the conductive pad 317 may be buried in an insulating structure 311 formed on the substrate 301. The second insulating layer 321 may be disposed on the insulating structure 311 and may extend to cover the conductive pads 317.

The first insulating layer 281 and the second insulating layer 321 may be formed of various dielectrics. In one embodiment, each of the first insulating layer 281 and the second insulating layer 321 may include an oxide layer. The first insulating layer 281 and the second insulating layer 321 may define a bonding structure in which dielectric layers are bonded together.

Fig. 22A and 22B are cross-sectional views illustrating a process of exposing sacrificial columns 263A and 263B according to an embodiment of the present disclosure.

Referring to fig. 22A and 22B, after the bonding process, the sacrificial substrate 201 shown in fig. 21A and 21B may be removed. When the sacrificial substrate 201 is removed, the first sacrificial post 263A and the second sacrificial post 263B may be protected by the first protective layer 203 shown in fig. 21A and 21B.

Subsequently, the first protective layer 203 shown in fig. 21A and 21B may be removed, thereby exposing the first sacrificial post 263A and the second sacrificial post 263B. In one embodiment, the first protective layer 203 may be removed by performing a planarization process, thereby exposing the first sacrificial post 263A and the second sacrificial post 263B.

Fig. 23A and 23B are sectional views showing a process of exposing the conductive pad 317.

Referring to fig. 23A and 23B, the gate interval insulating layer 261A and the dummy interval insulating layer 261B may be exposed by selectively removing the first sacrificial post 263A and the second sacrificial post 263B shown in fig. 22A and 22B. The gap fill pattern 245 shown in fig. 22A may be removed by etching material for removing the first sacrificial post 263A. Upon removal of the first sacrificial post 263A and the second sacrificial post 263B, the third protective layer 207 may be protected by the second protective layer 205 shown in fig. 22A and 22B.

Subsequently, vertical holes 291A and 291B exposing the conductive pads 317 may be formed by etching the oxide layer 265, the first insulating layer 281, and the second insulating layer 321 exposed by removing portions of the first sacrificial post 263A and the second sacrificial post 263B shown in fig. 22A and 22B therein. In the process of forming the vertical holes 291A and 291B, the second protective layer shown in fig. 22A and 22B may be removed, and the third protective layer 207 may be exposed.

The vertical holes 291A and 291B may include a first vertical hole 291A having a sidewall defined by the gate interval insulating layer 261A and a second vertical hole 291B having a sidewall defined by the dummy interval insulating layer 261B.

Fig. 24 is a perspective view illustrating a portion of the first vertical hole 291A illustrated in fig. 23A. Fig. 24 shows only a portion of the gap-filling insulating layer 249 to assist in understanding the structure of the via portion 293.

Referring to fig. 24, the first vertical hole 291A may be surrounded by a gate interval insulating layer 261A. The first vertical hole 291A may be connected to the first gap 215 through a via portion 293 penetrating the gate interval insulating layer 261A.

When the gap filling pattern 245 shown in fig. 22A is removed, the first gap 215 and the via portion 293 may be opened. As described with reference to fig. 10D, the first gap 215 is a region defined between the first material layers 211. The second blocking insulating layer 269 or the gate conductive pattern 271G may be exposed through the first gap 215. In one embodiment, the second blocking insulating layer 269 may be exposed through the first gap 215.

Fig. 25 and 26 are perspective views illustrating a process of forming a gate contact structure according to an embodiment of the present disclosure. Fig. 25 and 26 show only a portion of the gap-fill insulating layer 249 to aid in understanding the structure of each of the via portion 293 and the gate contact structure 290A.

Referring to fig. 25, sidewalls of the gate conductive pattern 271G may be exposed by removing portions of the second blocking insulating layer 269 exposed through the first gaps 215. In one embodiment, the conductive barrier layer 273 of the gate conductive pattern 271G may be exposed by removing a portion of the second blocking insulating layer 269.

Referring to fig. 26, the gate contact structure 290A may be formed by filling the first gap 215, the via portion 293, and the first vertical hole 291A shown in fig. 25 with a conductive material. The gate contact structure 290A may include a horizontal portion 290HP filling the first gap 215 and the via portion 293 shown in fig. 25, and a vertical portion 290VP filling the first vertical hole 291A shown in fig. 25.

In one embodiment, gate contact structure 290A may include a conductive barrier layer 295A and a metal layer 297A. The conductive barrier layer 295A of the gate contact structure 290A may constitute a surface of each of the horizontal portion 290HP and the vertical portion 290VP, and the metal layer 297A of the gate contact structure 290A may constitute a central region of each of the horizontal portion 290HP and the vertical portion 290VP.

The horizontal portion 290HP of the gate contact structure 290A may contact the sidewall of the gate conductive pattern 271G, and the vertical portion 290VP of the gate contact structure 290A may be spaced apart from the gate conductive pattern 271G by the gate interval insulating layer 261A. In one embodiment, the conductive barrier layer 295A of the horizontal portion 290HP may contact the conductive barrier layer 273 of the gate conductive pattern 271G.

Fig. 27A and 27B are cross-sectional views illustrating a gate contact structure 290A and a vertical contact structure 290B according to an embodiment of the present disclosure. Fig. 27A illustrates the gate contact structure illustrated in fig. 26.

Referring to fig. 27A, the sacrificial post 263A shown in fig. 21A may be replaced with a gate contact structure 290A by the process described with reference to fig. 22A, 23A, 24, 25 and 26.

Referring to fig. 27B, the second sacrificial post 263B shown in fig. 21B may be replaced with a vertical contact structure 290B by using a process that replaces the first sacrificial post 263A shown in fig. 21A with the gate contact structure 290A shown in fig. 27B. The vertical contact structure 290B may fill the second vertical hole 291B shown in fig. 23B. The vertical contact structure 290B may be spaced apart from the dummy stack structure 210B by a dummy spacer insulating layer 261B.

Referring to fig. 27A and 27B, the gate contact structure 290A and the vertical contact structure 290B may be respectively in contact with different conductive pads 317. The vertical contact structure 290B may comprise the same conductive material as the gate contact structure 290A. In one embodiment, vertical contact structure 290B may include a conductive barrier layer 295B and a metal layer 297B.

In the process of forming the gate contact structure 290A and the vertical contact structure 290B, a conductive material may be formed to fill the first and second vertical holes 291A and 291B shown in fig. 23A and 23B, and the conductive material may be planarized by a Chemical Mechanical Polishing (CMP) process or the like. When the third protective layer 207 is exposed, the planarization process may be stopped. Accordingly, the conductive material may be separated into the gate contact structure 290A and the vertical contact structure 290B.

Fig. 28A and 28B are cross-sectional views illustrating embodiments of subsequent processes that continue after the gate contact structure 290A and the vertical contact structure 290B are formed.

Referring to fig. 28A and 28B, the third protective layer 207 shown in fig. 27A and 27B may be removed, thereby exposing the memory layer 221. Subsequently, an upper insulating layer 401 may be formed. The upper insulating layer 401 may extend to cover the memory layer 221, the gate contact structure 290A, the vertical contact structure 290B, the gate interval insulating layer 261A, the dummy interval insulating layer 261B, the first insulating pattern 209A, and the second insulating pattern 209B.

Subsequently, upper holes 403A and 403B may be formed. The upper holes 403A and 403B may include a first upper hole 403A and a second upper hole 403B. The first upper hole 403A may penetrate the upper insulating layer 410 and the memory layer 221 to expose the channel layer 231 of the channel structure 230. The second upper hole 403B may penetrate the upper insulating layer 401 to expose the vertical contact structure 290B.

Subsequently, impurities may be implanted into a portion of the channel layer 231 exposed through the first upper hole 403A. In one embodiment, an n-type impurity may be implanted into the channel layer 231.

Next, a channel contact structure 405A filling the first upper hole 403A and a via plug 405B filling the second upper hole 403B may be formed. As described with reference to fig. 6 and 9, each of the channel contact structure 405A and the via plug 405 may include a conductive barrier layer and a metal layer.

Subsequently, subsequent processes for forming the bit line BL and the upper lines UL1 and UL2 shown in fig. 6 and 9 may be performed.

Fig. 29 is a block diagram showing a configuration of a memory system 1100 according to an embodiment of the present disclosure.

Referring to fig. 29, a memory system 1100 includes a memory device 1120 and a memory controller 1110.

Memory device 1120 may be a multi-chip package configured with a plurality of flash memory chips. The memory device 1120 may include a peripheral circuit layer and a stacked structure bonded to each other by a bonding structure. The stacked structure may include at least one of a cell stacked structure and a dummy stacked structure. The gate contact structure connected to the gate conductive pattern of the cell stack structure may include a vertical portion penetrating the cell stack structure and the bonding structure and spaced apart from the gate conductive pattern, and a horizontal portion extending from the vertical portion to contact the gate conductive pattern. The dummy stack structure may be penetrated by a vertical contact structure connected to the peripheral circuit layer. Similar to the vertical portion of the gate contact structure, the vertical contact structure may be spaced apart from the dummy stack structure and penetrate the bonding structure.

The memory controller 1110 controls the memory device 1120 and may include a Static Random Access Memory (SRAM) 1111, a Central Processing Unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115.SRAM 1111 serves as an operation memory for CPU 1112, CPU 1112 performs overall control operations for data exchange by memory controller 1110, and host interface 1113 includes a data exchange protocol for a host connected to memory system 1100. The error correction block 1114 detects and corrects errors included in the data read from the storage 1120. The memory interface 1115 interfaces with the memory device 1120. The memory controller 1110 may also include a Read Only Memory (ROM) or the like for storing code data for interfacing with a host.

Memory system 1100 may be a memory card or a Solid State Drive (SSD) in which memory device 1120 is engaged with controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1100 may communicate with an external (e.g., host) through one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol.

Fig. 30 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the disclosure.

With reference to FIG. 30, a computing system 1200 may include a CPU 1220, a Random Access Memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210, which are electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing operating voltages to the computing system 1200, and may also include an application chipset, an image processor, a mobile DRAM, and the like.

The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211. The memory device 1212 may be configured the same as the memory device 1120 described with reference to fig. 29. The memory controller 1211 may be configured the same as the memory controller 1100 described with reference to fig. 29.

According to the present disclosure, since the gate contact structure and the vertical contact structure penetrate the bonding structure and are connected to the peripheral circuit layer, the bonding structure may be simplified to a structure in which dielectric layers are bonded together. Therefore, the junction structure failure can be minimized, so that the operation reliability of the semiconductor memory device can be improved.

According to the present disclosure, since the vertical portion of the gate contact structure connected to the peripheral circuit layer is spaced apart from the multi-layered gate conductive pattern, an operation failure occurring when the vertical portion of the gate contact structure is commonly connected with the multi-layered conductive pattern can be improved.

According to the present disclosure, a horizontal portion extending from a vertical portion of the gate contact structure is self-aligned at a height at which one of the multi-layer gate conductive patterns is disposed. Accordingly, the one gate conductive pattern can be stably connected to the gate contact structure, so that the operation reliability of the semiconductor memory device can be improved.

According to the present disclosure, a vertical contact structure penetrating through a dummy stacked structure is formed by using a process of forming a gate contact structure, so that a manufacturing time of a semiconductor memory device can be reduced.

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2020-0098769, filed on 6 th month 8 2020, to korean intellectual property office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising:

a peripheral circuit layer;

a bonding structure disposed on the peripheral circuit layer;

a channel structure disposed on the engagement structure;

a first gate contact structure including a first vertical portion penetrating the junction structure and a first horizontal portion intersecting the first vertical portion and extending from the first vertical portion;

A first gate conductive pattern in contact with a sidewall of the first horizontal portion and spaced apart from the first vertical portion, wherein the first gate conductive pattern extends to surround the channel structure; and

a first gate interval insulating layer having a first width between the first vertical portion and the first gate conductive pattern and a second width smaller than the first width on a portion of the first vertical portion.

2. The semiconductor memory device of claim 1, wherein the bonding structure comprises a structure in which dielectric layers are bonded together.

3. The semiconductor memory device according to claim 1, further comprising:

a second gate conductive pattern surrounding the channel structure, and disposed between the first gate conductive pattern and the bonding structure; and

a second gate contact structure disposed between the second gate conductive pattern and the first gate contact structure,

Wherein the second gate contact structure includes a second vertical portion penetrating the bonding structure and the first gate conductive pattern, and a second horizontal portion extending from the second vertical portion, and

wherein a sidewall of the second horizontal portion is in contact with the second gate conductive pattern.

4. The semiconductor memory device according to claim 3, wherein the first gate conductive pattern protrudes further toward the first gate contact structure than the second gate conductive pattern.

5. The semiconductor memory device according to claim 3, further comprising:

a first interlayer insulating layer surrounding the channel structure between the first gate conductive pattern and the second gate conductive pattern;

a second interlayer insulating layer overlapping the first interlayer insulating layer with the first gate conductive pattern interposed therebetween, wherein the second interlayer insulating layer surrounds the channel structure; and

a second gate interval insulating layer surrounding sidewalls of the second vertical portion, wherein the second horizontal portion penetrates the second gate interval insulating layer,

Wherein the first gate interval insulating layer surrounds a sidewall of the first vertical portion and is penetrated by the first horizontal portion.

6. The semiconductor memory device according to claim 5, wherein each of the first gate interval insulating layer and the second gate interval insulating layer protrudes toward the first gate conductive pattern to fill a gap between the first interlayer insulating layer and the second interlayer insulating layer.

7. The semiconductor memory device according to claim 5, wherein each of the first gate interval insulating layer and the second gate interval insulating layer includes a bottom surface facing the peripheral circuit layer and overlapping the bonding structure.

8. The semiconductor memory device according to claim 1, wherein the peripheral circuit layer comprises:

a substrate including an impurity region;

an interconnect structure connected to the impurity region; and

a conductive pad connected to the interconnect structure and overlapping the first vertical portion.

9. The semiconductor memory device of claim 8, wherein the first vertical portion extends into contact with the conductive pad.