CN114065679A

CN114065679A - Rapid FPGA top-level layout design method

Info

Publication number: CN114065679A
Application number: CN202111373193.1A
Authority: CN
Inventors: 高东旭; 韦援丰
Original assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Current assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2022-02-18

Abstract

The invention discloses a rapid design method of an FPGA top layer layout, which comprises the following steps: dividing an FPGA top layer domain into programmable modules distributed in an array mode and programmable IO modules located around the programmable modules; setting a rectangular bounding box of each programmable module class forming the programmable gate array on a computer; setting parameters for forming the programmable gate array on a computer; and fourthly, generating the FPGA top layer layout by the computer according to the composition of the FPGA top layer layout in the first step and the parameters set in the second step and the third step. According to the invention, the required FPGA array can be quickly and accurately spliced only by specifying the rectangular bounding box of each programmable module and providing the parameters for forming the programmable gate array, compared with the manual splicing, the spliced domain does not generate dislocation, the LVS error of the splicing type is not caused, the splicing speed is high, and the working efficiency is improved.

Description

Rapid FPGA top-level layout design method

Technical Field

The invention belongs to the technical field of FPGA, and particularly relates to a rapid design method of an FPGA top-level layout.

Background

A Field-Programmable Gate Array (FPGA) is a Programmable device, and its structure features that it is composed of high-density repetitive Programmable modules, and after being programmed, it can realize different circuit functions. Due to the special features of short design cycle, fast time to market, low Non-repetitive Engineering (NRE) cost of FPGAs, and the dynamic reconfigurable nature of FPGAs, more and more soc (system On a chip) systems On chip are being considered to be embedded into the FPGA core.

At present, the rear-end layout design of each programmable module adopts a full-custom mode, because the rear-end layout design of an automatic process cannot meet the requirement of high density.

The top array physical layout of the programmable module can be divided into a programmable module class (BLK) and a programmable IO module class (IOBLK). Each column of the array is one of the programmable module classes, the number of rows of each column is the same, and the programmable IO module class surrounds the array. The programmable modules can be classified into general programmable modules (GBLK), memory programmable blocks (MBLK), and digital signal processing programmable blocks (DBLK). The programmable IO module class is that each programmable block class corresponds to an upper programmable IO module and a lower programmable IO module, and the left side and the right side are respectively provided with two programmable IO modules. Each module is divided into a left module and a right module according to the physical position of the chip, and the height and the width of each module are the same and are different. An FPGA chip at the level of ten million gates needs 1000 physical layout modules, and the types of the modules are 20.

Traditional manual splicing of the modules is slow, prone to error and irregular, and eFPGA (embedded field programmable gate array) clients cannot provide physical information for IP in time when the clients want to know the physical information in advance; LVS (layout-schematic ratio) errors caused by manual splicing are sometimes difficult to locate; these problems are exacerbated by billions of FPGAs.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a rapid design method for the top layer layout of the FPGA aiming at the defects in the prior art, compared with manual splicing, the design method for the top layer layout of the FPGA does not generate dislocation, cannot cause splicing type LVS errors, is rapid in splicing speed, and improves the working efficiency.

In order to solve the technical problems, the invention adopts the technical scheme that: a rapid FPGA top layer layout design method is characterized by comprising the following steps:

dividing an FPGA top layer domain into programmable module types (BLK) distributed in an array mode and programmable IO module types (IOBLK) located around the programmable module types (BLK); programmable module types (BLK) distributed in an array form a programmable gate array, each column of the programmable gate array is one of the programmable module types (BLK), and the number of rows of each column is equal;

setting a rectangular bounding box of each programmable module (BLK) forming the programmable gate array on a computer;

setting parameters for forming the programmable gate array on a computer;

and step four, generating the FPGA top layer layout by the computer according to the composition of the FPGA top layer layout in the step one and the parameters set in the step two and the step three.

The rapid FPGA top-level layout design method is characterized by comprising the following steps: and the second step to the fourth step are all carried out on a computer by adopting the Skill language of Cadence software.

The rapid FPGA top-level layout design method is characterized by comprising the following steps: the parameters in the second step comprise a layout path of each programmable module class, a row number sequence of each section after each column is divided into several sections, a spacing sequence between longitudinal arrays, a spacing sequence between transverse arrays and a programmable module class code sequence from left to right of the FPGA array.

The rapid FPGA top-level layout design method is characterized by comprising the following steps: the programmable block class (BLK) includes a general programmable block (GBLK), a storage programmable block (MBLK), and a digital signal processing programmable block (DBLK).

The rapid FPGA top-level layout design method is characterized by comprising the following steps: the programmable IO module class (IOBLK) comprises an upper common programmable IO module (IOGU) arranged above a common programmable module (GBLK) and a lower common programmable IO module (IOGD) arranged below the common programmable module (GBLK), an upper storage programmable IO module (IOMU) arranged above a storage programmable block (MBLK) and a lower storage programmable IO module (IOMD) arranged below the storage programmable block (MBLK), an upper digital signal processing programmable IO module (IODU) arranged above a digital signal processing programmable block (DBLK) and a lower digital signal processing programmable IO module (IODD) arranged below the digital signal processing programmable block (DBLK); and a left programmable IO module (IOL) disposed on a left side of the programmable module class (BLK) and a right programmable IO module (IOR) disposed on a right side of the programmable module class (BLK).

The invention also provides a rapid FPGA top-level layout design method aiming at the condition that a certain programmable module is not designed completely or all programmable module layouts are not designed at the beginning stage and only the splicing area size of the FPGA layout needs to be accurately evaluated, which can accurately position the boundary of an IP core without influencing the layout design of other modules adjacent to the IP core and comprises the following steps:

firstly, setting the length and width values of a programmable gate array on a computer;

and step two, generating an FPGA top layer layout with only module boundaries for splicing.

The rapid FPGA top-level layout design method is characterized by comprising the following steps: and both the first step and the second step are carried out on a computer by adopting the Skill language of Cadence software.

Compared with the prior art, the invention has the following advantages:

1. the invention provides a rapid top-level layout design method. According to the method, based on the Cadence's Skill language tool, only the rectangular bounding box of each programmable module class needs to be specified, parameters for forming the programmable gate array are given, the required FPGA array can be spliced quickly and accurately, the domain generated by splicing cannot be dislocated compared with manual splicing, LVS errors of splicing classes cannot be caused, the splicing speed is high, and the working efficiency is improved.

2. In the initial stage of FPGA design, when the physical layout of each programmable module does not start to be designed, the invention can quickly generate the layout of the bounding box of each programmable module according to the specified numerical value, and can accurately evaluate the physical dimension of the top layout of the FPGA.

3. The invention can rapidly provide the accurate area of the physical layout design when the client of the eFPGA proposes the parameter condition of the customized IP core, and the client can accurately position the boundary of the IP core without influencing the layout design of other modules adjacent to the IP core.

4. The method is suitable for designing the top layer layout of the FPGA core and the top layer layout of the eFPGA, and the popularization and the application of the method can solve the technical problem of designing the top layer layout of the FPGA at the hundred million gate level in the prior art.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

FIG. 1 is a block diagram of a process flow of embodiment 1 of the present invention;

FIG. 2 is a schematic diagram of a top-level layout of an FPGA generated by the method of embodiment 1 of the present invention;

fig. 3 is a flow chart of a method in embodiment 2 of the present invention.

Detailed Description

Example 1

The embodiment generates the designed FPGA top layer layout.

As shown in fig. 1, the fast FPGA top layout design method of this embodiment includes the following steps:

setting parameters for forming the programmable gate array on a computer;

In specific implementation, the required FPGA top gate array layout can be generated by clicking the generation button.

In this embodiment, the second step to the fourth step are all performed on a computer by using the skip language of Cadence software.

In this embodiment, the parameters in the second step include a layout path of each programmable module class, a row number sequence of each segment after each column is divided into several segments, a pitch sequence between the vertical arrays, a pitch sequence between the horizontal arrays, and a programmable module class code sequence of the FPGA array from left to right.

In this embodiment, the programmable block class (BLK) includes a general programmable block (GBLK), a storage programmable block (MBLK), and a digital signal processing programmable block (DBLK).

In this embodiment, the programmable IO module class (IOBLK) includes an upper common programmable IO module (IOGU) disposed above a common programmable module (GBLK), a lower common programmable IO module (IOGD) disposed below the common programmable module (GBLK), an upper storage programmable IO module (IOMU) disposed above a storage programmable block (MBLK), a lower storage programmable IO module (IOMD) disposed below the storage programmable block (MBLK), an upper digital signal processing programmable IO module (IODU) disposed above a digital signal processing programmable block (DBLK), and a lower digital signal processing programmable IO module (IODD) disposed below the digital signal processing programmable block (DBLK); and a left programmable IO module (IOL) disposed on a left side of the programmable module class (BLK) and a right programmable IO module (IOR) disposed on a right side of the programmable module class (BLK).

In specific implementation, each parameter is specifically set as follows:

the layout (layout) path of each programmable module class can be selected and stored in a developed interface, and can be read all the classes at one time without being specified one by one next time;

the row number sequence of each section after each column is divided into several sections is represented by a letter DV, such as DV = "50505050" represents that each column is divided into 4 sections;

the pitch sequence between the vertical arrays is represented by the letter SV, such as SV = "100200100" for each row of segments with pitches of 100um, 200um, 100um from top to bottom; as shown in fig. 2;

the sequence of pitches between the transverse arrays, denoted by the letter SH, for example SH = "100300100", represents a pitch of 100um, 300um, 100um per column from left to right; as shown in fig. 2;

the programmable module class code sequence from left to right of the FPGA array, such as the number "4" represents successive 4 columns of the same class of modules, g represents GBLK (general programmable module), m represents MBLK (memory programmable block), d represents DBLK (digital signal processing programmable block), t represents a clock column, c represents a chip middle column, for example: "4 gd3gt4gmc8gmt2gd2 g".

The array scale in fig. 2 is only illustrative, and a layout array of any scale and pitch can be generated according to parameters. Compared with manual splicing, the layout generated by splicing cannot generate dislocation, splicing type LVS errors cannot be caused, the splicing speed is high, and the working efficiency is improved.

Example 2

The embodiment aims at the situation that a certain programmable module is not designed completely, or all programmable module layouts are not designed at the beginning stage, and the splicing area size of the FPGA layouts is only required to be accurately evaluated.

As shown in fig. 3, the method for designing the FPGA top layout of the present embodiment includes the following steps:

firstly, setting the length and width values of a programmable gate array on a computer; automatically establishing a temporary layout library;

generating an FPGA top layer layout with only module boundaries for splicing; the various programmable modules can generate layouts with the same size in batch at one time.

In this embodiment, both the first step and the second step are performed on a computer by using the skip language of Cadence software.

According to the method for designing the top-level layout of the FPGA, when the physical layout of each programmable module does not start to be designed in the initial stage of FPGA design, the bounding box layout of each programmable module can be quickly generated according to the specified numerical value, and the physical size of the top-level layout of the FPGA can be accurately evaluated. When the client of the eFPGA proposes the parameter condition of the customized IP core, the accurate area of the physical layout design can be quickly given, the client can accurately position the boundary of the IP core, and the layout design of other modules adjacent to the IP core is not influenced.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A rapid FPGA top layer layout design method is characterized by comprising the following steps:

dividing an FPGA top layer domain into programmable modules distributed in an array mode and programmable IO modules located around the programmable modules; the programmable modules arranged in an array form a programmable gate array, each column of the programmable gate array is one of the programmable modules, and the number of rows in each column is equal;

setting a rectangular bounding box of each programmable module class forming the programmable gate array on a computer;

setting parameters for forming the programmable gate array on a computer;

2. The method for rapidly designing the FPGA top-level layout according to claim 1, characterized in that: and the second step to the fourth step are all carried out on a computer by adopting the Skill language of Cadence software.

3. The method for rapidly designing the FPGA top-level layout according to claim 1 or 2, is characterized in that: the parameters in the second step comprise a layout path of each programmable module class, a row number sequence of each section after each column is divided into several sections, a spacing sequence between longitudinal arrays, a spacing sequence between transverse arrays and a programmable module class code sequence from left to right of the FPGA array.

4. The method for rapidly designing the FPGA top-level layout according to claim 1 or 2, is characterized in that: the programmable module class includes common programmable modules, storage programmable blocks and digital signal processing programmable blocks.

5. The method for rapidly designing the FPGA top-level layout according to claim 4, characterized in that: the programmable IO module class comprises an upper common programmable IO module arranged above the common programmable module, a lower common programmable IO module arranged below the common programmable module, an upper storage programmable IO module arranged above the storage programmable block, a lower storage programmable IO module arranged below the storage programmable block, an upper digital signal processing programmable IO module arranged above the digital signal processing programmable block and a lower digital signal processing programmable IO module arranged below the digital signal processing programmable block; and the left programmable IO module is arranged on the left side of the programmable module class and the right programmable IO module is arranged on the right side of the programmable module class.

6. A rapid FPGA top layer layout design method is characterized by comprising the following steps:

7. The method for rapidly designing the FPGA top-level layout according to claim 6, characterized in that: and both the first step and the second step are carried out on a computer by adopting the Skill language of Cadence software.