CN114063757A - INTEL SVID power supply replacement method and device - Google Patents
INTEL SVID power supply replacement method and device Download PDFInfo
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- CN114063757A CN114063757A CN202111402627.6A CN202111402627A CN114063757A CN 114063757 A CN114063757 A CN 114063757A CN 202111402627 A CN202111402627 A CN 202111402627A CN 114063757 A CN114063757 A CN 114063757A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000001105 regulatory effect Effects 0.000 claims abstract description 8
- 230000001276 controlling effect Effects 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000000630 rising effect Effects 0.000 claims description 4
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- 230000002457 bidirectional effect Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a INTEL SVID power supply replacement method and device, wherein a field programmable gate array line receives and identifies address data and effective load data in bus data of a power supply management bus of a central processing unit, a preset number of output circuits are configured according to the address data, the output circuits are used for controlling a corresponding number of adjustable power supply modules in a one-to-one correspondence manner, and finally, the voltage output of the adjustable power supply modules is adjusted according to the effective load data. The invention adopts the form of adding the adjustable power supply to the field programmable gate array, and utilizes the field programmable gate array to identify and analyze the data of the power supply management bus, thereby realizing the functions of supplying power and regulating the voltage of the adjustable power supply, replacing some power supply chips supporting the SVID technology, meeting the requirement of INTEL on power supply, and solving the problem of power supply chip supply.
Description
Technical Field
The invention relates to the technical field of power chips, in particular to a INTEL SVID power supply replacement method and device.
Background
The SVID (Serial Voltage Identification) is a power management bus protocol of a power chip which is provided by INTEL (INTEL) to a CPU (central processing unit) for supplying power, and the protocol realizes the functions of the CPU such as control, Voltage switching, real-time parameter reading and the like to the power chip. At present, the power chip supporting the SVID technology is mainly monopolized by texas instruments, inflixa, risa and core sources. With the increasing problem of chip supply, manufacturers of other power chips without supporting the SVID technology are urgently required to find a SVID power supply replacement scheme to meet the power supply requirement of INTEL to the power supply and solve the problem of power chip supply.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the INTEL SVID power supply replacement method and device are provided to meet the power supply requirement of INTEL to power supply and solve the supply problem of power supply chips.
In order to solve the problems, the invention adopts the following scheme:
a method of INTEL SVID power replacement, comprising the steps of:
s1, receiving and identifying address data and payload data in bus data of a power management bus of the central processing unit;
s2, configuring a preset number of output circuits according to the address data, wherein the output circuits are used for controlling a corresponding number of adjustable power modules in a one-to-one correspondence manner;
and S3, adjusting the voltage output of the adjustable power supply module according to the effective load data.
In order to solve the above problems, the present invention adopts another scheme as follows:
an INTEL SVID power supply replacement device comprises a field programmable gate array and an adjustable power supply;
the field programmable gate array is connected to the adjustable power supply, and the field programmable gate array is used for connecting a power management bus of a central processing unit and executing the INTEL SVID power supply replacement method.
In conclusion, the beneficial effects of the invention are as follows: the INTEL SVID power supply replacement method and device are characterized in that a field programmable gate array and an adjustable power supply are adopted, the field programmable gate array is used for identifying and analyzing data of a power supply management bus, and further the power supply and voltage regulation functions of the adjustable power supply are realized, so that power supply chips supporting SVID technology are replaced, the requirements of INTEL on power supply are met, and the supply problem of the power supply chips is solved.
Drawings
FIG. 1 is a schematic diagram illustrating the steps of a INTEL SVID power supply replacement method according to an embodiment of the present invention;
fig. 2 is a system block diagram of an INTEL SVID power supply replacement apparatus according to an embodiment of the invention.
Description of reference numerals:
1. a central processing unit; 2. a field programmable gate array; 3. an adjustable power module.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1 and 2, a INTEL SVID power supply replacement method includes the following steps:
s1, receiving and identifying address data and payload data in the bus data of the power management bus of the central processing unit 1;
s2, configuring a preset number of output circuits according to the address data, wherein the output circuits are used for controlling a corresponding number of adjustable power modules 3 in a one-to-one correspondence manner;
s3, adjusting the voltage output of the adjustable power supply module 3 according to the payload data.
From the above description, the beneficial effects of the present invention are: the INTEL SVID power supply replacement method and device are characterized in that a field programmable gate array (2) and an adjustable power supply are adopted, the field programmable gate array (2) is used for identifying and analyzing data of a power supply management bus, and then the power supply and voltage regulation functions of the adjustable power supply are realized so as to replace some power supply chips supporting the SVID technology, meet the requirements of INTEL on power supply of the power supply and solve the supply problem of the power supply chips.
Further, the step S3 further includes:
s31, configuring a power state bit on a register, wherein the value of the power state bit comprises a power busy state value and a power idle state value;
s32, setting a timer with preset duration, starting the timer to time, and adjusting the voltage output of the adjustable power module 3 according to the effective load data;
s33, judging whether the timer stops timing;
if not, setting the value of the power state bit as a power busy state value, and releasing an alarm signal of the power management bus to the central processing unit 1;
if so, setting the value of the power state bit as a power idle state value, and stopping releasing the alarm signal.
As can be seen from the above description, the value of the power status bit and the timer are set to provide enough time for the adjustable power supply to complete a single voltage regulation, and the value of the power status bit is changed to the power idle status value only after the timer counts up, i.e. it indicates that the current adjustable power supply has completed the voltage regulation and can receive and execute the next regulation command of the central processing unit 1, thereby achieving stable and reliable power management.
Further, the step S3 is followed by:
s4, identifying command data in the bus data, wherein the command data comprises target data required to be acquired by the central processing unit 1;
and S5, taking the current value of the target data as response data, and sending the response data to the central processing unit 1 through the power management bus.
As can be seen from the above description, the command data of the central processing unit 1 is received, and the target data that the central processing unit 1 wants to know is responded, so that the central processing unit 1 can know the real-time state of the current adjustable power supply and assist the current adjustable power supply to perform efficient and reasonable power supply management work.
Further, step S1 is preceded by:
s0, receiving a clock signal of the power management bus;
if the clock signal is a falling edge, the step S1 is executed;
if the clock signal is a rising edge, the step S4 is executed.
From the above description, the clock signal is used to divide the working content, perform the power supply voltage regulation work at the falling edge, and respond to the data request of the central processing unit 1 at the rising edge, so as to comprehensively cooperate with the central processing unit 1 to realize the analysis and conversion of the power supply management protocol.
Further, the taking the current value of the target data as the response data includes:
and if the target data comprises the power state bit, adding the current value of the power state bit into the response data.
As can be seen from the above description, the power status bit is reported when necessary, so that the cpu 1 can know the completion of the current voltage regulation in real time.
Further, the taking the current value of the target data as the response data further includes:
and if the target data comprises the parameter data of the adjustable power supply module 3, acquiring the parameter data of the adjustable power supply module 3, and adding the parameter data into the response data.
From the above description, it can be known that the central processing unit 1 is helped to know the working condition of the adjustable power supply module 3 in real time in response to the requirement of the central processing unit 1 for the parameter data of the adjustable power supply module 3, so as to make a better instruction for the next step.
Further, before the sending the response data, the step S5 further includes:
and accessing a first check value in the response data, wherein the first check value is used for representing the integrity of the response data.
From the above description, it can be known that the first check value is added to the response data, so that the central processing unit 1 can confirm the integrity of the data after receiving the data, ensure that the transmission link is normal, and improve the reliability of the data.
Further, the step S1 further includes:
a second parity value in the bus data is identified, the second parity value being indicative of an integrity of the bus data.
As can be seen from the above description, the bus data sent down on the power management bus includes the second check value, and the second check value can be checked after the bus data is received, so as to confirm that the transmission data is correct and reliable data, and ensure that the power management protocol is correctly analyzed and converted.
Further, the step S3 is specifically:
performing digital-to-analog conversion on the effective load data to obtain a voltage regulation analog quantity;
and outputting the voltage regulation analog quantity to a regulation feedback network of the adjustable power supply module 3, and regulating the voltage output of the adjustable power supply module 3.
As can be seen from the above description, during voltage regulation, the payload data is subjected to digital-to-analog conversion, and the obtained result is used to regulate the adjustable power supply module 3.
Referring to fig. 2, an INTEL SVID power supply replacement apparatus includes a field programmable gate array 2 and an adjustable power supply module 3;
the field programmable gate array 2 is connected with the adjustable power supply module 3, and the field programmable gate array 2 is used for connecting a power supply management bus of the central processing unit 1 and executing the INTEL SVID power supply replacement method.
From the above description, the beneficial effects of the present invention are: the INTEL SVID power supply replacement method and device are characterized in that a field programmable gate array (2) and an adjustable power supply are adopted, the field programmable gate array (2) is used for identifying and analyzing data of a power supply management bus, and then the power supply and voltage regulation functions of the adjustable power supply are realized so as to replace some power supply chips supporting the SVID technology, meet the requirements of INTEL on power supply of the power supply and solve the supply problem of the power supply chips.
The INTEL SVID power supply replacement method and device of the invention are applicable to an application scenario in which the central processing unit 1 utilizes a power supply management bus protocol to regulate and control a power supply, and are specifically described below with reference to specific embodiments:
referring to fig. 1, a first embodiment of the present invention is:
a method of INTEL SVID power replacement, as shown in fig. 1, comprising the steps of:
s0, receiving a clock signal of the power management bus; if the clock signal is a falling edge, the step S1 is executed; if the clock signal is a rising edge, the step S4 is executed.
S1, receiving and identifying address data and payload data in the bus data of the power management bus of the central processing unit 1;
in this embodiment, the main data to be identified and analyzed are address data, command data, and payload data in the bus data, and specifically, according to the rule of the power management bus protocol, the frame start field is identified first, and then these data are identified one by one. In addition, the bus data also includes a second check value, which is used to confirm that the data sent from the central processing unit 1 is not damaged, etc., so as to ensure the correctness of the transmission link. Alternatively, the second check value may be generated by exclusive-or using address data, command data, and payload data.
S2, configuring a preset number of output circuits according to the address data, wherein the output circuits are used for controlling a corresponding number of adjustable power modules 3 in a one-to-one correspondence manner;
in this embodiment, the preset number corresponds to the number of the adjustable power modules 3 that the central processing unit 1 currently wants to control, which are included in the address data; for this purpose, corresponding output lines are provided for differential control according to the commands of the central processor 1.
S31, configuring a power state bit on a register, wherein the value of the power state bit comprises a power busy state value and a power idle state value;
s32, setting a timer with preset duration, starting the timer to time, and adjusting the voltage output of the adjustable power module 3 according to the effective load data;
in this embodiment, the preset duration of the timer is a fixed value considered to be preset in advance, and provides sufficient completion time for a single voltage conversion process, which is triggered specifically after receiving payload data.
In this embodiment, when adjusting the voltage output of the adjustable power module 3, firstly, performing digital-to-analog conversion on the payload data to obtain a voltage adjustment analog quantity; and then outputting the voltage regulation analog quantity to a regulation feedback network of the adjustable power supply module 3, and regulating the voltage output of the adjustable power supply module 3. Also, the regulation feedback network may use resistance regulation feedback.
S33, judging whether the timer stops timing;
if not, setting the value of the power state bit as a power busy state value, and releasing an alarm signal of the power management bus to the central processing unit 1;
if so, setting the value of the power state bit as a power idle state value, and stopping releasing the alarm signal.
S4, identifying command data in the bus data, wherein the command data comprises target data required to be acquired by the central processing unit 1;
in this embodiment, the target data specifically includes a power status bit, parameter data of the adjustable power module 3, and a first check value. The first check value may be generated by xoring data of other fields such as a power status bit and parameter data. After receiving the response data, the central processing unit 1 may perform a check using the first check value to confirm that the data has no errors during the transmission process. The first check value and the second check value form a bidirectional double guarantee to ensure that power management is stably and reliably realized.
And S5, taking the current value of the target data as response data, and sending the response data to the central processing unit 1 through the power management bus.
In this embodiment, the response data corresponds to the content of the target data, for example, if the target data provides the value of the power status bit and the parameter data of the adjustable power module 3, the values of the two data are sent to the central processing unit 1 in the response data. For the parameter data of the adjustable power module 3, the detection result of the external detection unit on the adjustable power module 3 can be read by checking the fixed data or reading the external I2C.
Referring to fig. 2, the second embodiment of the present invention is:
an INTEL SVID power supply replacement device is shown in fig. 2 and comprises a field programmable gate array 2 and an adjustable power supply module 3. The field programmable gate array 2 is connected to the adjustable power supply module 3, and the field programmable gate array 2 is used for connecting to a power management bus of the central processing unit 1 and executing the INTEL SVID power supply replacement method of the first embodiment.
In this embodiment, specifically, as shown in fig. 2, the field programmable gate array 2 includes a receiving driving module, an analyzing module, a data processing module, a voltage regulating module, a data collecting unit, and a verification response module. The receiving driving module is used for connecting three signal lines of CLK (clock), DATA (DATA) and ALERT # (alarm) from a power management bus of the central processing unit 1. The analysis module is used for analyzing the data of the data bus so as to obtain an address, a command, a payload and a second check value. The data processing module is used for digitizing the data of the effective load and sending the data to the voltage regulating module, setting a power state bit on the register and setting and starting the timer. The voltage regulating module is used for accessing the digitized data of the effective load into the voltage feedback network and regulating the voltage output of the adjustable power supply module 3. The data acquisition unit is used for acquiring parameter data of the adjustable power supply module 3. The verification response module is responsible for generating response data and sending the response data to the central processing unit 1.
In summary, the invention discloses a INTEL SVID power supply replacement method and device, which adopts a field programmable gate array plus an adjustable power supply form, and utilizes the field programmable gate array to identify and analyze data of a power supply management bus, thereby realizing that one field programmable gate array simultaneously controls a plurality of adjustable power supply modules, having power supply and voltage regulation functions to the adjustable power supply, using a way of matching working contents of timer timing, check response and clock signal division, reasonably laying out a power supply management flow, having a protection function of bidirectional check, replacing some power supply chips supporting an SVID technology, meeting the requirements of INTEL on power supply, and solving the supply problem of the power supply chips.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent modifications made by the contents of the present specification and the drawings, or applied to the related technical fields directly or indirectly, are included in the scope of the present invention.
Claims (10)
1. A method of INTEL SVID power replacement, comprising the steps of:
s1, receiving and identifying address data and payload data in bus data of a power management bus of the central processing unit;
s2, configuring a preset number of output circuits according to the address data, wherein the output circuits are used for controlling a corresponding number of adjustable power modules in a one-to-one correspondence manner;
and S3, adjusting the voltage output of the adjustable power supply module according to the effective load data.
2. The power replacement method INTEL SVID of claim 1, wherein the step S3 further comprises:
s31, configuring a power state bit on a register, wherein the value of the power state bit comprises a power busy state value and a power idle state value;
s32, setting a timer with preset duration, starting the timer to time, and adjusting the voltage output of the adjustable power supply module according to the effective load data;
s33, judging whether the timer stops timing;
if not, setting the value of the power state bit as a power busy state value, and releasing an alarm signal of the power management bus to the central processing unit;
if so, setting the value of the power state bit as a power idle state value, and stopping releasing the alarm signal.
3. The power replacement method INTEL SVID of claim 2, wherein the step S3 is followed by further comprising:
s4, identifying command data in the bus data, wherein the command data comprises target data required to be acquired by the central processing unit;
and S5, taking the current value of the target data as response data, and sending the response data to the central processing unit through the power management bus.
4. The power replacement method INTEL SVID of claim 3, wherein the step S1 is preceded by the step of:
s0, receiving a clock signal of the power management bus;
if the clock signal is a falling edge, the step S1 is executed;
if the clock signal is a rising edge, the step S4 is executed.
5. The INTEL SVID method of power supply replacement according to claim 3, wherein the taking the current value of the target data as answer data includes:
and if the target data comprises the power state bit, adding the current value of the power state bit into the response data.
6. The INTEL SVID method of power supply replacement according to claim 5, wherein said taking the current value of the target data as answer data further comprises:
and if the target data comprises parameter data of the adjustable power supply module, acquiring the parameter data of the adjustable power supply module, and adding the parameter data into the response data.
7. The method INTEL SVID of claim 3, wherein before the step S5, the step of sending the response data further comprises:
and accessing a first check value in the response data, wherein the first check value is used for representing the integrity of the response data.
8. The power replacement method INTEL SVID of claim 1, wherein the step S1 further comprises:
a second parity value in the bus data is identified, the second parity value being indicative of an integrity of the bus data.
9. The INTEL SVID power supply replacement method according to claim 1, wherein the step S3 is specifically:
performing digital-to-analog conversion on the effective load data to obtain a voltage regulation analog quantity;
and outputting the voltage regulation analog quantity to a regulation feedback network of the adjustable power supply module, and regulating the voltage output of the adjustable power supply module.
10. An INTEL SVID power supply replacement device, which is characterized by comprising a field programmable gate array and an adjustable power supply module;
the field programmable gate array is connected with the adjustable power supply module, and the field programmable gate array is used for connecting a power supply management bus of a central processing unit and executing a INTEL SVID power supply replacement method of any one of claims 1 to 9.
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