CN114050874A - Modulation calibration circuit and method - Google Patents
Modulation calibration circuit and method Download PDFInfo
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- CN114050874A CN114050874A CN202210029819.5A CN202210029819A CN114050874A CN 114050874 A CN114050874 A CN 114050874A CN 202210029819 A CN202210029819 A CN 202210029819A CN 114050874 A CN114050874 A CN 114050874A
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Abstract
The invention provides a modulation calibration circuit and a modulation calibration method. The modulation calibration circuit comprises; the calibration source generating circuit, the gain adjusting circuit and the direct current offset adjusting circuit. The calibration source generating circuit is used for generating an I path of calibration source and a Q path of calibration source, and the I path of calibration source and the Q path of calibration source respectively comprise at least two voltages with different amplitudes; the input end of the gain adjusting circuit is electrically connected with the output end of the calibration source generating circuit and is used for respectively carrying out gain adjustment on the I-path calibration source and the Q-path calibration source; the input end of the direct current offset adjusting circuit is electrically connected with the output end of the gain adjusting circuit and is used for carrying out direct current offset adjustment on the I-path calibration source and the Q-path calibration source which are subjected to gain adjustment. The invention solves the defects that the interference on the detection result caused by the signal of the IQ baseband needs to be considered in the prior art, and the absolute accuracy of the output signal of the IQ modulator needs to be measured, so the design difficulty of a calibration circuit is high.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a modulation calibration circuit and a modulation calibration method.
Background
The existing calibration method usually needs to input an IQ baseband signal to calibrate the IQ modulator, if the IQ modulator output needs to ignore the influence of the IQ baseband signal, a filter is needed to carry out filtering, and filtering within a full bandwidth is difficult to realize for an ultra-wideband IQ modulator, so that self-closed loop calibration is difficult to realize during calibration, and often test equipment such as an external spectrometer is needed to calibrate the IQ modulator. That is, the conventional calibration method needs to consider the interference to the detection result caused by the presence of the signal in the IQ baseband, and needs to measure the absolute accuracy of the output signal of the IQ modulator, so that the design difficulty of the calibration circuit is high.
Disclosure of Invention
The invention provides a modulation calibration circuit and a method thereof, which are used for solving the defects that the interference on a detection result caused by the existence of a signal in an IQ baseband needs to be considered, and the absolute accuracy of an output signal of an IQ modulator needs to be measured, so that the design difficulty of a calibration circuit is high.
The present invention provides a modulation calibration circuit, comprising:
a calibration source generation circuit; the calibration source generating circuit is used for generating an I path of calibration source and a Q path of calibration source, and the I path of calibration source and the Q path of calibration source respectively comprise at least two voltages with different amplitudes;
a gain adjustment circuit; the input end of the gain adjusting circuit is electrically connected with the output end of the calibration source generating circuit and is used for respectively carrying out gain adjustment on the I-path calibration source and the Q-path calibration source; and
and the input end of the direct current bias adjusting circuit is electrically connected with the output end of the gain adjusting circuit and is used for carrying out direct current bias adjustment on the I-path calibration source and the Q-path calibration source which are subjected to gain adjustment.
According to a modulation calibration circuit provided by the present invention, the calibration source generating circuit includes:
a bandgap reference source module for generating a reference voltage;
the input end of the operational circuit is electrically connected with the output end of the band-gap reference source module and is used for generating at least two voltages with different resistance values based on the reference voltage;
a first switch; the input end of the first switch is electrically connected with the output end of the operational circuit; the I-path calibration source is used for selecting one output voltage from the output end of the operational circuit as the I-path calibration source;
a second switch; the input end of the second switch is electrically connected with the output end of the operational circuit; the output end of the operational circuit is used for selecting an output voltage as the Q-path calibration source; and
and the power supply module is electrically connected with the band gap reference source module, the operation circuit, the first switch and the second switch respectively.
According to a modulation calibration circuit provided by the present invention, the gain adjustment circuit includes: a first sub-regulation circuit and a second sub-regulation circuit;
the first sub-regulation circuit includes:
a first multiplier; the first input end of the first multiplier is electrically connected with the output end of the I-path calibration source generated by the calibration source generating circuit; a second input of the first multiplier is configured to receive a first gain adjustment signal;
a first adder; a first input end of the first adder is electrically connected with an output end of the first multiplier; the second input end of the first adder is electrically connected with the output end of the I-path calibration source generated by the calibration source generating circuit; the output end of the first adder is electrically connected with the input end of the direct current offset adjusting circuit;
the second sub-regulation circuit includes:
a second multiplier; the first input end of the second multiplier is electrically connected with the output end of the Q-path calibration source generated by the calibration source generating circuit; a second input of the second multiplier is for receiving a second gain adjustment signal;
a second adder; a first input end of the second adder is electrically connected with an output end of the second multiplier; a second input end of the second adder is electrically connected with an output end of the calibration source generating circuit generating the Q-path calibration source; the output end of the second adder is electrically connected with the input end of the direct current offset adjusting circuit.
According to the modulation calibration circuit provided by the invention, the direct current offset adjusting circuit comprises a digital-to-analog conversion module, a first differential amplifier and a second differential amplifier;
a first input end of the first differential amplifier is electrically connected with an output end of the first adder, and a second input end of the first differential amplifier is electrically connected with a first direct-current voltage output end of the digital-to-analog conversion module;
the first input end of the second differential amplifier is electrically connected with the output end of the second adder, and the second input end of the second differential amplifier is electrically connected with the second direct-current voltage output end of the digital-to-analog conversion module.
According to the modulation calibration circuit provided by the invention, the modulation calibration circuit further comprises a third switch and a fourth switch;
the third switch comprises a first input terminal for inputting an external IQ signal; a second input end for inputting the I-path calibration source and the Q-path calibration source generated by the calibration source generating circuit; and an output for performing an alternative output to the first input of the third switch and the second input of the third switch;
the fourth switch comprises a first input end electrically connected with the output end of the third switch, a second input end used for inputting an internal IQ signal, and an output end used for carrying out one-out-of-two output on the first input end of the fourth switch and the second input end of the fourth switch; the output end of the fourth switch is electrically connected with the gain adjusting circuit.
The application also provides a modulation calibration method, which is applied to the modulation calibration circuit, and the method comprises the following steps:
generating an I path calibration source and a Q path calibration source of a preset voltage amplitude value based on a calibration source generating circuit; respectively adjusting the bias voltage of the I path calibration source and the Q path calibration source through a direct current bias adjusting circuit to carry out local oscillator leakage calibration;
adjusting generation of different voltage amplitude combinations of the I path of calibration source and the Q path of calibration source based on the calibration source generation circuit; and adjusting the gain coefficients of the I path of calibration source and the Q path of calibration source which are combined by different voltage amplitudes to perform image frequency suppression calibration.
According to the modulation calibration method provided by the invention, the calibration source generation circuit generates an I path calibration source and a Q path calibration source with preset amplitude values; adjusting the bias voltage of the I-path calibration source and the Q-path calibration source through the direct current bias adjusting circuit respectively to carry out local oscillator leakage calibration, comprising:
generating an I path of calibration source and a Q path of calibration source with preset amplitude values based on a calibration source generating circuit;
respectively adjusting the bias voltages of the I path of calibration source and the Q path of calibration source to obtain a first alternative bias voltage of the I path of calibration source with the minimum detection voltage;
respectively adjusting the bias voltages of the I path of calibration source and the Q path of calibration source to obtain a second alternative bias voltage of the Q path of calibration source with the minimum detection voltage;
searching a first target bias voltage of an I-path calibration source with the minimum detection voltage around the first alternative bias voltage based on a dichotomy, and setting the bias voltage of the I-path calibration source as the first target bias voltage;
and searching a second target bias voltage of the Q-path calibration source with the minimum detection voltage around the second candidate bias voltage based on a dichotomy, and setting the bias voltage of the Q-path calibration source as the second target bias voltage.
According to the modulation calibration method provided by the invention, the calibration source generation circuit is used for adjusting the generation of different voltage amplitude combinations of the I-path calibration source and the Q-path calibration source; adjusting the gain coefficient of the I path calibration source and the Q path calibration source which are combined by different voltage amplitudes through the gain adjusting circuit to carry out image suppression calibration, comprising the following steps:
reading first detection power of an I path calibration source and a Q path calibration source of a calibration source generation circuit under the gains of a plurality of different gain adjusting circuits when the I path calibration source and the Q path calibration source are combined at a first preset voltage amplitude value;
reading second detection power under the gains of a plurality of different gain adjusting circuits when an I path calibration source and a Q path calibration source of the calibration source generating circuit are combined at a second preset voltage amplitude value;
calculating the difference between the second detection power and the first detection power with the same gain coefficient to obtain a plurality of first alternative values;
obtaining a first target value with the minimum value based on the plurality of first candidate values;
adjusting a gain of the gain adjustment circuit based on the first target value.
According to the modulation calibration method provided by the invention, the modulation calibration circuit further comprises a phase adjusting circuit electrically connected with the direct current offset adjusting circuit, and the phase adjusting circuit is used for adjusting local oscillator phases of the I path calibration source and the Q path calibration source;
the modulation calibration method further comprises:
adjusting generation of different voltage amplitude combinations of the I path of calibration source and the Q path of calibration source based on the calibration source generation circuit; and adjusting local oscillation phases of the I-path calibration source and the Q-path calibration source which are combined by different voltage amplitudes through the phase adjusting circuit to carry out local oscillation phase calibration.
According to the modulation calibration method provided by the invention, the calibration source generation circuit is used for adjusting the generation of different voltage amplitude combinations of the I-path calibration source and the Q-path calibration source; adjusting the local oscillation phase of the I-path calibration source and the Q-path calibration source of different voltage amplitude combinations through the phase adjusting circuit to perform local oscillation phase calibration, comprising:
reading third detection power of an I path calibration source and a Q path calibration source of the calibration source generating circuit under local oscillation phases of a plurality of different phase adjusting circuits when the I path calibration source and the Q path calibration source are combined at a third preset voltage amplitude value;
reading fourth detection power of the I path calibration source and the Q path calibration source of the calibration source generating circuit under local oscillation phases of a plurality of different phase adjusting circuits when the I path calibration source and the Q path calibration source are combined at a fourth preset voltage amplitude value;
calculating the difference between the fourth detection power and the third detection power of the same local oscillator phase to obtain a plurality of second alternative values;
obtaining a second target value with the minimum value based on the plurality of second candidate values;
adjusting a phase of the phase adjustment circuit based on the second target value.
The modulation calibration circuit provided by the invention generates an I path calibration source and a Q path calibration source which respectively comprise at least two voltages with different amplitudes through the calibration source generating circuit; respectively carrying out gain adjustment on the I path of calibration source and the Q path of calibration source through a gain adjustment circuit; and performing direct current bias adjustment on the I path calibration source and the Q path calibration source subjected to gain adjustment through a direct current bias adjustment circuit. And the I path calibration source and the Q path calibration source generated by the calibration source generating circuit are subjected to gain adjustment of the gain adjusting circuit so as to realize local oscillator leakage calibration. And after the direct current offset of the direct current offset adjusting circuit is adjusted, the image frequency suppression calibration is carried out. The invention directly detects the output of the IQ modulator, does not need to consider the interference on the detection result caused by the signal of the IQ baseband, only needs to refer to the relative change value of the detection voltage under the same local oscillation frequency in the calibration process, does not need to measure the absolute accuracy of the output signal of the IQ modulator, reduces the difficulty of circuit design, and can realize the self-closing loop calibration in the circuit.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is one of the circuit schematics of the modulation calibration circuit provided by the present invention;
FIG. 2 is a second schematic circuit diagram of the modulation calibration circuit provided in the present invention;
FIG. 3 is a third schematic circuit diagram of the modulation calibration circuit provided in the present invention;
FIG. 4 is a fourth schematic circuit diagram of the modulation calibration circuit provided in the present invention;
fig. 5 shows a schematic diagram of an ideal model of a prior art IQ-modulator;
FIG. 6 shows a schematic diagram of a prior IQ modulator model considering IQ amplitude, phase, and DC offset errors;
FIG. 7 is a schematic diagram of a local oscillator path model of an IQ modulator considering local oscillator amplitude, phase and DC offset errors;
FIG. 8 is a block flow diagram of a modulation calibration method provided by the present invention;
fig. 9 is a second flowchart of the modulation calibration method provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An ideal model of an IQ modulator is shown in fig. 5, local oscillator signal sin (w)Ct) generating two signals with 90-degree phase difference by a quadrature phase shift network and respectively supplying the two signals to two mixers, sin (w)Ct) phase change of 90 DEG into sin (w)Ct+pi/4)=-cos(wCt); i (t) way Signal and sin (w)Ct) mixing to produce I (t) sin (w)Ct, Q (t) signal and-cos (w)Ct) mixing to produce-Q (t) cos (w)Ct); and the two paths of signals are combined and output through the adder.
The relationship between the output and the input of the IQ modulator can be obtained by the above analysis of the ideal IQ modulator model:
In an actual circuit, an IQ signal input channel brings errors of gain, phase and direct current offset due to influences on links such as a DAC, a trace and an amplifier, and an IQ modulator model after considering the influences of the three is shown in fig. 6.
The IQ signal to the mixer, taking into account the gain error, phase error and dc offset, is:
In an actual circuit, a local oscillation signal passes through a phase shifter and an internal circuit of an IQ modulator, and errors of gain, phase and direct current misadjustment are brought, wherein phase errors are sin (w)Ct) phase is taken as reference, errors are all counted into one path of 90-degree phase shift, and an IQ modulator local oscillation path model is shown in FIG. 7 after the influence of the three paths is considered.
After considering the gain error, the phase error and the dc offset, the local oscillator signals to the mixer are:
At this time, the actual output signals after the frequency mixing of the two orthogonal signals and the adder are as follows:
(formula 6)
Multiplication of the terms in equation 6 yields:
(formula 7)
A little elaboration on equation 6 may result:
As can be seen from equation 6, the polynomial with the local oscillator signal and the IQ signal is equation 6, and the polynomial with the local oscillator signal and the IQ signal is the modulation signal in the actual output signal. Compared with the ideal signal formula 6, the local oscillator gain error (f) is
And
) Local oscillator phase error
IQ baseband gain error (
And
) IQ baseband phase error (
And
) The inconsistent part is the image frequency leakage.
As can be seen from equation 8, the polynomial with only local oscillator signals is equation 6, the signals expressed by the polynomial are local oscillator leakage in the actual output signals, and the local oscillator leakage is detuned by IQ baseband dc (IQ baseband dc) ((
And
) Local oscillator gain error (
And
) And local oscillator phase error
Influence.
As can be seen from equation 6, the polynomial with only baseband signals is equation 6, the signal of the polynomial expression is the baseband leakage in the actual output signal, and the baseband leakage is offset by the local oscillator dc (i.e., (ii) (i.e., the local oscillator dc offset)
And
) And IQ baseband gain error (
And
) Influence.
As can be seen from equation 6, the polynomial independent of both the local oscillator and the baseband is equation 6, and the signal of the polynomial expression is the dc component in the actual output signalThe magnitude of the DC component is offset by local oscillator DC (
And
) And IQ baseband DC offset (
And
) Influence.
Some mathematical models of sinusoidal operations need to be simulated before discussing the calibration of the IQ modulator.
Sine and cosine operations satisfy formula 6, so that it can be seen that after two paths of completely orthogonal signals are added, the amplitude becomes the root and mean square, and when a and b are arbitrarily combined only within ± 1, only the phase of the output signal is affected, and the amplitude of the output signal is not affected.
In order to actually observe the waveform and amplitude variation trend of the output signal, code simulation is carried out on the four operation situations. Supposing that two paths of signals are orthogonal sinusoidal signals yc and ys, when the two paths of signals are completely orthogonal and have no orthogonal phase error, addition and subtraction operation is carried out on the two paths of signals, the result shows that the actual output result is consistent with the theoretical calculation conclusion, the operation symbols only influence the phase of the output signals, and the amplitude is kept unchanged.
When two paths of orthogonal signals are not completely orthogonal and have a certain phase deviation, the two paths of orthogonal signals have
This time game
，
The method comprises the following steps:
Wherein the amplitude
Equation 6 can be derived.
Phase position
Comprises the following steps:
(formula 17)
When four combinations of a and b of ± 1 are considered in equation 6, the actual amplitude curve has only two cases, and waveform diagrams of the two cases are drawn through simulation, so that it can be seen that when a and b of equation 6 are combined to ± 1, the output amplitude is the same, and the phase may only be 0 or pi.
The calibration of the IQ modulator mainly aims at the image frequency leakage, the local oscillator leakage, the baseband leakage and the direct current component after the output of the IQ modulator. In the actual circuit design, because the baseband leakage frequency is low, a high-pass filter can be adopted to suppress the baseband leakage output by the IQ modulator; the output of the IQ modulator usually employs ac coupling because the dc component of the output of the IQ modulator caused by dc offset is filtered by the dc blocking capacitor. So what really needs to be calibrated to the IQ-modulator is mainly the image and local oscillator leakage.
Without considering the IQ modulator output dc offset, equation 8 can be simplified as:
From equation 6, it can be seen that the magnitude of the local oscillator leakage is offset by IQ baseband DC (
And
) Local oscillator gain error (
And
) And local oscillator phase error
Influence.
Let the I-path signal and the Q-path signal be 0V (time invariant) in equation 6, we can obtain:
In combination with equation 6, it can be known that the amplitude of the output signal of equation 6 after being detected is:
(formula 21)
At this time, by adjusting the DC offset of IQ baseband
And
at this time, the detection voltage is minimum through the IQ modulator. Considering that, in the actual circuit design, the IQ baseband dc offset may not be completely calibrated to 0, and the local oscillator quadrature phase error still needs to be further calibrated, so as to further reduce the local oscillator leakage.
After local oscillator leakage calibration, the output of the IQ modulator is further simplified as follows:
In equation 6, let the I-path signal and the Q-path signal be +1V, +1V and +1V, -1V, and can be obtained:
Adjust local oscillator phase difference, to
And
and under the condition that the voltages after signal detection are the same, the local oscillator quadrature phase error is 0 degree.
In equation 6, let the I-path signal and the Q-path signal be +1V, 0V, and +1V, which can be obtained:
At this time, fine adjustment is performed on the gain of IQ baseband
And
when the voltages after signal detection are the same, it can be considered that
。
Based on the creative thinking, by designing an accurate reference source as an IQ baseband signal, two voltages of 0V and +1V need to be realized in the path I, and three voltages of 0V, +1V and-1V need to be realized in the path Q. And designing a direct current offset adjusting circuit to carry out offset adjustment on the I path signal and the Q path signal so as to realize local oscillator leakage calibration. And designing a gain adjusting circuit to perform gain adjustment on the I path signal and the Q path signal so as to perform image frequency suppression calibration. The calibration mode can directly detect the output of the IQ modulator without considering the interference of the IQ baseband on the detection result when signals exist, and only the relative change value of the detection voltage under the same local oscillation frequency needs to be referred in the calibration process, the absolute accuracy of the output signals of the IQ modulator does not need to be measured, the difficulty of circuit design is reduced, and the self-closed loop calibration can be realized in the circuit.
Referring to fig. 1, a modulation calibration circuit 100 according to the present invention is described with reference to fig. 1 to 4, where the modulation calibration circuit 100 includes: a calibration source generating circuit 10, a gain adjusting circuit 20 and a DC offset adjusting circuit 30.
A calibration source generation circuit 10; the calibration source generating circuit 10 is configured to generate an I-path calibration source and a Q-path calibration source, where the I-path calibration source and the Q-path calibration source each include at least two voltages with different amplitudes; specifically, in one possible embodiment, the I-way calibration source includes voltages of both 0V and +1V magnitudes. The Q-path calibration source comprises three voltage amplitudes of 0V, +1V and-1V.
A gain adjustment circuit 20; the input end of the gain adjusting circuit 20 is electrically connected to the output end of the calibration source generating circuit 10, and is configured to perform gain adjustment on the I-path calibration source and the Q-path calibration source respectively; the specific gain adjustment circuit 20 includes a first sub-adjustment circuit 21 for performing gain adjustment on the I-path calibration source and a second sub-adjustment circuit 22 for performing gain adjustment on the Q-path calibration source.
And the input end of the direct current bias adjusting circuit 30 is electrically connected with the output end of the gain adjusting circuit 20, and is used for performing direct current bias adjustment on the I-path calibration source and the Q-path calibration source subjected to gain adjustment.
According to the modulation calibration circuit provided by the invention, an I-path calibration source and a Q-path calibration source which respectively comprise at least two voltages with different amplitudes are generated through a calibration source generating circuit 10; respectively carrying out gain adjustment on the I path calibration source and the Q path calibration source through a gain adjustment circuit 20; and performing dc offset adjustment on the I-path calibration source and the Q-path calibration source subjected to gain adjustment through a dc offset adjustment circuit 30. The I path calibration source and the Q path calibration source generated by the calibration source generating circuit 10 are subjected to gain adjustment by the gain adjusting circuit 20 to realize local oscillator leakage calibration. And after the dc offset adjustment of the dc offset adjustment circuit 30, the image frequency suppression calibration is performed. The invention directly detects the output of the IQ modulator, does not need to consider the interference on the detection result caused by the signal of the IQ baseband, only needs to refer to the relative change value of the detection voltage under the same local oscillation frequency in the calibration process, does not need to measure the absolute accuracy of the output signal of the IQ modulator, reduces the difficulty of circuit design, and can realize the self-closing loop calibration in the circuit.
Further, referring to fig. 2, the calibration source generating circuit 10 includes: the device comprises a band gap reference source module 11, an arithmetic circuit 12, a first switch 13, a second switch 14 and a power supply module 15.
A bandgap reference source module 11, wherein the bandgap reference source module 11 is used for generating a reference voltage. Specifically, the bandgap reference source module 11 may be any chip capable of generating a precise voltage output. In one possible embodiment, the bandgap reference source module 11 may be a model OPA735aid bvr chip manufactured by texas instruments. The band-gap reference source module 11 can generate a reference voltage of 2.048V, the voltage temperature stability can reach 3 ppm/DEG C, the precision can reach 0.05%, and the noise can reach 3 uVpp/V.
And an input end of the operational circuit 12 is electrically connected with an output end of the bandgap reference source module 11, and is configured to generate at least two voltages with different resistance values based on the reference voltage.
The operational circuit 12 may be designed by adopting a virtual ground of an operational amplifier, an input end of the operational amplifier is electrically connected to an output end of the bandgap reference source module 11, and the operational amplifier can simultaneously generate accurate voltage outputs of ± 1V and 0V. In order to reduce noise interference, the operational amplifier adopts a low-noise operational amplifier, the offset voltage of the low-noise operational amplifier is only 5uV at most, the temperature drift is 0.05 uV/DEG C at most, and the noise is less than 135 nV/root Hz.
It should be noted that, referring to fig. 3, the power supply terminals (i.e., the V + terminal, the V-terminal, and the VIN terminal in the figure) of the operation circuit 12 and the bandgap reference source module 11 adopt a derivative filter network to reduce power supply interference. Preferably, the operation circuit 12 and the bandgap reference source module 11 need to separately add a shielding box to reduce external interference.
Referring to fig. 4, an input terminal of the first switch 13 is electrically connected to an output terminal of the arithmetic circuit 12; for selecting an output voltage from the output of the arithmetic circuit 12 as the I-path calibration source. Specifically, the first switch 13 may be a one-out-of-three switch, the one-out-of-three switch may be powered by a dual power supply, the on-resistance is only 1 Ω, the control interface is controlled by 3.3V logic, the output may be rail-to-rail, and the current leakage does not exceed ± 10 nA. Since the I-path calibration source in this embodiment includes two voltages, 1V and 0V. Alternative switches may also be used in other embodiments.
A second switch 14; the input end of the second switch 14 is electrically connected with the output end of the arithmetic circuit 12; for selecting an output voltage from the output of the arithmetic circuit 12 as the Q-path calibration source. Specifically, the second switch 14 may be a one-out-of-three switch, the one-out-of-three switch may be powered by dual power supplies, the on-resistance is only 1 Ω, the control interface is controlled by 3.3V logic, the output may be rail-to-rail, and the current leakage does not exceed ± 10 nA.
It should be noted that the power supply terminals (i.e., VDD terminal and VSS terminal in the figure) of the first switch 13 and the second switch 14 adopt a pi filter network, so as to reduce power supply interference. Preferably, the first switch 13 and the second switch 14 need to separately add shielding boxes to reduce external interference.
And the power supply module 15 is electrically connected with the bandgap reference source module 11, the operational circuit 12, the first switch 13 and the second switch 14 respectively, and is configured to provide a stable power supply for the bandgap reference source module 11, the operational circuit 12, the first switch 13 and the second switch 14 respectively. Specifically, the power supply module 15 employs a voltage regulator chip, which may be a chip manufactured by texas instruments, model number TPS7a3901 DSCT. The voltage stabilizing chip can directly generate positive and negative double power supplies for power supply, can provide 150mA rated current, and can reach the suppression ratio of more than 50dB within the range of 1MHz in the power supply noise suppression ratio. The bandgap reference source module 11, the operation circuit 12, the first switch 13 and the second switch 14 can be supplied with a stable and low-noise power supply.
According to a modulation calibration circuit provided by the present invention, the gain adjustment circuit 20 includes: a first sub-adjustment circuit 21 for adjusting the gain of the I-path calibration source and a second sub-adjustment circuit 22 for adjusting the gain of the Q-path calibration source.
The first sub-regulation circuit 21 includes: a first multiplier 211 and a first adder 212.
A first input terminal of the first multiplier 211 is electrically connected to an output terminal of the calibration source generating circuit 10 for generating the I-path calibration source; a second input of the first multiplier 211 is arranged to receive a first gain adjustment signal.
A first input terminal of the first adder 212 is electrically connected to an output terminal of the first multiplier 211; a second input terminal of the first adder 212 is electrically connected to the output terminal of the calibration source generating circuit 10 for generating the I-path calibration source; the output terminal of the first adder 212 is electrically connected to the input terminal of the dc offset adjustment circuit 30.
It should be noted that the first gain adjustment signal is used to adjust the gain of the I-path calibration source. The first gain adjustment signal may be provided by a digital-to-analog conversion module 31. Taking the voltage of the I-path calibration source as x and the voltage of the first gain adjustment signal as y as an example, when the I-path calibration source passes through the first sub-adjustment circuit 21, the voltage output by the output terminal of the first sub-adjustment circuit 21 is x × y + x, and x × (y +1) is obtained by extracting a formula. As can be seen from x (y +1), by adjusting the voltage of the first gain adjustment signal, the gain of the I-path calibration source through the first sub-adjustment circuit 21 can be adjusted. Namely, the first sub-adjustment circuit 21 forms a voltage-controlled amplifier circuit by the first multiplier 211 and the first adder 212, so that the gain is continuously and accurately adjustable.
The second sub-regulation circuit 22 includes: a second multiplier 221 and a second adder 222.
A second multiplier 221; a first input terminal of the second multiplier 221 is electrically connected to an output terminal of the calibration source generation circuit 10 generating the Q-path calibration source; a second input of the second multiplier 221 is configured to receive a second gain adjustment signal.
A second adder 222; a first input terminal of the second adder 222 is electrically connected to an output terminal of the second multiplier 221; a second input terminal of the second adder 222 is electrically connected to the output terminal of the calibration source generation circuit 10 for generating Q calibration sources; the output terminal of the second adder 222 is electrically connected to the input terminal of the dc offset adjustment circuit 30.
It should be noted that the first gain adjustment signal is used to adjust the gain of the Q-path calibration source. The second gain adjustment signal may be provided by a digital to analog conversion module 31. The second sub-regulation circuit 22 has the same circuit structure as the first sub-regulation circuit 21, and similarly, the second sub-regulation circuit 22 forms a voltage-controlled amplifier circuit by the second multiplier 221 and the second adder 222, and also realizes continuous and accurate gain regulation.
According to the modulation calibration circuit provided by the present invention, the dc offset adjustment circuit 30 includes a digital-to-analog conversion module 31, a first differential amplifier 32, and a second differential amplifier 33.
A first input end of the first differential amplifier 32 is electrically connected to an output end of the first adder 212, and a second input end of the first differential amplifier 32 is electrically connected to a first dc voltage output end of the digital-to-analog conversion module 31.
A first input end of the second differential amplifier 33 is electrically connected to an output end of the second adder 222, and a second input end of the second differential amplifier 33 is electrically connected to a second dc voltage output end of the digital-to-analog conversion module 31.
Specifically, in order to prevent interference to the I-path calibration source and the Q-path calibration source, the first differential amplifier 32 and the second differential amplifier 33 use a first-stage differential amplifier as a buffer, the gain of the first-stage differential amplifier is designed to be 1, the common-mode voltage is 0V and is not adjustable, and the first-stage differential amplifier and the second differential amplifier have enable control pins which can directly turn off the outputs of the I-path calibration source and the Q-path calibration source. In order to provide as many DAC channels as possible to the first sub-regulation circuit 21, the second sub-regulation circuit 22, the first differential amplifier 32 and the second differential amplifier 33. In a feasible embodiment, the digital-to-analog conversion module 31 can meet the use requirement by adopting a digital-to-analog conversion chip DAC with 16 channels, and the digital-to-analog conversion module 31 adopts a single power supply +5V for power supply and is internally provided with a reference source. The digital-to-analog conversion module 31 can output a dc voltage of 0 to 5V, and limit the dc voltage required by each channel through the external voltage-dividing resistor, thereby realizing control functions of gain, common mode voltage, and the like, and performing dc bias adjustment on the I-path calibration source and the Q-path calibration source. The digital-to-analog conversion module 31 may be a chip manufactured by idenay semiconductor corporation under model LTC2668IUJ-I2 HPEF.
In other aspects of the invention, the modulation calibration circuit further comprises a third switch 40 and a fourth switch 50.
The third switch 40 comprises a first input for inputting an external IQ signal; a second input terminal for inputting the I-path calibration source and the Q-path calibration source generated by the calibration source generating circuit 10; and an output for performing an alternative output to a first input of the third switch 40 and a second input of the third switch 40.
The fourth switch 50 includes a first input end electrically connected to the output end of the third switch 40, a second input end for inputting the internal IQ signal, and an output end for performing one-out-of-two output on the first input end of the fourth switch 50 and the second input end of the fourth switch 50; the output terminal of the fourth switch 50 is electrically connected to the gain adjusting circuit 20.
By controlling the on and off states of the third switch 40 and the fourth switch 50, a signal can be selected from the external IQ signal, the calibration source generation circuit 10, and the internal IQ signal for calibration. For example, it is desirable to select the signal of the calibration source generating circuit 10 for calibration, so that the third switch 40 selectively turns on the signal generated by the calibration source generating circuit 10 and turns off the path of the external IQ signal; and make the fourth switch 50 selectively turn on the signal generated by the calibration source generating circuit 10 outputted by the third switch 40, and turn off the path of the internal IQ signal; thereby selecting the signal of the calibration source generating circuit 10 for calibration.
In the embodiment of the present invention, the third switch 40 and the fourth switch 50 are arranged to form a two-stage switch to realize the IQ data source switching, and the switching can be performed among the external IQ signal input, the calibration source input, and the internal IQ signal input. Therefore, the embodiment of the invention can realize the calibration of the multi-path IQ signals.
It should be noted that the fourth switch 50 of the embodiment of the present invention further includes three identical outputs, and each output is buffered by the third differential amplifier 34 with a gain of 1. Wherein, the two paths are respectively used as a high-band IQ modulator baseband drive and a low-band IQ modulator baseband drive; and the other path is used as a reserved IQ baseband. The digital-to-analog conversion module 31 supplies a dc voltage of 0 to 5V to each of the third differential amplifiers 34.
The application also provides a modulation calibration method which is applied to the modulation calibration circuit. Because the baseband leakage frequency in the actual circuit design is lower, a high-pass filter can be adopted to inhibit the baseband leakage output by the IQ modulator; the output of the IQ modulator usually employs ac coupling because the dc component of the output of the IQ modulator caused by dc offset is filtered by the dc blocking capacitor. So what really needs to be calibrated to the IQ-modulator is mainly the image and local oscillator leakage. The modulation calibration method of the embodiment realizes local oscillator leakage calibration and image frequency suppression calibration through the modulation calibration circuit.
Referring to fig. 8, a modulation calibration method according to an embodiment of the present invention is applied to the modulation calibration circuit, and the modulation calibration method includes:
according to the modulation calibration method provided by the invention, the calibration source generation circuit 10 generates an I path calibration source and a Q path calibration source with preset amplitudes; adjust respectively I way calibration source and Q way calibration source carry out local oscillator leakage calibration through the bias voltage of direct current offset regulating circuit 30, include:
step 110, generating an I path calibration source and a Q path calibration source with preset amplitudes based on the calibration source generating circuit 10;
step 120, respectively adjusting the bias voltages of the I path calibration source and the Q path calibration source to obtain a first alternative bias voltage of the I path calibration source with the minimum detection voltage;
step 130, respectively adjusting the bias voltages of the I path calibration source and the Q path calibration source to obtain a second alternative bias voltage of the Q path calibration source with the minimum detection voltage;
step 140, searching a first target bias voltage of an I-path calibration source with the minimum detection voltage around the first candidate bias voltage based on a dichotomy, and setting the bias voltage of the I-path calibration source as the first target bias voltage;
and 150, searching a second target bias voltage of the Q-path calibration source with the minimum detection voltage around the second candidate bias voltage based on a dichotomy, and setting the bias voltage of the Q-path calibration source as the second target bias voltage.
Specifically, in a possible embodiment, the calibration process of the local oscillator leakage calibration specifically includes the following steps:
step 1001, controlling the on-off of the third switch 40 and the fourth switch, and selecting an IQ data source as an I-path calibration source and a Q-path calibration source generated by the calibration source generation circuit 10;
step 1002, setting the voltage of the I path of calibration source to be 0 and the voltage of the Q path of calibration source to be 0;
step 1003, setting bias voltage Bp = Vref of the Q-path calibration source;
step 1004, setting the bias voltage of the I-path calibration source from Vmin to Vmax, stepping to (Vmin-Vmax)/20, and reading the detection voltage Pin corresponding to the bias voltage of each I-path calibration source;
step 1005, searching the minimum value in the detection voltages Pin of the multiple I-path calibration sources, and setting a first alternative bias voltage Bi = Vin of the I-path calibration source; vin is an offset voltage corresponding to the minimum value of the detected voltages Pin (i.e., the first alternative offset voltage);
step 1006, setting the bias voltage of the Q-path calibration source from Vmin to Vmax, stepping to (Vmin-Vmax)/20, and reading a detection voltage Pqn corresponding to the bias voltage of each Q-path calibration source;
step 1007, searching the minimum value of the detection voltages Pqn of the Q-path calibration sources, and setting a second alternative bias voltage Bq = Vqn of the Q-path calibration sources; vqn is the bias voltage corresponding to the minimum value of detected voltage Pqn (i.e. the second alternative bias voltage);
step 1008, setting the bias voltage Bi of the I-path calibration source from Vi (n-1) to Vi (n +1) through a dichotomy, and searching a first target bias voltage Bimin corresponding to the minimum value Pimin in the detection voltage; setting bias voltage Bi = Bimin of the I path calibration source;
step 1009, setting the bias voltage Bq of the Q-path calibration source from Vq (n-1) to Vq (n +1) by a dichotomy, and searching for a second target bias voltage Bqmin corresponding to the minimum value Pqmin in the detection voltage; and setting bias voltage Bq = Bqmin of the Q-path calibration source.
Based on the above steps 1001 and 1009, local oscillator leakage calibration may be performed on the I-path calibration source and the Q-path calibration source of the calibration source generation circuit 10.
Where Vref denotes a reference voltage of the bias voltage of the Q-way calibration source, Vi (n-1) denotes a value of the bias voltage one time before (i.e., n-1 th time) the first candidate bias voltage Bi = Vin, and Vi (n +1) denotes a value of the bias voltage one time after (i.e., n +1 th time) the first candidate bias voltage Bi = Vin.
Specifically, step 300, the calibration-source-based generation circuit 10 adjusts the generation of different voltage amplitude combinations of the I-path calibration source and the Q-path calibration source; adjusting the gain coefficients of the I path calibration source and the Q path calibration source of different voltage amplitude combinations through the gain adjusting circuit 20 to perform image rejection calibration, including:
step 310, reading first detection powers of the I path calibration source and the Q path calibration source of the calibration source generation circuit 10 under the gains of the plurality of different gain adjustment circuits 20 when the first preset voltage amplitude is combined;
the first preset voltage amplitude combination refers to voltages of the I-path calibration source and the Q-path calibration source, which are preset, for example, the I-path calibration source is preset to be 1V, and the Q-path calibration source is preset to be 0V.
Step 320, reading second detection powers of the I path calibration source and the Q path calibration source of the calibration source generation circuit 10 under the gains of the plurality of different gain adjustment circuits 20 when the I path calibration source and the Q path calibration source are combined at a second preset voltage amplitude value;
similarly, the second preset voltage amplitude combination refers to preset voltages of the I-path calibration source and the Q-path calibration source, for example, the I-path calibration source may be preset to 0V, and the Q-path calibration source may be preset to 1V.
Step 330, calculating the difference between the second detection power and the first detection power with the same gain coefficient to obtain a plurality of first alternative values;
step 340, obtaining a first target value with the minimum value based on the plurality of first candidate values;
step 350, adjusting the gain of the gain adjustment circuit 20 based on the first target value.
A first target value with the smallest value is obtained based on the plurality of first candidate values, and the gain of the gain adjusting circuit 20 is adjusted based on the first target value. Specifically, the gain of the gain adjusting circuit 20 can be adjusted by adjusting the first gain adjusting signal and the second gain adjusting signal output to the gain adjusting circuit 20 by the digital-to-analog converting module 31 in the modulation calibration circuit.
Specifically, in one possible embodiment, the calibration procedure of the image rejection calibration is as follows:
step 3001, setting the voltage of the I path calibration source to be 1 and the voltage of the Q path calibration source to be 0;
step 3002, setting the gain coefficient of the I path calibration source to 1, and the gain coefficient of the Q path calibration source to 1;
step 3003, reading the detection power P11;
step 3004, setting the gain coefficient of the I path calibration source to 1+ Delta Gi;
step 3005, reading the detection power P12;
step 3006, setting the gain coefficient of the I path calibration source to 1-delta Gi;
step 3007, reading the detection power P13;
step 3008, setting the gain coefficient of the I-path calibration source to 0 and the gain coefficient of the Q-path calibration source to 1;
step 3009, setting the gain coefficient of the I-path calibration source to 1;
step 3010, read the detection power P21 at this time;
step 3011, setting the gain coefficient of the I-path calibration source to 1+ [ delta ] Gi;
step 3012, read the detection power P22 at this time;
step 3013, setting the gain coefficient of the I-path calibration source to 1-delta Gi;
step 3014, read the detection power P23 at this time;
step 3015, calculating Δ P1= P21-P11; Δ P2= P22-P12; selecting the smaller value of delta P1, delta P2 and delta P3 to determine the smaller value as a gain adjustment direction (or called a first target value);
in step 3016, the gain of the gain adjustment circuit 20 is adjusted along the gain adjustment direction (or the first target value) until the detected detection power is minimum. The image rejection calibration can be performed on the I-path calibration source and the Q-path calibration source through the above step 3001.
Where Δ Gi refers to a gain control voltage that the digital-to-analog conversion module 31 controls the output. The gain factor of the I-path calibration source and the gain factor of the Q-path calibration source can be changed by the digital-to-analog conversion module 31, respectively.
Referring to fig. 9, in another aspect of the present invention, the modulation calibration circuit further includes a phase adjustment circuit (not shown) electrically connected to the dc offset adjustment circuit 30, and the phase adjustment circuit is configured to adjust local oscillation phases of the I-path calibration source and the Q-path calibration source;
the modulation calibration method further comprises:
Some modulators with phase adjustment circuits (such as ADRF6780, model of Adenon semiconductor technologies, Inc.) have some digital step-by-step local oscillator phase adjustment capability, which allows local oscillator phase calibration.
step 210, reading third detection powers of the I path calibration source and the Q path calibration source of the calibration source generation circuit 10 under the local oscillation phases of the plurality of different phase adjustment circuits when the I path calibration source and the Q path calibration source are combined at a third preset voltage amplitude;
the third preset voltage amplitude combination refers to voltages of the I-path calibration source and the Q-path calibration source, which are preset, for example, the I-path calibration source is preset to be 1V, and the Q-path calibration source is preset to be 1V.
Step 220, reading fourth detection power of the I path calibration source and the Q path calibration source of the calibration source generation circuit 10 under the local oscillation phases of the multiple different phase adjusting circuits when the I path calibration source and the Q path calibration source are combined at a fourth preset voltage amplitude value;
the fourth preset voltage amplitude combination refers to voltages of the I-path calibration source and the Q-path calibration source, which are preset, for example, the I-path calibration source is preset to 1V, and the Q-path calibration source is preset to-1V.
Step 230, calculating the difference between the fourth detection power and the third detection power of the same local oscillator phase to obtain a plurality of second alternative values;
step 240, obtaining a second target value with the minimum value based on the plurality of second candidate values;
step 250, adjusting the phase of the phase adjustment circuit based on the second target value.
A second target value with the smallest value is obtained based on the plurality of second candidate values, and the gain of the gain adjusting circuit 20 is adjusted based on the second target value.
Specifically, in a possible embodiment, the calibration process of the local oscillator phase calibration specifically includes the following steps:
step 2001, setting the voltage of the I path calibration source to be 1 and the voltage of the Q path calibration source to be 1;
step 2002, adjusting the local oscillation phase of the Q-path calibration source to be 0;
step 2003, adjusting the local oscillation phase of the I path calibration source to be 0;
step 2004, reading the detection power P11;
step 2005, adjusting the local oscillation phase of the Q-path calibration source to 1;
step 2006, adjusting the local oscillation phase of the I path calibration source to 0;
step 2007, reading the detection power P12;
step 2008, setting the gain coefficient of the I path calibration source as 1 and the gain coefficient of the Q path calibration source as-1;
step 2009, adjusting the local oscillation phase of the Q-path calibration source to 0;
step 2010, adjusting the local oscillator phase of the I path calibration source to be 0;
step 2011, reading the detection power P21;
step 2012, adjusting the local oscillation phase of the Q-path calibration source to 1;
step 2013, adjusting the local oscillator phase of the I-path calibration source to be 0;
step 2014, reading the detection power P22;
step 2015, calculating Δ P1= P21-P11; Δ P2= P22-P12; selecting the smaller value of the delta P1 and the delta P2 to determine the smaller value as a local oscillation phase adjusting direction (or called as a second target value);
step 2016, adjust the phase of the phase adjusting circuit along the local oscillator phase adjusting direction (or called the second target value) until the detected detection power is minimum.
The local oscillation phase calibration can be performed on the I-path calibration source and the Q-path calibration source through the steps 2001-2016.
Thereby generating an I-path calibration source and a Q-path calibration source each including at least two voltages of different magnitudes by the calibration source generating circuit 10; respectively carrying out gain adjustment on the I path calibration source and the Q path calibration source through a gain adjustment circuit 20; and performing dc offset adjustment on the I-path calibration source and the Q-path calibration source subjected to gain adjustment through a dc offset adjustment circuit 30. The I path calibration source and the Q path calibration source generated by the calibration source generating circuit 10 are subjected to gain adjustment by the gain adjusting circuit 20 to realize local oscillator leakage calibration. And after the dc offset adjustment of the dc offset adjustment circuit 30, the image frequency suppression calibration is performed. The invention directly detects the output of the IQ modulator, does not need to consider the interference on the detection result caused by the signal of the IQ baseband, only needs to refer to the relative change value of the detection voltage under the same local oscillation frequency in the calibration process, does not need to measure the absolute accuracy of the output signal of the IQ modulator, reduces the difficulty of circuit design, and can realize the self-closing loop calibration in the circuit.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A modulation calibration circuit, comprising:
a calibration source generation circuit; the calibration source generating circuit is used for generating an I path of calibration source and a Q path of calibration source, and the I path of calibration source and the Q path of calibration source respectively comprise at least two voltages with different amplitudes;
a gain adjustment circuit; the input end of the gain adjusting circuit is electrically connected with the output end of the calibration source generating circuit and is used for respectively carrying out gain adjustment on the I-path calibration source and the Q-path calibration source; and
and the input end of the direct current bias adjusting circuit is electrically connected with the output end of the gain adjusting circuit and is used for carrying out direct current bias adjustment on the I-path calibration source and the Q-path calibration source which are subjected to gain adjustment.
2. The modulation calibration circuit of claim 1, wherein the calibration source generation circuit comprises:
a bandgap reference source module for generating a reference voltage;
the input end of the operational circuit is electrically connected with the output end of the band-gap reference source module and is used for generating at least two voltages with different resistance values based on the reference voltage;
a first switch; the input end of the first switch is electrically connected with the output end of the operational circuit; the I-path calibration source is used for selecting one output voltage from the output end of the operational circuit as the I-path calibration source;
a second switch; the input end of the second switch is electrically connected with the output end of the operational circuit; the output end of the operational circuit is used for selecting an output voltage as the Q-path calibration source; and
and the power supply module is electrically connected with the band gap reference source module, the operation circuit, the first switch and the second switch respectively.
3. The modulation calibration circuit of claim 2,
the gain adjustment circuit includes: a first sub-regulation circuit and a second sub-regulation circuit;
the first sub-regulation circuit includes:
a first multiplier; the first input end of the first multiplier is electrically connected with the output end of the I-path calibration source generated by the calibration source generating circuit; a second input of the first multiplier is configured to receive a first gain adjustment signal;
a first adder; a first input end of the first adder is electrically connected with an output end of the first multiplier; the second input end of the first adder is electrically connected with the output end of the I-path calibration source generated by the calibration source generating circuit; the output end of the first adder is electrically connected with the input end of the direct current offset adjusting circuit;
the second sub-regulation circuit includes:
a second multiplier; the first input end of the second multiplier is electrically connected with the output end of the Q-path calibration source generated by the calibration source generating circuit; a second input of the second multiplier is for receiving a second gain adjustment signal;
a second adder; a first input end of the second adder is electrically connected with an output end of the second multiplier; a second input end of the second adder is electrically connected with an output end of the calibration source generating circuit generating the Q-path calibration source; the output end of the second adder is electrically connected with the input end of the direct current offset adjusting circuit.
4. The modulation calibration circuit of claim 3, wherein the DC offset adjustment circuit comprises a digital-to-analog conversion module, a first differential amplifier and a second differential amplifier;
a first input end of the first differential amplifier is electrically connected with an output end of the first adder, and a second input end of the first differential amplifier is electrically connected with a first direct-current voltage output end of the digital-to-analog conversion module;
the first input end of the second differential amplifier is electrically connected with the output end of the second adder, and the second input end of the second differential amplifier is electrically connected with the second direct-current voltage output end of the digital-to-analog conversion module.
5. The modulation calibration circuit of claim 1, further comprising a third switch and a fourth switch;
the third switch comprises a first input terminal for inputting an external IQ signal; a second input end for inputting the I-path calibration source and the Q-path calibration source generated by the calibration source generating circuit; and an output for performing an alternative output to the first input of the third switch and the second input of the third switch;
the fourth switch comprises a first input end electrically connected with the output end of the third switch, a second input end used for inputting an internal IQ signal, and an output end used for carrying out one-out-of-two output on the first input end of the fourth switch and the second input end of the fourth switch; the output end of the fourth switch is electrically connected with the gain adjusting circuit.
6. A modulation calibration method applied to the modulation calibration circuit according to any one of claims 1 to 5, the method comprising:
generating an I path calibration source and a Q path calibration source of a preset voltage amplitude value based on a calibration source generating circuit; respectively adjusting the bias voltage of the I path calibration source and the Q path calibration source through a direct current bias adjusting circuit to carry out local oscillator leakage calibration;
adjusting generation of different voltage amplitude combinations of the I path of calibration source and the Q path of calibration source based on the calibration source generation circuit; and adjusting the gain coefficients of the I path of calibration source and the Q path of calibration source which are combined by different voltage amplitudes to perform image frequency suppression calibration.
7. The modulation calibration method according to claim 6, wherein the calibration source-based generation circuit generates an I-path calibration source and a Q-path calibration source of a preset amplitude; adjusting the bias voltage of the I-path calibration source and the Q-path calibration source through the direct current bias adjusting circuit respectively to carry out local oscillator leakage calibration, comprising:
generating an I path of calibration source and a Q path of calibration source with preset amplitude values based on a calibration source generating circuit;
respectively adjusting the bias voltages of the I path of calibration source and the Q path of calibration source to obtain a first alternative bias voltage of the I path of calibration source with the minimum detection voltage;
respectively adjusting the bias voltages of the I path of calibration source and the Q path of calibration source to obtain a second alternative bias voltage of the Q path of calibration source with the minimum detection voltage;
searching a first target bias voltage of an I-path calibration source with the minimum detection voltage around the first alternative bias voltage based on a dichotomy, and setting the bias voltage of the I-path calibration source as the first target bias voltage;
and searching a second target bias voltage of the Q-path calibration source with the minimum detection voltage around the second candidate bias voltage based on a dichotomy, and setting the bias voltage of the Q-path calibration source as the second target bias voltage.
8. The modulation calibration method according to claim 6, wherein the calibration source generation based circuit adjusts generation of different voltage amplitude combinations of the I-path calibration source and the Q-path calibration source; adjusting the gain coefficient of the I path calibration source and the Q path calibration source which are combined by different voltage amplitudes through the gain adjusting circuit to carry out image suppression calibration, comprising the following steps:
reading first detection power of an I path calibration source and a Q path calibration source of a calibration source generation circuit under the gains of a plurality of different gain adjusting circuits when the I path calibration source and the Q path calibration source are combined at a first preset voltage amplitude value;
reading second detection power under the gains of a plurality of different gain adjusting circuits when an I path calibration source and a Q path calibration source of the calibration source generating circuit are combined at a second preset voltage amplitude value;
calculating the difference between the second detection power and the first detection power with the same gain coefficient to obtain a plurality of first alternative values;
obtaining a first target value with the minimum value based on the plurality of first candidate values;
adjusting a gain of the gain adjustment circuit based on the first target value.
9. The modulation calibration method according to claim 6, wherein the modulation calibration circuit further comprises a phase adjustment circuit electrically connected to the dc offset adjustment circuit, the phase adjustment circuit being configured to adjust local oscillation phases of the I-path calibration source and the Q-path calibration source;
the modulation calibration method further comprises:
adjusting generation of different voltage amplitude combinations of the I path of calibration source and the Q path of calibration source based on the calibration source generation circuit; and adjusting local oscillation phases of the I-path calibration source and the Q-path calibration source which are combined by different voltage amplitudes through the phase adjusting circuit to carry out local oscillation phase calibration.
10. The modulation calibration method according to claim 9, wherein the calibration source generation based circuit adjusts generation of different voltage amplitude combinations of the I-path calibration source and the Q-path calibration source; adjusting the local oscillation phase of the I-path calibration source and the Q-path calibration source of different voltage amplitude combinations through the phase adjusting circuit to perform local oscillation phase calibration, comprising:
reading third detection power of an I path calibration source and a Q path calibration source of the calibration source generating circuit under local oscillation phases of a plurality of different phase adjusting circuits when the I path calibration source and the Q path calibration source are combined at a third preset voltage amplitude value;
reading fourth detection power of the I path calibration source and the Q path calibration source of the calibration source generating circuit under local oscillation phases of a plurality of different phase adjusting circuits when the I path calibration source and the Q path calibration source are combined at a fourth preset voltage amplitude value;
calculating the difference between the fourth detection power and the third detection power of the same local oscillator phase to obtain a plurality of second alternative values;
obtaining a second target value with the minimum value based on the plurality of second candidate values;
adjusting a phase of the phase adjustment circuit based on the second target value.
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| CN115913274B (en) * | 2023-02-08 | 2023-05-30 | 上海芯浦科技有限公司 | Method for eliminating local signal of transmitter |
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