CN114050137A

CN114050137A - Semiconductor package device and method of manufacturing the same

Info

Publication number: CN114050137A
Application number: CN202111187413.1A
Authority: CN
Inventors: 方绪南
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-10-12
Filing date: 2021-10-12
Publication date: 2022-02-15

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a first electronic component; the second electronic element is arranged on the first electronic element, the width of the second electronic element is smaller than that of the first electronic element, a conductive pad is arranged on the first electronic element in a region which is not covered by the second electronic element, a first circuit layer is arranged on the conductive pad, and a joint region exists between the conductive pad and the first circuit layer. The semiconductor packaging device can utilize the first circuit layer to lead out the electric signals in the first electronic element, and a conductive column does not need to be directly manufactured on the first electronic element, so that the yield of products is improved.

Description

Semiconductor package device and method of manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.

Background

When a chip (Die) and a Wafer (Wafer) are subjected to Hybrid Bonding (Hybrid Bonding), a high-conductivity Pillar (Tall Pillar) is generally used to conduct electrical signals in the structure to the outside. The manufacturing method of the conductive pillars can be divided into two methods, namely, firstly manufacturing the conductive pillars (pilar First) and then manufacturing the conductive pillars (pilar Last).

The First fabrication of the conductive Pillar (pilar First) means that the conductive Pillar is fabricated before the hybrid bonding of the chip and the wafer. The specific manufacturing process of the conductive column comprises the following steps: the surface of the wafer is first subjected to Chemical Mechanical Polishing (CMP), then coated with photoresist, exposed to light to form openings, and finally plated to form conductive pillars. In the above manner, the roughness of the Bonding Area (Bonding Area) is increased by setting the photoresist and removing the seed layer of the electroplating, and in a serious case, the hybrid Bonding cannot be performed.

Post-fabrication of the conductive pillars (Pillar Last) refers to fabricating the conductive pillars after the hybrid bonding of the chip and the wafer. This approach can avoid increasing the roughness of the bonding area, but it is necessary to coat the wafer surface with the chip. Due to the existence of the chip, the flatness of the surface of the wafer cannot meet the requirement of photoresist coating, so that the photoresist cannot be uniformly coated, and the fabrication of the conductive post cannot be carried out.

Therefore, a new technical solution is needed to solve at least one of the above technical problems.

Disclosure of Invention

The present disclosure provides a semiconductor package device and a method of manufacturing the same.

In a first aspect, the present disclosure provides a semiconductor package device, comprising:

a first electronic component;

the second electronic element is arranged on the first electronic element, the width of the second electronic element is smaller than that of the first electronic element, a conductive pad is arranged on a region, which is not covered by the second electronic element, of the first electronic element, a first circuit layer is arranged on the conductive pad, and a joint region exists between the conductive pad and the first circuit layer.

In some alternative embodiments, a connection structure is disposed between the conductive pad and the first circuit layer, and the connection structure and the conductive pad form the joint region therebetween.

In some alternative embodiments, an intermetallic layer is present between the connection structure and the conductive pad.

In some alternative embodiments, a connection structure is disposed between the conductive pad and the first circuit layer, and the connection structure and the first circuit layer form the joint region therebetween.

In some alternative embodiments, an intermetallic layer is present between the connection structure and the first line layer.

In some alternative embodiments, the upper surface of the first circuit layer and the upper surface of the second electronic element are flush.

In some optional embodiments, a second circuit layer is disposed on the first circuit layer.

In some optional embodiments, the first circuit layer includes conductive pillars.

In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:

directly bonding a first electronic element and a second electronic element, wherein the width of the second electronic element is smaller than the width of the first electronic element;

arranging a prefabricated first circuit layer on the first electronic element in an area which is not covered by the second electronic element, wherein the thickness of the first circuit layer is greater than or equal to that of the second electronic element;

and forming a second circuit layer on the first circuit layer to obtain the semiconductor packaging device.

In some optional embodiments, the disposing a prefabricated first circuit layer on the first electronic component in an area not covered by the second electronic component includes:

providing a dummy chip, wherein a conductive post is arranged on the dummy chip;

flip-chip bonding the dummy chip to an area of the first electronic component not covered by the second electronic component.

In some optional embodiments, after flip-chip bonding the dummy chip to an area of the first electronic component not covered by the second electronic component, the method further comprises:

removing a portion of the structure of the dummy chip to expose the first line.

In some optional embodiments, the removing the partial structure of the dummy chip to expose the first line includes:

the dummy chip is ground to expose the first line.

In some optional embodiments, after providing a prefabricated first circuit layer on the first electronic component in an area not covered by the second electronic component, the method further comprises:

disposing a capillary underfill material and a mold material over the first electronic component; or

A molded underfill material is disposed over the first electronic component.

In some optional embodiments, the forming a second circuit layer on the first circuit layer comprises:

and forming a rewiring layer on the first circuit layer.

In the semiconductor packaging device and the manufacturing method thereof provided by the disclosure, the first circuit layer is arranged in the area which is not covered by the second electronic element on the first electronic element, so that the electric signal in the first electronic element can be led out by using the first circuit layer without directly manufacturing the conductive column on the first electronic element, the problem that the conductive column for external connection in hybrid bonding is difficult to manufacture is solved, and the product yield is improved.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1-3 are first through third schematic views of a semiconductor package device according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a method of manufacturing a semiconductor package device according to an embodiment of the present disclosure.

Description of the symbols:

100. a first electronic component; 110. a first conductive pad; 130. a third conductive pad; 200. a second electronic component; 210. a second conductive pad; 310. a first circuit layer; 311. a conductive post; 320. a second circuit layer; 410. a capillary underfill material; 420. molding the material; 500. a conductive ball; 600. a substrate; 700. an electrical connection wire; 800. a dummy chip; 900. and (5) a connecting structure.

Detailed Description

The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.

It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

It should be readily understood that the meaning of "in.. on," "over,", and "above" in this disclosure should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.

Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used in this disclosure to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly as such.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

The embodiment of the disclosure provides a semiconductor packaging device. Fig. 1-3 are first to third schematic views of a semiconductor package device according to an embodiment of the present disclosure.

Fig. 1 shows a longitudinal cross section of a semiconductor package device according to an embodiment of the present disclosure. As shown in fig. 1, the semiconductor package device includes a first electronic component 100 and a second electronic component 200. The second electronic component 200 is disposed on the first electronic component 100. The width of the second electronic component 200 is smaller than the width of the first electronic component 100.

As shown in fig. 1, a first conductive pad 110 is disposed on a surface of the first electronic component 100, and a second conductive pad 210 is disposed on a surface of the second electronic component 200. The first conductive pad 110 and the corresponding second conductive pad 210 are directly coupled to achieve an electrical connection between the first electronic component 100 and the second electronic component 200. In addition, the dielectric material on the surface of the first electronic component 100 and the corresponding dielectric material on the surface of the second electronic component 200 are directly bonded (not shown in fig. 1).

As shown in fig. 1, a third conductive pad 130 is disposed on a region of the first electronic component 100 not covered by the second electronic component 200. The third conductive pad 130 is disposed with a first circuit layer 310. The first circuit layer 310 includes a molding material 420 and a plurality of conductive pillars 311 disposed in the molding material 420. The third conductive pad 130 and the conductive pillar 311 in the first circuit layer 310 are connected by the connection structure 900, so as to form a bonding region. The connection structure 900 may be solder, that is, the third conductive pad 130 and the conductive post 311 may be connected by soldering. Further, an intermetallic compound layer (not shown in fig. 1) formed by soldering may exist between the third conductive pad 130 and the connection structure 900.

As shown in fig. 1, the upper surface of the first circuit layer 310 is flush with the upper surface of the second electronic component 200. A second circuit layer 320 is also disposed on the first circuit layer 310 and the first electronic component 100. The second circuit Layer 320 is, for example, a Redistribution Layer (RDL), the surface of the second circuit Layer 320 is further provided with conductive balls 500, in the semiconductor package device shown in fig. 1, the electrical signals in the first electronic element 100 and the second electronic element 200 are conducted to the second circuit Layer 320 through the first circuit Layer 310, and then conducted to the external element through the conductive balls 500 on the surface of the second circuit Layer 320.

As shown in fig. 1, a capillary underfill material 410 is further disposed between the first electronic component 100 and the second electronic component 200 and between the first electronic component 100 and the first circuit layer 310 to fill the gap in the above-mentioned portion, so as to improve the structural strength.

The semiconductor package device of fig. 1 may be further electrically connected to a substrate to achieve more complete and various functions. Fig. 2 and 3 respectively show different ways in which a semiconductor package device according to an embodiment of the present disclosure is connected to a substrate.

In fig. 2, the semiconductor package device described above may be electrically connected to the substrate 600 through the conductive balls 500, which may be manufactured using a Flip Chip (Flip Chip) process. The material of the substrate 600 may be a polymer material, ceramic, glass, or the like, which is not limited in the present disclosure.

In fig. 3, the semiconductor package device described above can be electrically connected to the substrate 600 through the electrical connection wires 700, which can be formed by Wire Bonding (Wire Bonding). The material of the substrate 600 may be a polymer material, ceramic, glass, or the like, which is not limited in the present disclosure.

In the semiconductor package device provided by the present disclosure, the first circuit layer 310 is disposed in the area of the first electronic element 100 not covered by the second electronic element 200, so that the first circuit layer 310 can be used to lead out the electrical signal in the first electronic element 100, and the conductive pillar 311 does not need to be directly fabricated on the first electronic element 100, thereby overcoming the problem of difficulty in fabricating the conductive pillar 311 for external connection in hybrid bonding, and facilitating the improvement of the product yield.

The embodiment of the disclosure also provides a manufacturing method of the semiconductor packaging device. Fig. 4 is a schematic diagram of a method of manufacturing a semiconductor package device according to an embodiment of the present disclosure.

As shown in fig. 4, the method comprises the steps of:

first, as shown in the first step of fig. 4, the first electronic component 100 and the second electronic component 200 are directly bonded, wherein the width of the second electronic component 200 is smaller than the width of the first electronic component 100.

Next, as shown in the second and third steps of fig. 4, a prefabricated first wiring layer 310 is provided on the first electronic component 100 in an area not covered by the second electronic component 200, wherein the thickness of the first wiring layer 310 is greater than or equal to the thickness of the second electronic component 200.

Finally, as shown in the fourth step of fig. 4, a second circuit layer 320 is formed on the first circuit layer 310 to obtain the semiconductor package device.

In some embodiments, the step of disposing the first circuit layer 310 may further include: first, as shown in the second step of fig. 4, a dummy chip 800 is flip-chip bonded to an area of the first electronic component 100 not covered by the second electronic component 200, wherein the dummy chip 800 is provided with the conductive pillar 311. Next, as shown in the third step of fig. 4, the dummy chip 800 is polished together with the second electronic component 200, and a portion of the structure of the dummy chip 800 is removed to expose the first line.

In some embodiments, after the first circuit layer 310 is disposed, a capillary underfill 410 and a mold 420 may be disposed over the first electronic component 100, or a mold underfill may be disposed over the first electronic component 100.

In some embodiments, the second circuit layer 320 may be formed by a re-routing process, in which case the second circuit layer 320 is a re-routing layer.

The method for manufacturing a semiconductor package device according to the embodiments of the present disclosure can achieve similar technical effects to those of the semiconductor package device described above, and will not be described herein again.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed in this disclosure have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated in the present disclosure, the order and grouping of the operations is not a limitation of the present disclosure.

Claims

1. A semiconductor package device, comprising:

a first electronic component;

2. The semiconductor package device of claim 1, wherein a connection structure is disposed between the conductive pad and the first circuit layer, the connection structure and the conductive pad forming the bonding region therebetween.

3. The semiconductor package device of claim 2, wherein an intermetallic layer is present between the connection structure and the conductive pad.

4. The semiconductor package device of claim 1, wherein a connection structure is disposed between the conductive pad and the first circuit layer, the connection structure and the first circuit layer forming the bonding region therebetween.

5. The semiconductor package device of claim 4, wherein an intermetallic layer is present between the connection structure and the first line layer.

6. The semiconductor package device of claim 1, wherein an upper surface of the first circuit layer and an upper surface of the second electronic component are flush.

7. The semiconductor package device of claim 1, wherein a second wiring layer is disposed on the first wiring layer.

8. The semiconductor package device of claim 1, wherein the first circuit layer comprises conductive pillars.

9. A method of manufacturing a semiconductor package device, comprising:

10. The method of claim 9, wherein said providing a pre-fabricated first circuit layer on said first electronic component in an area not covered by said second electronic component comprises: