CN114038360A - Backboard detection circuit, backboard detection method and display device - Google Patents
Backboard detection circuit, backboard detection method and display device Download PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
The application relates to a backboard detection circuit, which comprises a backboard, a backboard circuit, an array substrate detection signal circuit and a dead-spot position detection circuit, wherein the backboard circuit and the array substrate detection signal circuit are arranged on the backboard, and the backboard circuit is electrically connected with the array substrate detection signal circuit and the dead-spot position detection circuit; the backplane circuit comprises pixel units arranged in a matrix of a plurality of rows and a plurality of columns, the array substrate detection signal circuit is electrically connected with the pixel units in each row and outputs corresponding detection signals to the pixel units in each row, the pixel units generate corresponding response signals according to the detection signals, the dead-point position detection circuit is electrically connected with the pixel units in each column and receives the response signals, and the dead-point position detection circuit judges the dead-point positions in the pixel units according to the response signals. The application also provides a backboard detection method and a display device with the backboard detection circuit.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a backplane detection circuit, a backplane detection method, and a display device having the backplane detection circuit.
Background
Micro Light Emitting diodes (Micro LEDs) have the advantages of small size, power saving, wide color gamut, long service life, and the like, and with the maturity of manufacturing processes and the reduction of price, related products (such as Micro LED displays) of Micro LEDs are increasing in recent years. At present, the Micro LED backboard is used for detecting whether a dead pixel can be judged in a mode that whether an LED can be lightened or not usually only after a large amount of transfer, but the LED chip and the large amount of transfer capacity are wasted, and whether the dead pixel is caused by the Micro LED backboard is difficult to judge when the display module has the problem of abnormal display.
Therefore, how to solve the problem that the Micro LED backplane cannot be detected before mass transfer, which results in wasted LED chips and mass transfer capacity, becomes an urgent need for technical personnel to solve.
Disclosure of Invention
In view of the foregoing defects of the prior art, an object of the present application is to provide a backplane detection circuit, a backplane detection method and a display device having the backplane detection circuit, which aim to solve the problem of wasted LED chips and huge transfer capacity due to the Micro LED backplane being unable to detect before huge transfer.
A backboard detection circuit comprises a backboard, a backboard circuit, an array substrate detection signal circuit and a dead-center position detection circuit, wherein the backboard circuit and the array substrate detection signal circuit are arranged on the backboard, and the backboard circuit is electrically connected with the array substrate detection signal circuit and the dead-center position detection circuit; the backplane circuit comprises pixel units arranged in a matrix of multiple rows and multiple columns, the array substrate detection signal circuit is electrically connected with the pixel units in each row and outputs corresponding detection signals to the pixel units in each row, the pixel units generate corresponding response signals according to the detection signals, the dead-pixel position detection circuit is electrically connected with the pixel units in each column and receives the response signals, and the dead-pixel position detection circuit judges the dead-pixel position in the pixel units according to the response signals.
In summary, in the backplane detection circuit, the array substrate detection signal circuit and the dead-center position detection circuit are used for detecting the wiring of the backplane circuit, the conductivity of devices and the working state before massive transfer, so that massive transfer of the backplane with dead centers is avoided, the production efficiency is improved, and the production cost is reduced.
Optionally, the backplane detection circuit further includes a plurality of signal transmission nodes, the signal transmission nodes are disposed on the backplane, and each signal transmission node is electrically connected to the pixel unit in each row, and is configured to transmit the response signal transmitted by the pixel unit to the dead-point position detection circuit.
Optionally, each pixel unit includes a first reset transistor, a data control transistor, a driving transistor, and a storage capacitor, where a gate of the first reset transistor receives a first scan signal, a drain of the first reset transistor is electrically connected to an initialization voltage signal terminal and receives an initialization voltage written by the initialization voltage signal terminal, and a source of the first reset transistor is electrically connected to the drain of the data control transistor, the storage capacitor, and the gate of the driving transistor; the grid electrode of the data control transistor receives a second scanning signal, the drain electrode of the data control transistor is electrically connected with the storage capacitor and the grid electrode of the driving transistor, the grid electrode of the driving transistor is electrically connected with the storage capacitor, and the source electrode of the driving transistor is electrically connected with the source electrode of the data control transistor.
Optionally, each pixel unit further includes a switch transistor, a first light-emitting control transistor and a second light-emitting control transistor, wherein a drain of the driving transistor is electrically connected to a source of the switch transistor and a source of the first light-emitting control transistor, and a source of the driving transistor is also electrically connected to a drain of the second light-emitting control transistor, and is configured to drive the light-emitting diode to emit light; the grid electrode of the switch transistor receives the second scanning signal, the drain electrode of the switch transistor receives the data signal, and the source electrode of the switch transistor is electrically connected with the drain electrode of the driving transistor and the source electrode of the first light-emitting control transistor; the grid electrode of the first light-emitting control transistor receives a light-emitting control signal, the drain electrode of the first light-emitting control transistor is electrically connected with the power voltage end to receive power voltage, and the source electrode of the first light-emitting control transistor is electrically connected with the drain electrode of the driving transistor.
Optionally, a first end of the storage capacitor is electrically connected to the drain of the first light-emitting control transistor, and a second end of the storage capacitor is electrically connected to the source of the first reset transistor, the drain of the data control transistor, and the gate of the driving transistor, and is configured to change the gate voltage of the driving transistor; the grid electrode of the second light-emitting control transistor receives the light-emitting control signal, the drain electrode of the second light-emitting control transistor is electrically connected with the source electrode of the driving transistor and the source electrode of the driving transistor, and the source electrode of the second light-emitting control transistor is electrically connected with the light-emitting diode; each pixel unit further comprises a second reset transistor and a detection transistor, wherein a gate of the second reset transistor receives the first scanning signal, a drain of the second reset transistor is electrically connected with the initialization voltage signal terminal and a drain of the first reset transistor, and a source of the second reset transistor is electrically connected with a source of the second light-emitting control transistor and the light-emitting diode and writes the initialization voltage into the storage capacitor;
optionally, the gate of the detection transistor is electrically connected to the array substrate detection signal circuit to receive the detection signal, the source of the detection transistor is electrically connected to the source of the second light-emitting control transistor, the source of the second reset transistor, and the light-emitting diode, and the drain of the detection transistor is electrically connected to the signal transmission node, so as to transmit the response signal to the dead-point position detection circuit through the signal transmission node.
Optionally, the dead-spot position detecting circuit includes: the signal amplifier is used for amplifying the response signal received by the dead point position detection circuit; the signal comparator is used for comparing the voltage value of the amplified response signal with a preset reference voltage and outputting a corresponding output voltage through the output end of the signal comparator; the analog-to-digital converter is used for converting the output voltage transmitted by the signal comparator into corresponding digital signals 1 and 0; and a netlist extractor for receiving the digital signals 1 and 0 transmitted by the analog-to-digital converter and generating a netlist consisting of the digital signals 1 and 0 from the digital signals 1 and 0.
Optionally, when the output voltage output by the signal comparator is a positive output voltage, the analog-to-digital converter converts the positive output voltage into a digital signal 1, and when the output voltage output by the signal comparator is a negative output voltage, the analog-to-digital converter converts the negative output voltage into a digital signal 0, where the digital signal 0 is represented as a corresponding dead-pixel position in the pixel unit.
In summary, in the backplane detection circuit, the array substrate detection signal circuit and the dead-center position detection circuit are used for detecting the wiring of the backplane circuit, the conductivity of devices and the working state before massive transfer, so that massive transfer of the backplane with dead centers is avoided, the production efficiency is improved, and the production cost is reduced.
Based on the same inventive concept, the present application further provides a backplane detection method for detecting the backplane detection circuit, where the backplane detection method includes: the scanning signal circuit outputs scanning signals to control the pixel units to be started line by line, and the driving signal circuit outputs data signals and writes the data signals into the pixel units; the array substrate detection signal circuit outputs corresponding detection signals to the pixel units line by line, and the pixel units generate corresponding response signals based on the detection signals, wherein the response signals are electric signals; the dead point position detection circuit is electrically connected with the backboard circuit and receives the response signal; and the dead pixel position detection circuit processes the received response signal and determines the dead pixel position in the pixel unit according to the processing result.
In summary, in the backplane detection method, the detection of the routing of the backplane circuit, the conductivity of the device and the working state is realized before the massive transfer through the array substrate detection signal circuit and the dead point position detection circuit, so that the massive transfer of the backplane with dead points is avoided, the production efficiency is improved, and the production cost is reduced.
Based on the same inventive concept, the application also provides a display device, which comprises a display panel and the backboard detection circuit.
In summary, in the display device, the array substrate detection signal circuit and the dead point position detection circuit are used for detecting the wiring of the backboard circuit, the conductivity of the device and the working state before the massive transfer, so that the massive transfer of the backboard with dead points is avoided, the production efficiency is improved, and the production cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a backplane detection circuit disclosed in an embodiment of the present application;
FIG. 2 is a circuit diagram of a signal detection circuit of the pixel unit and the array substrate shown in FIG. 1;
FIG. 3 is a timing diagram of the pixel unit shown in FIG. 2;
FIG. 4 is a schematic diagram illustrating the operation of the dead-center position detection circuit shown in FIG. 1;
fig. 5 is a schematic flowchart of a backplane detection method disclosed in an embodiment of the present application.
Description of reference numerals:
10-a backplane detection circuit;
100-a back plate;
200-dead-spot position detection circuitry;
110-a drive signal circuit;
120-a scan signal circuit;
130-pixel cells;
140-array substrate detection signal circuit;
150-signal transmission node;
160-response signal transmission line;
170-detection signal transmission line;
180-data signal lines;
190-scanning signal lines;
210-a signal amplifier;
220-a signal comparator;
230-an analog-to-digital converter;
240-netlist extractor;
250-a signal transmission terminal;
t1 — first reset transistor;
t2 — data control transistor;
t3 — drive transistor;
cst — storage capacitance;
t4-switching transistor;
t5 — first light emission control transistor;
t6 — second emission control transistor;
t7 — second reset transistor;
t8 — detection transistor;
LED-light emitting diodes;
vint-initialization voltage signal terminal;
VDD-supply voltage terminal;
S10-S40-backboard detection method steps.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The traditional LED display screen pixel is formed by combining LEDs with three primary colors of red, green and blue (RGB) in large size, and the pixel pitch reaches about 20mm due to the large size of a packaging body. With the reduction of the chip size and the improvement of the packaging level, the Micro LED further reduces the chip size to be below 50 microns, during preparation, the Micro-LED carries out thinning, microminiaturization and arraying on an LED structure, after the size is reduced to about 1-10 microns, a large amount of addressing is transferred to a circuit substrate to form an ultra-small-pitch LED so as to realize high resolution, then a protection layer and an electrode are completed by utilizing physical precipitation, and then packaging is carried out to complete the display of the Micro-LED. Moreover, compared with the traditional LED, the Micro LED has higher photoelectric efficiency, higher brightness, higher contrast ratio and lower power consumption, and can also realize flexible display in combination with a flexible panel, and in recent years, Micro LED related products (such as Micro LED displays) are increasing. At present, the Micro LED backboard is used for detecting whether a dead pixel can be judged in a mode that whether an LED can be lightened or not usually only after a large amount of transfer, but the LED chip and the large amount of transfer capacity are wasted, and whether the dead pixel is caused by the Micro LED backboard is difficult to judge when the display module has the problem of abnormal display. Based on this, the present application is expected to provide a solution to the problem of wasted LED chips and huge transfer capacity caused by the failure of Micro LED backplane to detect before huge transfer, and the details will be described in the following embodiments.
The detailed description of the scheme of the application provides a backboard detection circuit, a backboard detection method and a specific circuit structure of a display device with the backboard detection circuit.
Please refer to fig. 1, which is a schematic structural diagram of a backplane detection circuit according to an embodiment of the present disclosure. As shown in fig. 1, the present embodiment provides a backplane detection circuit 10, which includes a backplane 100, a driving signal circuit 110, a scanning signal circuit 120, a plurality of pixel units 130, an Array substrate test (AT) signal circuit 140, a plurality of signal transmission nodes 150, a plurality of response signal transmission lines 160, a plurality of detection signal transmission lines 170, a plurality of data signal lines 180, a plurality of scanning signal lines 190, and a dead-spot position detection circuit 200. The driving signal circuit 110, the scanning signal circuit 120, the pixel units 130, the data signal lines 180, and the scanning signal lines 190 are disposed on the backplane 100, and constitute a backplane circuit disposed on the backplane 100. The driving signal circuit 110 is electrically connected to the scanning signal circuit 120 and the pixel unit 130, and the scanning signal circuit 120 is electrically connected to the driving signal circuit 110 and the pixel unit 130.
In the embodiment of the present invention, the array substrate detection signal circuit 140 is electrically connected to the pixel unit 130. The signal transmission node 150 is electrically connected between the dead-center position detection circuit 200 and the pixel unit 130, that is, the dead-center position detection circuit 200 is electrically connected to the pixel unit 130 through the corresponding signal transmission node 150.
In the embodiment of the present application, the driving signal circuit 110 is disposed on the back plate 100 and configured to provide a corresponding driving signal. The pixel units 130 are electrically connected to the driving signal circuit 110 through corresponding Data signal lines 180, and the driving signal circuit 110 outputs Data (Data) signals to the pixel units 130 through the Data signal lines 180. That is, the driving signal circuit 110 is electrically connected to the pixel units 130 through the corresponding Data signal lines 180, and outputs Data (Data) signals to the pixel units 130.
The scan signal circuit 120 is disposed on the backplate 100 and is configured to provide a corresponding scan signal to the pixel unit 130. In this embodiment, the scan signal circuit 120 is disposed on one side of the back plate 100. In this embodiment, the scan signal circuit 120 may be a Gate Driver On Array (GOA) driving circuit and an Array substrate Emission driving (EOA) circuit. Accordingly, the scan signals include a GOA signal and an EOA signal.
In the present embodiment, the pixel units 130 are electrically connected to the scan signal circuit 120 through corresponding scan signal lines 190, and the scan signal circuit 120 outputs corresponding scan signals to the pixel units 130 through the scan signal lines 190. That is, the scan signal circuit 120 is electrically connected to the pixel units 130 through the corresponding scan signal lines 190, and outputs the corresponding scan signals to the pixel units 130. The pixel units 130 are arranged in a matrix of rows and columns and disposed on the backplane 100 for displaying according to the Data (Data) signals and the scan signals respectively transmitted by the driving signal circuit 110 and the scan signal circuit 120. That is, the driving signal circuit 110 is electrically connected to the pixel units 130 in each column through the corresponding Data signal line 180 and outputs a Data (Data) signal to the pixel units 130, and the scan signal circuit 120 is electrically connected to the pixel units 130 in each row through the corresponding scan signal line 190 and outputs a corresponding scan signal to the pixel units 130.
In the embodiment of the present application, the array substrate detection signal circuit 140 is disposed on one side of the backplate 100 opposite to the scan signal circuit 120, that is, the scan signal circuit 120 and the array substrate detection signal circuit 140 are respectively disposed on two opposite sides of the backplate 100. The array substrate detection signal circuit 140 is used for providing a corresponding detection signal. The pixel units 130 are electrically connected to the array substrate detection signal circuit 140 through the corresponding detection signal transmission lines 170, and the array substrate detection signal circuit 140 outputs detection signals to the pixel units 130 through the detection signal transmission lines 170. That is, the array substrate detection signal circuit 140 is electrically connected to the pixel units 130 in each row through the corresponding detection signal transmission lines 170, and outputs the corresponding detection signals to the pixel units 130 row by row through the detection signal transmission lines 170. The pixel unit 130 generates a corresponding response signal based on the detection signal.
In the embodiment of the present application, the detection signal may be an AT detection signal.
In the embodiment of the present application, the plurality of signal transmission nodes 150 are disposed on one side of the backplane 100 opposite to the driving signal circuit 110, that is, the plurality of signal transmission nodes 150 and the driving signal circuit 110 are respectively disposed on the other opposite sides of the backplane 100. The plurality of signal transmission nodes 150 are configured to transmit the response signal transmitted from the pixel unit 130 to the dead-center position detection circuit 200. The pixel units 130 are electrically connected to the signal transmission node 150 through corresponding response signal transmission lines 160, and the pixel units 130 output corresponding response signals to the signal transmission node 150 through the response signal transmission lines 160. It can also be described that the number of the signal transmission nodes 150 is the same as the number of the columns of the pixel units 130, and a plurality of the pixel units 130 in each column are electrically connected to the signal transmission nodes 150 through the corresponding response signal transmission lines 160, and output the response signals to the signal transmission nodes 150 through the corresponding response signal transmission lines 160.
In the embodiment of the present application, the response signal may be an electrical signal, and the signal transmission node 150 may be an AT Pad (Pad).
In the embodiment of the present invention, the plurality of response signal transmission lines 160 are disposed at corresponding positions on the backplane 100, and the plurality of response signal transmission lines 160 are sequentially arranged in parallel along a first direction 001 (i.e. a row direction of the pixel units 130) and are insulated from each other, so as to transmit the response signals transmitted from the pixel units 130 to the corresponding signal transmission nodes 150. In the embodiment of the present application, a plurality of detection signal transmission lines 170 are disposed at corresponding positions on the backplane 100, and the plurality of detection signal transmission lines 170 are sequentially arranged in parallel along a second direction 002 (i.e. the column direction of the pixel units 130) and are insulated from each other, so as to transmit the detection signals outputted by the array substrate detection signal circuit 140 to the corresponding pixel units 130. Wherein the first direction 001 is perpendicular to the second direction 002. It is understood that, in the embodiment, the first direction 001 is a horizontal direction in fig. 1, and the second direction 002 is a vertical direction in fig. 1. It should be noted that the use of the first direction 001 and the second direction 002 is only for the purpose of describing specific embodiments, and is not intended to limit the present application.
In the embodiment of the present application, the response signal transmission line 160 may be an AT reception signal line, and the detection signal transmission line 170 may be an AT detection switch line.
In the embodiment of the present invention, the Data signal lines 180 are disposed on the back plate 100 and are sequentially arranged in parallel along a first direction 001 (i.e. a row direction of the pixel units 130) and are insulated from each other, and the Data signal lines 180 are used for transmitting the Data (Data) signals outputted from the driving signal circuit 110 to the pixel units 130. The plurality of scanning signal lines 190 are disposed on the backplane 100, and are sequentially arranged in parallel along a second direction 002 (i.e., a column direction of the pixel units 130) and are insulated from each other, and the plurality of scanning signal lines 190 are used for transmitting the scanning signals output by the scanning signal circuits 120 to the corresponding pixel units 130.
In the embodiment of the present application, the dead-center position detecting circuit 200 is disposed at one side of the backplate 100 and electrically connected to the signal transmission node 150 of the backplate 100, that is, the dead-center position detecting circuit 200 is electrically connected to the pixel unit 130 through the signal transmission node 150 of the backplate 100. The dead-center position detection circuit 200 is configured to receive the response signal through the signal transmission node 150, and determine the operating state of the backplane circuit and the dead-center positions in the plurality of pixel units 130 according to the response signal.
In the embodiment of the present application, the dead point position detecting circuit 200 may be an external testing unit or device disposed outside the backplane 100. The dead-center position detection circuit 200 and the signal transmission node 150 may be electrically connected by a wire and a pin.
Please refer to fig. 2, which is a circuit diagram of the pixel unit and the array substrate detection signal circuit shown in fig. 1. As shown in fig. 2, each of the pixel units 130 provided herein includes at least a first reset transistor T1, a data control transistor T2, a driving transistor T3, a switching transistor T4, a first light emission control transistor T5, a storage capacitor Cst, a second light emission control transistor T6, a second reset transistor T7, and a detection transistor T8.
The gate of the first reset transistor T1 receives a first Scan signal Scan1, the drain of the first reset transistor T1 is electrically connected to an initialization voltage signal terminal Vint, and receives an initialization voltage written by the initialization voltage signal terminal Vint, and the source of the first reset transistor T1 is electrically connected to the drain of the data control transistor T2, the second terminal of the storage capacitor Cst, and the gate of the driving transistor T3. When the first Scan signal Scan1 is a low level signal, the first reset transistor T1 is turned on in response to the first Scan signal Scan1, and the initialization voltage is written into the storage capacitor Cst through the first reset transistor T1 as the initialization voltage of the storage capacitor Cst.
The gate of the data control transistor T2 receives a second Scan signal Scan2, the drain of the data control transistor T2 is electrically connected to the second terminal of the storage capacitor Cst, the gate of the driving transistor T3 and the source of the first reset transistor T1, and the source of the data control transistor T2 is electrically connected to the source of the driving transistor T3 and the drain of the second light emission control transistor T6. When the second Scan signal Scan2 is a low level signal, the Data control transistor T2 is turned on in response to the second Scan signal Scan2, and the Data (Data) signal is written into the storage capacitor Cst through the first Data control transistor T2.
The gate of the driving transistor T3 is electrically connected to the second end of the storage capacitor Cst, the drain of the data control transistor T2 and the source of the first reset transistor T1, the drain of the driving transistor T3 is electrically connected to the source of the switching transistor T4 and the source of the first light emission control transistor T5, and the source of the driving transistor T3 is electrically connected to the source of the data control transistor T2 and the drain of the second light emission control transistor T6, so as to drive the light emitting diode LED to emit light.
The gate of the switching transistor T4 receives the second Scan signal Scan2, the drain of the switching transistor T4 receives the Data (Data) signal, and the source of the switching transistor T4 is electrically connected to the drain of the driving transistor T3 and the source of the first light emission controlling transistor T5. When the second Scan signal Scan2 is a low level signal, the switching transistor T4 is turned on in response to the second Scan signal Scan2, and the Data (Data) signal is written into the storage capacitor Cst through the switching transistor T4 as a reference voltage of the storage capacitor Cst.
The gate of the first light emitting control transistor T5 receives a light emitting control signal Emit, the drain of the first light emitting control transistor T5 is electrically connected to a power voltage terminal VDD, and receives a power voltage written from the power voltage terminal VDD, and the source of the first light emitting control transistor T5 is electrically connected to the drain of the driving transistor T3 and the source of the switching transistor T4. When the emission control signal Emit is a low level signal, the first emission control transistor T5 is turned on in response to the emission control signal Emit, and writes the power voltage into the storage capacitor Cst.
The storage capacitor Cst has a first terminal electrically connected to the drain of the first light emission controlling transistor T5, and a second terminal electrically connected to the source of the first reset transistor T1, the drain of the data controlling transistor T2, and the gate of the driving transistor T3, for changing the gate voltage of the driving transistor T3.
The gate of the second light emitting control transistor T6 receives the light emitting control signal Emit, the drain of the second light emitting control transistor T6 is electrically connected to the source of the driving transistor T3 and the source of the driving transistor T3, and the source of the second light emitting control transistor T6 is electrically connected to the light emitting diode LED. When the emission control signal Emit is a low level signal, the second emission control transistor T6 is turned on in response to the emission control signal Emit, and the second emission control transistor T6 transmits a driving current to the light emitting diode LED to drive the light emitting diode LED to Emit light.
The gate of the second reset transistor T7 receives the first Scan signal Scan1, the drain of the second reset transistor T7 is electrically connected to the initialization voltage signal terminal Vint and the drain of the first reset transistor T1, and the source of the second reset transistor T7 is electrically connected to the source of the second light emission control transistor T6 and the light emitting diode LED, and writes the initialization voltage into the storage capacitor Cst. When the first Scan signal Scan1 is a low level signal, the second reset transistor T7 is turned on in response to the first Scan signal Scan1 and discharges the storage capacitor Cst by an initialization voltage signal Vint.
In the embodiment of the present application, the first Scan signal Scan1 and the second Scan signal Scan2 can be provided by the Scan signal circuit 120.
The gate of the detection transistor T8 is electrically connected to the array substrate detection signal circuit 140 for receiving the detection signal. The source of the detecting transistor T8 is electrically connected to the source of the second light-emitting control transistor T6, the source of the second reset transistor T7 and the light-emitting diode LED, and the drain of the detecting transistor T8 is electrically connected to the signal transmission node 150, so as to transmit the anode signal of the light-emitting diode LED to the dead-center position detecting circuit 200 through the signal transmission node 150. In the embodiment of the present application, the anode signal is an electric signal, which is a response signal.
The transistors shown in the embodiment of fig. 2 are all P-type transistors, and it is conceivable that the implementation using N-type transistors is easily conceivable by those skilled in the art without inventive labor, and therefore, is within the scope of the embodiments of the present application. It should be noted that the transistors used in the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, there is no difference between the source and the drain.
The timing diagram corresponding to the pixel unit 130 shown in fig. 2 is shown in fig. 3, and specifically, four stages of t1, t2, t3 and t4 in the timing diagram shown in fig. 3 are selected. The details of the timing diagram of the pixel unit 130 shown in fig. 3 will be explained in the following embodiments.
Specifically, 1 represents a high potential, and 0 represents a low potential. It should be noted that 1 and 0 are logic potentials only for better explaining the specific operation of the embodiment of the present application, and are not potentials applied to the gates of the transistors during the specific implementation process. In this embodiment, since all the transistors are P-type transistors, the active signal is a low level signal.
In a period t1 (i.e., a reset period), the first Scan signal Scan1 is 0, the second Scan signal Scan2 is 1, the emission control signal Emit is 1, and the detection signal AT is 1.
Specifically, when the first Scan signal Scan1 is a low-level signal, the second Scan signal Scan2 is a high-level signal, and the first Scan signal Scan1 is a low-level signal, the first reset transistor T1 and the second reset transistor T7 are both turned on, and the data control transistor T2, the driving transistor T3, the switching transistor T4, the first light emission control transistor T5, and the second light emission control transistor T6 are all turned off. Accordingly, the first reset transistor T1 is turned on, and the initialization voltage written from the initialization voltage signal terminal Vint is transmitted to the second terminal of the storage capacitor Cst via the first reset transistor T1; the second reset transistor T7 is turned on to transmit the initialization voltage signal to the anode of the light emitting diode LED; the initialization voltage signal is respectively transmitted to the second terminal of the storage capacitor Cst and the anode of the light emitting diode LED, and the display state of the previous frame is cleared to provide an initial on state.
In a stage t2 (i.e., a data writing stage), the first Scan signal Scan1 is 1, the second Scan signal Scan2 is 0, the emission control signal Emit is 1, and the detection signal AT is 1.
Specifically, when the second Scan signal Scan2 is a low-level signal and the first Scan signal Scan1 and the emission control signal Emit are both high-level signals, the data control transistor T2, the driving transistor T3 and the switching transistor T4 are all turned on, and the first reset transistor T1, the first emission control transistor T5, the second emission control transistor T6 and the second reset transistor T7 are all turned off. Accordingly, the Data control transistor T2, the driving transistor T3, and the switching transistor T4 are turned on, and the Data (Data) signal is written into the second terminal of the storage capacitor Cst through the Data control transistor T2, the driving transistor T3, and the switching transistor T4; the Data control transistor T2 and the switching transistor T4 are turned on to transmit the Data (Data) signal to the second terminal of the storage capacitor Cst through the driving transistor T3.
In a stage t3 (i.e., an AT signal detection stage), the first Scan signal Scan1 is 1, the second Scan signal Scan2 is 1, the emission control signal Emit is 0, and the detection signal AT is 0.
Specifically, when the emission control signal Emit is a low-level signal, the first Scan signal Scan1 is a high-level signal, and the second Scan signal Scan2 is a high-level signal, the driving transistor T3, the first emission control transistor T5, the second emission control transistor T6, and the detecting transistor T8 are all turned on, and the first reset transistor T1, the data control transistor T2, the switching transistor T4, and the second reset transistor T7 are all turned off. At this time, the detection transistor T8 transmits an anode signal (i.e., a response signal) of the light emitting diode LED to the dead point position detection circuit 200 through the signal transmission node 150.
In a stage t4 (i.e., a light emitting stage), the first Scan signal Scan1 is 1, the second Scan signal Scan2 is 1, the light emitting control signal Emit is 0, and the detection signal AT is 1.
Specifically, when the emission control signal Emit is a low-level signal, the first Scan signal Scan1 is a high-level signal, and the second Scan signal Scan2 is a high-level signal, the driving transistor T3, the first emission control transistor T5, and the second emission control transistor T6 are all turned on, and the first reset transistor T1, the data control transistor T2, the switching transistor T4, and the second reset transistor T7 are all turned off. At this time, the power voltage outputted from the power voltage terminal VDD is transmitted to the light emitting diode LED through the driving transistor T3, the first light emitting control transistor T5, and the second light emitting control transistor T6.
Please refer to fig. 4, which is a schematic diagram illustrating an operation principle of the dead point position detecting circuit shown in fig. 1. As shown in fig. 4, the dead-center position detection circuit 200 provided by the present application at least includes a signal amplifier 210, a signal comparator 220, an analog-to-digital converter 230, and a netlist extractor 240. The signal amplifier 210, the signal comparator 220, the analog-to-digital converter 230, and the netlist extractor 240 are electrically connected in sequence.
In the embodiment of the present application, the signal amplifier 210 is configured to amplify the response signal Vin (i.e., the electrical signal) received by the dead-center position detecting circuit 200, and transmit the amplified response signal to the signal comparator 220 through the output terminal Vout 1. It can be understood that, since the received response signal Vin is small, it needs to be processed by the signal amplifier 210 to obtain an amplified response signal for subsequent use.
The signal comparator 220 is configured to compare the voltage value of the amplified response signal with a preset reference voltage Vref, output a corresponding output voltage through an output terminal Vout2, and transmit the output voltage to the analog-to-digital converter 230. Specifically, when the backplane circuit is turned on row by row, if a pixel unit can normally operate (i.e., the light emitting diode LED is normally turned on), a corresponding response signal Vin is transmitted to the signal comparator 220 and compared with the reference voltage Vref, the voltage value of the response signal is greater than the reference voltage Vref, and at this time, the output terminal Vout2 of the signal comparator 220 outputs a positive output voltage V +. If the corresponding pixel unit is abnormally operated (i.e., the light emitting diode LED is not turned on), the voltage value of the response signal is less than the reference voltage Vref, and at this time, the output terminal Vout2 of the signal comparator 220 outputs a negative output voltage V-. The reference voltage Vref may be 0V or other values.
In the embodiment of the present application, the signal comparator 220 may be a voltage comparator (voltage comparator). The output voltages (i.e., the positive output voltage V + and the negative output voltage V-) are analog signals.
The analog-to-digital converter 230 is used for converting the output voltages (i.e. the positive output voltage V + and the negative output voltage V-) transmitted from the signal comparator 220 into corresponding digital signals, and transmitting the digital signals to the netlist extractor 240. Specifically, when the output voltage output by the output terminal Vout2 of the signal comparator 220 is a positive output voltage V +, the analog-to-digital converter 230 converts the positive output voltage V + into a digital signal 1, and when the output voltage output by the output terminal Vout2 of the signal comparator 220 is a negative output voltage V-, the analog-to-digital converter 230 converts the negative output voltage V into a digital signal 0.
The netlist extractor 240 is configured to receive the digital signals 1 and 0 transmitted by the analog-to-digital converter 230, and generate a netlist consisting of the digital signals 1 and 0 from the digital signals 1 and 0. The digital signal 1 indicates that the voltage value of the response signal fed back by the corresponding pixel unit is greater than the reference voltage Vref, that is, the corresponding pixel unit can normally operate, and the digital signal 0 indicates that the voltage value of the response signal fed back by the corresponding pixel unit is less than the reference voltage Vref, that is, the operating state of the corresponding pixel unit is abnormal, that is, the dead point position in the pixel unit is determined.
The dead-center position detecting circuit 200 further includes a plurality of signal transmitting terminals 250, the plurality of signal transmitting terminals 250 are disposed on the dead-center position detecting circuit 200 and are connected to the plurality of signal transmitting nodes 150 in a one-to-one correspondence, and the plurality of signal transmitting terminals 250 are configured to receive the response signal transmitted by the pixel unit 130. The signal transmission terminals 250 are further electrically connected to the signal amplifier 210, and are configured to transmit the response signal Vin to the signal amplifier 210 for processing the response signal Vin. In the embodiment of the present application, the plurality of signal transmission terminals 250 respectively receive response signals Vin1, Vin2, Vin3 and Vin 4.
Please refer to fig. 5, which is a flowchart illustrating a backplane detection method according to an embodiment of the present disclosure. The backplane detection method shown in fig. 5 is applied to the backplane detection circuit shown in fig. 1 to 4, and is used for detecting the backplane in advance, and avoiding a large amount of transfer of the backplane with bad points, thereby reducing the production cost and improving the working efficiency.
In step S10, the scan signal circuit 120 outputs scan signals to control the pixel units 130 to be turned on row by row, and the driving signal circuit 110 outputs Data signals and writes the Data signals into the pixel units 130.
Specifically, the driving signal circuit 110 provides a corresponding driving signal. The driving signal circuit 110 is electrically connected to the plurality of pixel units 130 in each column through corresponding Data signal lines 180, and outputs Data (Data) signals to the pixel units 130, and the scan signal circuit 120 is electrically connected to the plurality of pixel units 130 in each row through corresponding scan signal lines 190, and outputs corresponding scan signals to the pixel units 130. The pixel units 130 are arranged in a matrix of rows and columns and disposed on the backplane 100 for displaying according to the Data (Data) signals and the scan signals respectively transmitted by the driving signal circuit 110 and the scan signal circuit 120.
In step S20, the array substrate detection signal circuit 140 outputs corresponding detection signals to the pixel units 130 line by line, and the pixel units 130 generate corresponding response signals based on the detection signals, where the response signals are electrical signals.
Specifically, the scanning signal circuit 120 and the array substrate detection signal circuit 140 are respectively disposed on two opposite sides of the backplane 100. The array substrate detection signal circuit 140 is used for providing a corresponding detection signal. The array substrate detection signal circuit 140 is electrically connected to the plurality of pixel units 130 in each row through the corresponding detection signal transmission line 170, and outputs corresponding detection signals to the pixel units 130 row by row through the plurality of detection signal transmission lines 170. The pixel unit 130 generates a corresponding response signal based on the detection signal.
Step S30, the dead-center position detection circuit 200 is electrically connected to the backplane circuit, and receives the response signal.
Specifically, the signal transmission nodes 150 and the driving signal circuit 110 are respectively disposed on the other opposite sides of the backplane 100, and the signal transmission nodes 150 are configured to transmit the response signals transmitted by the pixel units 130 to the dead-center position detection circuit 200. The number of the signal transmission nodes 150 is the same as the number of the columns of the pixel units 130, and a plurality of the pixel units 130 in each column are electrically connected to the signal transmission nodes 150 through the corresponding response signal transmission lines 160, and output the response signals to the signal transmission nodes 150 through the corresponding response signal transmission lines 160.
The dead-center position detection circuit 200 is disposed at one side of the backplate 100, and is electrically connected to the pixel unit 130 through the signal transmission node 150 of the backplate 100. The dead-center position detection circuit 200 receives the response signal through the signal transmission node 150.
In step S40, the dead-center position detection circuit 200 processes the received response signal, and determines the dead-center position in the pixel unit according to the processing result.
Specifically, the dead-center position detection circuit 200 at least includes a signal amplifier 210, a signal comparator 220, an analog-to-digital converter 230, and a netlist extractor 240. The signal amplifier 210, the signal comparator 220, the analog-to-digital converter 230, and the netlist extractor 240 are electrically connected in sequence.
In the embodiment of the present application, the signal amplifier 210 is configured to amplify the response signal Vin (i.e., the electrical signal) received by the dead-center position detecting circuit 200, and transmit the amplified response signal to the signal comparator 220 through the output terminal Vout 1. When the backplane circuit is turned on row by row, if the pixel units can work normally, the corresponding response signal Vin is transmitted to the signal comparator 220 and compared with the reference voltage Vref, the voltage value of the response signal is greater than the reference voltage Vref, and at this time, the output terminal Vout2 of the signal comparator 220 outputs a positive output voltage V +. If the corresponding pixel unit works abnormally, the voltage value of the response signal is less than the reference voltage Vref, and at this time, the output terminal Vout2 of the signal comparator 220 outputs a negative output voltage V-. When the output voltage outputted from the output terminal Vout2 of the signal comparator 220 is a positive output voltage V +, the analog-to-digital converter 230 converts the positive output voltage V + into a digital signal 1, and when the output voltage outputted from the output terminal Vout2 of the signal comparator 220 is a negative output voltage V-, the analog-to-digital converter 230 converts the negative output voltage V into a digital signal 0. The netlist extractor 240 receives the digital signals 1 and 0 transmitted from the analog-to-digital converter 230 and generates a netlist consisting of the digital signals 1 and 0 from the digital signals 1 and 0. The digital signal 1 indicates that the voltage value of the response signal fed back by the corresponding pixel unit is greater than the reference voltage Vref, that is, the corresponding pixel unit can work normally, and the digital signal 0 indicates that the voltage value of the response signal fed back by the corresponding pixel unit is less than the reference voltage Vref, that is, the working state of the corresponding pixel unit is abnormal.
In summary, in the backplane detection circuit 10, the array substrate detection signal circuit 140 and the dead-center position detection circuit 200 are used to detect the routing of the backplane circuit, the conductivity of the devices, and the working state before the massive transfer, so that the massive transfer of the backplane with dead centers is avoided, the production efficiency is improved, and the production cost is reduced.
The embodiment of the present application further provides a display device, which includes a display panel and the backplane detection circuit 10 shown in fig. 1 to 4. The display panel comprises a display area and a non-display area, wherein the display area is used for displaying images, and the non-display area is arranged around the display area and is not used for displaying images. The display panel may use a liquid crystal material as a display medium, but the application is not limited thereto. The display device may be an electroluminescent display device, such as a Micro LED panel, a Mini LED panel, a mobile phone, a tablet computer, a navigator, a display, and any electronic device or component with a display function, which is not particularly limited in this application.
It should be understood that the application of the present application is not limited to the above examples, and that modifications or changes may be made by those skilled in the art based on the above description, and all such modifications and changes are intended to fall within the scope of the appended claims.
Claims (10)
1. A backboard detection circuit is characterized by comprising a backboard, a backboard circuit, an array substrate detection signal circuit and a dead-center position detection circuit, wherein the backboard circuit and the array substrate detection signal circuit are arranged on the backboard, and the backboard circuit is electrically connected with the array substrate detection signal circuit and the dead-center position detection circuit;
the backplane circuit comprises pixel units arranged in a matrix of multiple rows and multiple columns, the array substrate detection signal circuit is electrically connected with the pixel units in each row and outputs corresponding detection signals to the pixel units in each row, the pixel units generate corresponding response signals according to the detection signals, the dead-pixel position detection circuit is electrically connected with the pixel units in each column and receives the response signals, and the dead-pixel position detection circuit judges the dead-pixel position in the pixel units according to the response signals.
2. The backplane detection circuit according to claim 1, further comprising a plurality of signal transmission nodes disposed on the backplane, each signal transmission node being electrically connected to the pixel unit of each column for transmitting the response signal transmitted from the pixel unit to the dead-point detection circuit.
3. The backplane detection circuit according to claim 1, wherein each of the pixel units comprises a first reset transistor, a data control transistor, a driving transistor and a storage capacitor, wherein a gate of the first reset transistor receives a first scan signal, a drain of the first reset transistor is electrically connected to an initialization voltage signal terminal and receives an initialization voltage written by the initialization voltage signal terminal, and a source of the first reset transistor is electrically connected to a drain of the data control transistor, the storage capacitor and a gate of the driving transistor; the grid electrode of the data control transistor receives a second scanning signal, the drain electrode of the data control transistor is electrically connected with the storage capacitor and the grid electrode of the driving transistor, the grid electrode of the driving transistor is electrically connected with the storage capacitor, and the source electrode of the driving transistor is electrically connected with the source electrode of the data control transistor.
4. The backplane detection circuit according to claim 3, wherein each of the pixel units further includes a switch transistor, a first light-emitting control transistor and a second light-emitting control transistor, wherein a drain of the driving transistor is electrically connected to a source of the switch transistor and a source of the first light-emitting control transistor, and a source of the driving transistor is further electrically connected to a drain of the second light-emitting control transistor for driving the light-emitting diode to emit light; the grid electrode of the switch transistor receives the second scanning signal, the drain electrode of the switch transistor receives the data signal, and the source electrode of the switch transistor is electrically connected with the drain electrode of the driving transistor and the source electrode of the first light-emitting control transistor;
the grid electrode of the first light-emitting control transistor receives a light-emitting control signal, the drain electrode of the first light-emitting control transistor is electrically connected with the power voltage end to receive power voltage, and the source electrode of the first light-emitting control transistor is electrically connected with the drain electrode of the driving transistor.
5. The backplane detection circuit according to claim 4, wherein a first terminal of the storage capacitor is electrically connected to the drain of the first light-emitting control transistor, and a second terminal of the storage capacitor is electrically connected to the source of the first reset transistor, the drain of the data control transistor, and the gate of the driving transistor, for varying the gate voltage of the driving transistor; the grid electrode of the second light-emitting control transistor receives the light-emitting control signal, the drain electrode of the second light-emitting control transistor is electrically connected with the source electrode of the driving transistor and the source electrode of the driving transistor, and the source electrode of the second light-emitting control transistor is electrically connected with the light-emitting diode.
6. The backplane detection circuit according to claim 5, wherein each of the pixel units further comprises a second reset transistor and a detection transistor, wherein a gate of the second reset transistor receives the first scan signal, a drain of the second reset transistor is electrically connected to the initialization voltage signal terminal and a drain of the first reset transistor, a source of the second reset transistor is electrically connected to a source of the second light emitting control transistor and the light emitting diode, and writes the initialization voltage into the storage capacitor;
the grid of the detection transistor is electrically connected with the array substrate detection signal circuit to receive the detection signal, the source of the detection transistor is electrically connected with the source of the second light-emitting control transistor, the source of the second reset transistor and the light-emitting diode, and the drain of the detection transistor is electrically connected with the signal transmission node and used for transmitting the response signal to the dead-point position detection circuit through the signal transmission node.
7. A backplane detection circuit according to any of claims 1-6, wherein the dead-point detection circuit comprises:
the signal amplifier is used for amplifying the response signal received by the dead point position detection circuit;
the signal comparator is used for comparing the voltage value of the amplified response signal with a preset reference voltage and outputting a corresponding output voltage through the output end of the signal comparator;
the analog-to-digital converter is used for converting the output voltage transmitted by the signal comparator into corresponding digital signals 1 and 0;
and a netlist extractor for receiving the digital signals 1 and 0 transmitted by the analog-to-digital converter and generating a netlist consisting of the digital signals 1 and 0 from the digital signals 1 and 0.
8. The backplane detection circuit of claim 7, wherein the analog-to-digital converter converts the positive output voltage into a digital signal 1 when the output voltage outputted by the signal comparator is a positive output voltage, and converts the negative output voltage into a digital signal 0 when the output voltage outputted by the signal comparator is a negative output voltage, wherein the digital signal 0 is represented as a corresponding dead pixel position in the pixel cell.
9. A backplane detection method for detecting the backplane detection circuit according to any one of the preceding claims 1 to 8, wherein the backplane detection method comprises:
the scanning signal circuit outputs scanning signals to control the pixel units to be started line by line, and the driving signal circuit outputs data signals and writes the data signals into the pixel units;
the array substrate detection signal circuit outputs corresponding detection signals to the pixel units line by line, and the pixel units generate corresponding response signals based on the detection signals, wherein the response signals are electric signals;
the dead point position detection circuit is electrically connected with the backboard circuit and receives the response signal;
and the dead pixel position detection circuit processes the received response signal and determines the dead pixel position in the pixel unit according to the processing result.
10. A display device comprising a display panel and the backplane detection circuit of any of claims 1-8.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616621A (en) * | 2015-02-05 | 2015-05-13 | 京东方科技集团股份有限公司 | Pixel circuit, and drive method and display device thereof |
| CN105609024A (en) * | 2016-01-05 | 2016-05-25 | 京东方科技集团股份有限公司 | Testing method and apparatus for display panel |
| CN106710528A (en) * | 2017-01-23 | 2017-05-24 | 上海天马有机发光显示技术有限公司 | Organic light-emitting pixel drive circuit, driving method and organic light-emitting display panel |
| CN107728395A (en) * | 2017-10-31 | 2018-02-23 | 京东方科技集团股份有限公司 | Array base palte, display device, data wire bad detection means and detection method |
| CN208421055U (en) * | 2017-11-27 | 2019-01-22 | 康佳集团股份有限公司 | OLED current detection circuit and OLED screen display system |
| CN109728068A (en) * | 2019-02-28 | 2019-05-07 | 上海天马有机发光显示技术有限公司 | A kind of array substrate, its driving method and display device |
| CN111627976A (en) * | 2020-07-10 | 2020-09-04 | 上海视欧光电科技有限公司 | Organic light emitting display device |
| CN213277403U (en) * | 2020-11-10 | 2021-05-25 | 重庆康佳光电技术研究院有限公司 | Detection circuit of LED display back plate and LED display panel |
-
2021
- 2021-08-06 CN CN202110903599.XA patent/CN114038360A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616621A (en) * | 2015-02-05 | 2015-05-13 | 京东方科技集团股份有限公司 | Pixel circuit, and drive method and display device thereof |
| CN105609024A (en) * | 2016-01-05 | 2016-05-25 | 京东方科技集团股份有限公司 | Testing method and apparatus for display panel |
| CN106710528A (en) * | 2017-01-23 | 2017-05-24 | 上海天马有机发光显示技术有限公司 | Organic light-emitting pixel drive circuit, driving method and organic light-emitting display panel |
| CN107728395A (en) * | 2017-10-31 | 2018-02-23 | 京东方科技集团股份有限公司 | Array base palte, display device, data wire bad detection means and detection method |
| CN208421055U (en) * | 2017-11-27 | 2019-01-22 | 康佳集团股份有限公司 | OLED current detection circuit and OLED screen display system |
| CN109728068A (en) * | 2019-02-28 | 2019-05-07 | 上海天马有机发光显示技术有限公司 | A kind of array substrate, its driving method and display device |
| CN111627976A (en) * | 2020-07-10 | 2020-09-04 | 上海视欧光电科技有限公司 | Organic light emitting display device |
| CN213277403U (en) * | 2020-11-10 | 2021-05-25 | 重庆康佳光电技术研究院有限公司 | Detection circuit of LED display back plate and LED display panel |
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Application publication date: 20220211 |