CN114035853A - MCU bootstrap system and chip that possess SPI interface - Google Patents
MCU bootstrap system and chip that possess SPI interface Download PDFInfo
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- CN114035853A CN114035853A CN202111359951.4A CN202111359951A CN114035853A CN 114035853 A CN114035853 A CN 114035853A CN 202111359951 A CN202111359951 A CN 202111359951A CN 114035853 A CN114035853 A CN 114035853A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention relates to an MCU (micro control unit) guidance system with an SPI (serial peripheral interface) and a chip, wherein the MCU guidance system comprises a state machine circuit and two alternate cache regions; the state machine circuit is connected with a flash memory with an SPI (serial peripheral interface) through an SPI (serial peripheral interface) bus and is used for reading a guide instruction segment from the flash memory; when two guide instruction segments read successively by the state machine circuit are continuous, the two guide instruction segments read successively are sent to one of the alternate cache regions, and then the two guide instruction segments received successively in the same alternate cache region are sent to the MCU in sequence; otherwise, sending the guide instruction segment read earlier into one of the alternate cache regions, and then sending the guide instruction segment read later into the other alternate cache region, wherein in the working state, one of the alternate cache regions sends the received guide instruction segment to the MCU, and then the other alternate cache region sends the received guide instruction segment to the MCU.
Description
Technical Field
The invention relates to the technical field of MCU (microprogrammed control Unit) boot starting, in particular to an MCU boot system and a chip with an SPI (serial peripheral interface).
Background
In order to meet the requirements of high performance and low cost of communication equipment, NorFlash (nor gate nonvolatile memory flash) is a current type of nonvolatile flash memory, and due to the characteristic that NorFlash can be executed in a chip, NandFlash (nand gate nonvolatile memory flash) is more suitable for being used as a storage medium of a starting program compared with another type of nonvolatile flash memory.
NorFlash mainly adopts SPI serial interface (SPI is serial peripheral interface); the NorFlash SPI interface has a small number of signal lines and a simple peripheral design, so that the NorFlash SPI interface is very suitable for being used as a data storage device in intelligent mobile terminal products such as mobile phones, tablets and small wheeled robots (such as pet robots, tumbler robots and indoor cleaning robots), but for intelligent mobile terminal products with functions needing to be upgraded periodically, a Micro Control Unit (MCU) in the existing intelligent mobile terminal products cannot support the use of NorFlash as a carrier of a bootstrap program, namely, the microcontroller Unit cannot be guided by bootstrap program data in the NorFlash to start and execute a task of upgrading functions.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide an MCU boot system and a chip with an SPI interface, which support an MCU by using a set of default boot commands built in a flash memory, and meet the requirements for booting the MCU, booting the configuration MCU, and booting the MCU for upgrading. The specific technical scheme is as follows:
the MCU system comprises a state machine circuit and two alternate buffer areas; the state machine circuit is connected with a flash memory with an SPI interface through an SPI bus and used for reading a guide instruction segment from the flash memory, wherein the state machine circuit has the following working state jumps: when two guide instruction segments read successively by the state machine circuit are continuous, triggering the state machine circuit to enter a continuous access state, wherein the state machine circuit is used for sending the two guide instruction segments read successively into one of the alternate cache regions in the continuous access state, and then sending the two guide instruction segments received successively in the one of the alternate cache regions to the MCU in sequence so as to guide the MCU to start; when two guide instruction segments read successively by the state machine circuit are not continuous, the state machine circuit is triggered to enter a branch access state, and the state machine circuit is used for sending one guide instruction segment read earlier into one of the alternate cache regions and then sending one guide instruction segment read later into the other alternate cache region in the branch access state; the state machine circuit is further configured to, in a branch access state, trigger one of the alternating cache regions to send a received one of the boot instruction segments to the MCU first, and then trigger the other of the alternating cache regions to send a received one of the boot instruction segments to the MCU, so as to avoid searching for two discontinuous boot instruction segments one by one address unit in the same alternating cache region.
Further, the two alternate buffer areas are a first alternate buffer area and a second alternate buffer area respectively; if the first guide instruction segment and the second guide instruction segment which are read successively are not continuous and the second guide instruction segment and the third guide instruction segment which are read successively are not continuous, the state machine circuit is used for sending the first guide instruction segment into the first alternate cache region, then sending the second guide instruction segment into the second alternate cache region and then sending the third guide instruction segment into the first alternate cache region in the branch access state; the state machine circuit is further configured to, in a branch access state, trigger the first alternating cache region to send the first guidance instruction segment to the MCU, trigger the second alternating cache region to send the second guidance instruction segment to the MCU, and trigger the first alternating cache region to send the third guidance instruction segment to the MCU, so as to avoid searching for two discontinuous guidance instruction segments one by one address unit in the same alternating cache region in the same timing cycle.
Further, the two alternate buffer areas are a first alternate buffer area and a second alternate buffer area respectively; if the first guide instruction segment and the second guide instruction segment read successively by the state machine circuit are not continuous, the state machine circuit jumps to the branch access state, and the state machine circuit sends the first guide instruction segment to a first alternate cache region and then sends the second guide instruction segment to a second alternate cache region in the branch access state; then, if the second leading instruction segment and the third leading instruction segment read successively by the state machine circuit are continuous, the state machine circuit jumps to the continuous access state from the branch access state, and the state machine circuit sends the third leading instruction segment to a second alternate cache region in the continuous access state; the state machine circuit is further configured to trigger the first alternating cache region to send the first guidance instruction segment to the MCU, and then trigger the second alternating cache region to send the two guidance instruction segments received successively to the MCU in sequence, so as to avoid searching for two discontinuous guidance instruction segments one by one address unit in the same alternating cache region in the same timing cycle.
Further, when the two consecutive read guidance instruction segments of the state machine circuit are consecutive, the state machine circuit enters the continuous access state, and then controls the two consecutive read guidance instruction segments to be stored in the same alternate cache region until the two consecutive read guidance instruction segments of the state machine circuit are not consecutive, the state machine circuit jumps to the branch access state and controls the latest read guidance instruction segment to be stored in another alternate cache region.
Further, in the process of sending a guide instruction segment in an alternate cache region to the MCU, synchronously sending another guide instruction segment into the alternate cache region or another alternate cache region; the two alternate cache regions are respectively positioned in different storage spaces in the MCU guide system; the processing process comprises the steps of sending the two successively read guide instruction segments to corresponding alternate cache regions and sending the two successively read guide instruction segments to the MCU from the corresponding alternate cache regions.
Furthermore, an SPI interface is arranged in the state machine circuit; each functional pin of the SPI interface of the flash memory is connected with the corresponding functional pin of the SPI interface of the state machine circuit through an SPI bus; the SPI interface of the flash memory is configured to be in a 4-line reading mode, so that the SPI interface of the state machine circuit is also adaptively adjusted to be in the 4-line reading mode; the write protection pin and the holding pin of the SPI interface of the state machine circuit are both configured as data input ends so as to form 4 data lines with parallel data receiving and transmitting functions in one SPI interface and read a guide instruction section in one clock cycle; the state machine circuit is used for performing parallel-to-serial conversion on binary numbers corresponding to the guide instruction segments received by 4 data input ends in parallel in a 4-line read mode of the SPI interface of the state machine circuit, and then transmitting the binary numbers to a corresponding alternate cache region; wherein, the alternate buffer area uses serial interface to receive and transmit data.
Furthermore, the two guidance instruction segments read successively by the state machine circuit are continuous, which indicates that the addresses corresponding to the two guidance instruction segments read successively by the state machine circuit are continuous; the two leading instruction segments read successively by the state machine circuit are not continuous, which indicates that the addresses corresponding to the two leading instruction segments read successively by the state machine circuit are not continuous, and then a leading instruction segment read later is determined to jump relative to a leading instruction segment read earlier; the boot instruction segment is boot program data stored in the flash memory in advance, and the boot program data configures an upgrade request port of the MCU to enter a boot mode.
Further, in the two alternative cache regions, when any one of the two alternative cache regions has no remaining cache space, the boot instruction segment is stopped from being continuously read from the flash memory, and the flash memory is configured to be in a write-protected state.
Further, the rate of reading the boot instruction segments by the state machine circuit through the SPI bus is greater than the rate of extracting the boot instruction segments from the alternate buffer by the MCU.
Further, after the MCU is booted, the upgrade program in the MCU is further configured to take over the SPI interface of the state machine circuit, so that the MCU performs read/write operations on the flash memory through the SPI interface and the SPI bus connected thereto, thereby reducing data conversion between different bus transmissions.
A chip, this chip inside set up the MCU bootstrap system that possesses the SPI interface.
Compared with the prior art, the method has the beneficial technical effects that two alternate cache regions are designed, and a working state scheduling mechanism existing in the state machine circuit is combined to deal with the continuous condition between two sequentially read guide instruction segments, so that most of the MCUs can support the start of the SPI NorFlash guide, the MCU upgrade is further realized, two sequentially read discontinuous guide instruction segments are respectively cached by the two alternate cache regions, the sequentially read two continuous guide instruction segments are respectively cached by one alternate cache region, and the probability of program operation abnormity caused by frequent code skipping is reduced; and further, the upgrade period of small wheeled robots (such as pet robots and tumbler robots) using the partial MCU which does not support SPI NorFlash guidance is shortened.
Drawings
Fig. 1 is a schematic connection diagram of an MCU boot system having an SPI interface, a flash memory (SPI flash) having an SPI interface, and an MCU according to an embodiment of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the drawings. Each unit block in the following embodiments is a logic circuit, and one logic circuit may be one physical unit, may be a state machine in which a plurality of logic devices are combined according to a certain read/write sequence and signal logic change, may be a part of one physical unit, or may be implemented by combining a plurality of physical units. In addition, in order to highlight the innovative part of the present invention, elements that are not so closely related to solving the technical problems presented by the present invention are not introduced in the embodiments of the present invention, but it does not indicate that other elements are not present in the embodiments of the present invention.
In the prior art, an MCU usually cannot directly access a peripheral flash memory (flash memory), and especially when developing or upgrading functions of a small portable intelligent device controlled by the MCU, the MCU is limited by the compatibility of data communication interfaces, and currently, it is not possible to better use a nor flash memory with a serial peripheral interface (SPI interface) and a nand flash memory with a serial peripheral interface (SPI interface) as storage media for storing boot program data, and the MCU of the small intelligent device also lacks necessary software drivers to support transfer of related boot program data.
The embodiment of the invention discloses an MCU (micro control unit) guidance system with an SPI (serial peripheral interface), which can be known by referring to FIG. 1 and comprises a state machine circuit and two alternate cache regions; the two alternate buffer areas are the first alternate buffer area and the second alternate buffer area of fig. 1, and preferably, are two buffer spaces with mutually independent pin resources, and the involved read and write operations do not interfere with each other. The state machine circuit is connected with a flash memory with an SPI interface through an SPI bus and is used for reading a guide instruction section from the flash memory; the flash memory with the SPI interface is the flash memory with the SPI interface, the SPI interface of the flash memory comprises 4 pins supporting data input and output, a clock pin SCK and a chip selection pin/CS, and the flash memory is used for providing 4 paths of data signals, 1 path of clock signals and 1 path of chip selection signals to the state machine circuit through the SPI bus, so that the state machine circuit reads code data with a program guide function from the flash memory to guide and start an MCU or a related processor. It should be noted that the 4 pins supporting data input and output shown in fig. 1 include IO0, IO1, IO2, and IO3, and provide 4 data signal lines, and in the same clock cycle, the greater the number of data signal lines, the higher the transmission rate of the SPI interface is.
In this embodiment, both the MCU and the state machine circuit may be designed with parallel interfaces, the MCU obtains a boot start program from a peripheral memory, and the MCU is specially configured with a port with a valid and effective upgrade request to execute a boot start mode; the state machine circuit can be a digital integrated circuit which uses a hardware programming language to construct logic functions according to the scheduling requirement of the working state, generates time sequence functions under each working state and can overcome the compatibility of various MCU to the standard SPI protocol.
The boot instruction segment may be boot program data that occupies a bit width of 4 bits or a multiple of 4 bits, for guiding the MCU to start up, so as to initialize configuration parameters (including determining a start address and judging verification information) of a related operating environment (including the MCU, the SPI interface and the flash memory), upgrade the functions of the MCU, erase data of the flash memory and upgrade memory blocks in the flash memory, the MCU boot system, the MCU and the flash memory form an integral system to support program start boot and subsequent program function upgrade under the SPI interface, the method is further used for intelligent mobile terminal products such as mobile phones, tablets and small wheeled robots (such as pet robots, tumbler robots and indoor cleaning robots), and the requirements of using NorFlash as a carrier of a bootstrap program are met.
In this embodiment, the state machine circuit has the following operating state jumps:
and when the two guide instruction segments read successively by the state machine circuit are continuous, triggering the state machine circuit to enter a continuous access state. The state machine circuit can enter the continuous access state from an initial state or other working states (including an idle state). When the state machine circuit detects that two successively read guide instruction sections are continuous, a detection result signal in the state machine circuit triggers the state machine circuit to enter a continuous access state.
In this embodiment, the data input end of the state machine circuit receives a boot instruction segment through the SPI bus according to a timing sequence specified by the SPI interface, so that the state machine circuit reads one boot instruction segment from the flash memory every other clock cycle, where a bit width of data read at one time is greater than 1, and generally, transmission of the SPI bus is performed in units of bytes. The flash memory transmits a process of booting instruction segments to the state machine circuit, and the state machine circuit triggers the chip selection pin/SS 1 of the flash memory and/or sets the chip selection pin/CS of the flash memory to be low level.
It should be noted that, before reading the boot instruction segment, the state machine circuit receives a request instruction sent from the MCU or triggered by an external power-on reset signal, where the request instruction is analyzed by the state machine circuit to obtain an address signal, and the state machine circuit reads the boot instruction segment corresponding to the address signal from the flash memory, where the address signal is used as address information corresponding to the instruction segment that needs to be received when the MCU is started, specifically, corresponds to an address of the boot instruction segment in the flash memory, and sequentially reads the boot instruction segments from the flash memory according to the address information, so that two consecutive boot instruction segments have two conditions, namely, continuous and non-continuous conditions, and it also indicates that two consecutive boot instruction segments may be two adjacent boot instruction segments. The boot instruction segment may be boot program data stored in the flash memory in advance before each MCU is started, where the boot program data configures an upgrade request port of the MCU to enter a boot mode.
Specifically, when the effective addresses corresponding to the two consecutive boot instruction segments read by the state machine circuit are consecutive, the two boot instruction segments read by the state machine circuit in sequence are consecutive, the storage sequence of the two boot instruction segments in the flash memory is consecutive, so that the state machine circuit can continuously access the boot instruction segments in the flash memory from a start address and store the boot instruction segments in the cache region of the stack structure according to the sequence of the boot instruction segments, and then the state machine circuit is configured to send the two boot instruction segments read in sequence to one of the alternate cache regions in a continuous access state, that is, the state machine circuit sequentially transmits the two consecutive boot instruction segments to the same alternate cache region, and the alternate cache region sequentially receives the two consecutive boot instruction segments in the stack structure, the access continuity between the guide instruction sections can be ensured, two guide instruction sections received successively in the alternate cache region can be sequentially sent to the MCU after a guide request instruction sent by the MCU is received, the MCU is guided to start upgrading, the MCU can continuously access the guide instruction sections from an initial address, the MCU is started to read and write the flash memory with the SPI interface, the influence of the read data length caused by the model difference of the MCU is reduced, the state machine circuit can control the progress of reading the guide instruction sections from the flash memory no matter how the data length and the data reading speed of the state machine circuit are read each time, and the compatibility problem caused by the model difference of the MCU is solved. It is noted that the state machine circuit only reads one piece of the boot instruction per clock cycle.
In some embodiments, after the MCU boot system, the MCU and the flash memory are powered on, the MCU boot system is used as a printed circuit board, a serial key is mounted on the printed circuit board, and after the serial key is pressed, the state machine circuit generates a level change to be respectively sent to the MCU and the flash memory, and particularly generates a boot start indication signal at an upgrade request port of the MCU, so that the state information of boot device self start and subsequent function upgrade can be obviously reflected on some mobile terminal devices.
When two leading instruction segments read successively by the state machine circuit are not continuous, triggering the state machine circuit to enter a branch access state, wherein the state machine circuit can jump from the continuous access state, the idle state or the initial state to the branch access state, and when the state machine circuit detects that the two leading instruction segments read successively are not continuous, a detection result signal in the state machine circuit triggers the state machine circuit to enter the branch access state; at this time, the two leading instruction segments read successively by the state machine circuit are not continuous, the storage sequence of the effective addresses corresponding to the two leading instruction segments in the memory space is not continuous, the effective addresses corresponding to the two leading instruction segments have an interval of one address segment in the flash memory, then the state machine circuit is used for sending the leading instruction segment read earlier into one of the alternate cache regions in the branch access state and then sending the leading instruction segment read later into the other alternate cache region, so that the two leading instruction segments are respectively sent to two different alternate cache regions when the leading instruction segments read twice continuously by the state machine circuit are discontinuous, and then the state machine circuit is used for selecting to receive the leading request instruction sent by the MCU in the branch access state, triggering one of the alternating cache regions to send a received guide instruction segment to the MCU, and triggering the other alternating cache region to send a received guide instruction segment to the MCU, so that when two guide instruction segments (two guide instruction segments read continuously twice and two guide instruction segments read in total) read successively by the state machine circuit are not continuous, the two guide instruction segments are regarded as two branch instructions, the two cache regions are separated to be stored, and the MCU is used for reading the two cache regions, thereby avoiding searching the two discontinuous guide instruction segments one by one in the same alternating cache region and accelerating the guiding speed; meanwhile, the state machine circuit can enable the MCU to read one guide instruction segment from the respective initial address in two alternate cache regions in sequence, so that two discontinuous guide instruction segments of address information can be read alternately between the two alternate cache regions, the compatibility of the MCU to the guide instruction codes of the flash memory is enhanced, namely the MCU is adapted to the guide instruction (namely the two discontinuous guide instruction segments transmitted by the flash memory) with jumping, and the stability of the MCU guide system to the program guide starting of different types of MCUs under the same SPI interface is improved.
Compared with the prior art, the embodiment of the invention has the beneficial technical effects that two alternate cache regions can be selected at the starting stage of the MCU, and a working state scheduling mechanism existing in the state machine circuit is combined to deal with the continuous condition between two successively read guide instruction segments, so that most of the MCU can support the SPI NorFlash guide starting and the subsequent upgrading, the two successively read discontinuous guide instruction segments are respectively cached by the two alternate cache regions, the two successively read continuous guide instruction segments are respectively cached by the one alternate cache region, and the probability of abnormal program operation caused by frequent code skipping is reduced; and further, the upgrade period of small wheeled robots (such as pet robots and tumbler robots) using the partial MCU which does not support SPI NorFlash guidance is shortened.
As an embodiment, the two alternate buffer areas are a first alternate buffer area and a second alternate buffer area, which may be located in different storage spaces in the MCU boot system respectively; the state that the first guide instruction segment and the second guide instruction segment read successively by the state machine circuit are not continuous, and the second guide instruction segment and the third guide instruction segment read successively are not continuous is that the state machine circuit reads the first guide instruction segment for the first time, the second guide instruction segment for the second time and the third guide instruction segment for the third time from the guide instruction segments read successively three times in the flash memory, wherein the corresponding storage addresses of the first guide instruction segment and the second guide instruction segment in the flash memory are discontinuous, the corresponding storage addresses of the second guide instruction segment and the third guide instruction segment in the flash memory are discontinuous, the corresponding storage addresses enter and are maintained in the branch access state, and then in the current branch access state, the state machine circuit firstly sends the first guide instruction segment into the first alternate cache region, sending the second guide instruction section into a second alternate cache region, and then sending the third guide instruction section into the first alternate cache region to realize alternate caching of discontinuous guide instruction sections between the first alternate cache region and the second alternate cache region; it is understood that, if the state machine circuit reads three or more pieces of the boot instruction, the state machine circuit keeps controlling that the pieces of the boot instruction read twice in succession are alternately buffered between the first alternate buffer area and the second buffer area. The state machine circuit is further configured to, in the branch access state, trigger the first alternating buffer area to send the first guidance instruction segment to the MCU after receiving a guidance request instruction sent by the MCU, trigger the second alternating buffer area to send the second guidance instruction segment to the MCU, and trigger the first alternating buffer area to send the third guidance instruction segment to the MCU; in the branch access state, the state machine circuit controls the first alternating buffer area and the second alternating buffer area to alternately transmit one internally stored pilot instruction segment to the MCU, and also allows the same MCU to alternately receive mutually discontinuous pilot instruction segments from the two alternating buffer areas, so as to avoid searching for two discontinuous pilot instruction segments one by one address unit in the same alternating buffer area in the same timing cycle.
As another embodiment, when the first boot instruction segment and the second boot instruction segment read successively from the flash memory by the state machine circuit are not continuous, and the second boot instruction segment and the third boot instruction segment read successively from the flash memory are continuous, it may be determined that, in the boot instruction segments read successively three times from the flash memory by the state machine circuit, if there is a case where the boot instruction segments read twice continuously are not continuous, the state machine circuit is triggered to jump to the branch access state correspondingly; and then if the other two consecutive read guide instruction segments are consecutive, correspondingly triggering the state machine circuit to jump to the continuous access state. Specifically, the state machine circuit is configured to jump to the branch access state when detecting that a first leading instruction segment and a second leading instruction segment read successively (equivalently, read twice consecutively) are not consecutive, where the state machine circuit sends the first leading instruction segment into the first alternating cache region and then sends the second leading instruction segment into the second alternating cache region in the branch access state, so as to implement that two leading instruction segments that are not consecutive to each other are stored in the first alternating cache region and the second alternating cache region, respectively; then, if the second guidance instruction segment and the third guidance instruction segment read successively (equivalent to two consecutive reads) by the state machine circuit are consecutive, the state machine circuit jumps from the branch access state to the continuous access state, and the state machine circuit stores the third guidance instruction segment into the second alternate cache region in the continuous access state, so as to store two consecutive guidance instruction segments into the same alternate cache region, especially store the two consecutive guidance instruction segments into the same alternate cache region (the second alternate cache region) with the guidance instruction segment read last (i.e. the second guidance instruction segment); it can be understood that, when the two consecutive read pieces of the boot instruction by the state machine circuit are not consecutive, the state machine circuit controls the two consecutive read pieces of the boot instruction to be alternately buffered between the first alternate buffer area and the second buffer area until the two consecutive read pieces of the boot instruction by the state machine circuit are consecutive; correspondingly, the state machine circuit is further configured to, after receiving a guidance request instruction sent by the MCU, trigger the first alternating buffer to send the first guidance instruction segment to the MCU, and then trigger the second alternating buffer to send the two guidance instruction segments received successively to the MCU in sequence, so as to avoid searching for two discontinuous guidance instruction segments one by one address unit in the same alternating buffer within the same timing cycle, but ensure that only two continuous guidance instruction segments can be searched within the same alternating buffer within the same timing cycle.
As another embodiment, the two alternate buffer areas are a first alternate buffer area and a second alternate buffer area, which may be located in different storage spaces in the MCU boot system respectively; if the first guide instruction segment and the second guide instruction segment read successively by the state machine circuit are continuous, the state machine circuit jumps to the continuous access state, and the state machine circuit sends the first guide instruction segment and the second guide instruction segment to a first alternate cache region in sequence in the continuous access state; the state machine circuit reads a first guide instruction segment from the flash memory for the first time and reads a second guide instruction segment from the flash memory for the second time, corresponding storage addresses of the first guide instruction segment and the second guide instruction segment in the flash memory are continuous, and two adjacent guide instruction segments are identified. And then, if the second boot instruction segment and the third boot instruction segment read successively by the state machine circuit are not continuous, the state machine circuit jumps from the continuous access state to the branch access state, and the state machine circuit sends the third boot instruction segment to a second alternate cache region in the branch access state, wherein the state machine circuit reads the second boot instruction segment from the flash memory for the second time and reads the third boot instruction segment from the flash memory for the third time, and the corresponding storage addresses of the second boot instruction segment and the third boot instruction segment in the flash memory are discontinuous, so that two non-adjacent boot instruction segments are identified. Correspondingly, the state machine circuit is further configured to, after receiving a guidance request instruction sent by the MCU, trigger the first alternating buffer to send the first guidance instruction segment and the second guidance instruction segment to the MCU in sequence, and then trigger the second alternating buffer to send the third guidance instruction segment to the MCU, so as to avoid searching for two discontinuous guidance instruction segments one by one address unit in the same alternating buffer in the same timing cycle, but ensure that only two continuous guidance instruction segments can be searched in the same alternating buffer in the same timing cycle. It is noted that the state machine circuit receives only one piece of boot instructions from the flash memory output at a time. Therefore, if the state machine circuit reads three or more than three guide instruction segments, when two guide instruction segments which are read continuously by the state machine circuit for two times are continuous, the state machine circuit firstly enters the continuous access state, then the guide instruction segments which are read continuously for two times are controlled to be stored in the same alternate cache region, until the guide instruction segments which are read continuously by the state machine circuit for two times are not continuous, the state machine circuit jumps to the branch access state, controls the guide instruction segment which is read last time to be stored in another alternate cache region, and repeatedly detects whether the two guide instruction segments which are read continuously for two times are continuous, so that the next working state can be scheduled.
On the basis of the foregoing embodiment, whether in the continuous access state or the branch access state, the state machine circuit synchronously sends one piece of the boot instruction in one of the alternate buffers into the MCU and another piece of the boot instruction into the alternate buffer or another alternate buffer; in some embodiments, during the sending of the first boot instruction segment in the first alternate buffer to the MCU, a third boot instruction segment is synchronously sent into the first alternate buffer in the continuous access state, wherein for the state machine circuit, a read time of the second boot instruction segment is between a read time of the first boot instruction segment and a read time of the third boot instruction segment, the first boot instruction segment is not continuous with the third boot instruction segment, the second boot instruction segment is continuous with the first boot instruction segment, and the third boot instruction segment is continuous with the second boot instruction segment. In some embodiments, during the process of sending the first boot instruction segment in the first alternate buffer to the MCU, a third boot instruction segment is synchronously sent into the first alternate buffer in the branch access state, wherein, for the state machine circuit, the read time of the second boot instruction segment is between the read time of the first boot instruction segment and the read time of the third boot instruction segment, the first boot instruction segment is not continuous with the third boot instruction segment, the second boot instruction segment is discontinuous with the first boot instruction segment, and the third boot instruction segment is discontinuous with the second boot instruction segment. It is noted that the two alternative buffer areas are respectively located in different storage spaces in the MCU boot system. The method has the advantages that the problem that two discontinuous guide instruction sections are searched one by one in the same alternating cache region in the same time sequence period is avoided, the influence of the phenomenon that branch codes and instructions jump on the guide process of the MCU, particularly the influence of the continuity of transmission data can be reduced, the adaptability of the MCU to the guide instruction sections of the flash memory is improved, the guide starting period of the MCU is shortened compared with the prior art, and the function upgrading period of small wheeled robots (such as pet robots and tumbler robots) using the MCU which does not support the guide of the flash memory is shortened.
It should be noted that, the time consumed by the state machine circuit in the processing process of the two successively read guidance instruction segments is configured as a time sequence period, and the corresponding processing process includes sending the two successively read guidance instruction segments to the corresponding alternate cache region and sending the two successively read guidance instruction segments from the corresponding alternate cache region to the MCU. Therefore, the sum of the time spent on sending the two successively read guide instruction segments to the corresponding alternate cache region and the time spent on sending the two successively read guide instruction segments from the corresponding alternate cache region to the MCU is equal to one timing cycle.
In the above embodiment, an SPI interface is provided inside the state machine circuit, and the SPI interface is provided with four data input and output pins, i.e., IO0, IO1, IO2, and IO3, so as to provide four data signal lines to the outside; the SPI interface is also provided with a clock pin SCLK and a chip select pin/SS 1; as shown in fig. 1, IO0, IO1, IO2, and IO3 of the SPI interface of the flash memory are respectively connected to pins of the SPI interface of the state machine circuit with the same name, a clock pin SCK of the SPI interface of the flash memory is connected to a clock pin SCLK of the SPI interface of the state machine circuit, and a chip select pin/CS of the SPI interface of the flash memory is connected to a chip select pin/SS 1 of the SPI interface of the state machine circuit.
Specifically, the SPI interface of the flash memory is configured to be in a 4-line read mode, so that the SPI interface of the state machine circuit is also adaptively adjusted to be in the 4-line read mode, and then the SPI interface of the flash memory may be connected with the SPI interface of the state machine circuit through the SPI bus; under the triggering action of an external trigger signal or the configuration action of a fixed parameter built in the flash memory, a 4-line mode of the flash memory is started, at this time, the 4-line mode configured by the flash memory is relative to a standard single-line SPI protocol of the flash memory, the state machine circuit configures a write protection pin in 4-line transmission of the flash memory as a data input end IO2, configures a hold pin in 4-line transmission as a data input end IO3, and adaptively configures the write protection pin and the hold pin of an SPI interface of the state machine circuit as data inputs, so as to form 4 data lines with parallel transceiving functions in one SPI interface, so as to realize 4 bits transmitted in each clock cycle SCLK (clock signal transmitted by clock pin SCLK), and can be used for completing parallel transmission of a boot instruction segment in one clock cycle, a set of default matching parameters of a 4-line mode is built in the FLASH memory, so that after the MCU guidance system is combined with the FLASH memory, the FLASH memory supports guidance of MCUs of various models in a standard 4-line SPI transmission mode, and the problem of poor compatibility of the MCU to FLASH is solved.
The state machine circuit is configured to perform parallel-to-serial conversion on binary numbers corresponding to a guidance instruction segment received in parallel by 4 data input ends in a 4-line read mode of an SPI interface of the state machine circuit, and transmit the binary numbers to a corresponding alternate buffer area, where the 4 data input ends are connected to the SPI bus, and then the SPI interface in the 4-line read mode is set as a parallel interface supporting half-duplex and configured to transmit a control signal, an address signal, and a data signal included in the guidance instruction segment in parallel according to a set timing sequence, and accordingly, the SPI bus is a parallel bus in this embodiment; in one embodiment, when the state machine circuit is to send the boot instruction segment to the alternation buffer, since the state machine circuit reads the boot data (the boot instruction segment) of the flash memory by using a parallel bus and the alternation buffer uses a serial interface to send and receive data, the parallel-to-serial conversion is: the state machine circuit converts the guide instruction sections which are originally sent out in parallel through the SPI interface and transmitted in parallel through the SPI bus into write-in data which are transmitted through the serial port bus of the alternate cache area and received by the serial port interface. The state machine circuit reads the guide instruction section from the flash memory in parallel by adopting an SPI interface in a 4-line mode, and compared with the SPI interface in the 4-line mode, the serial interface adopted by the state machine circuit for writing the guide instruction section into the alternate cache region reduces the number of signal lines, reduces the number of cache chip pins, lightens the operation burden of the interface adopted for guiding the MCU to start, and saves the use area of a PCB (printed circuit board).
In the foregoing embodiment, the two consecutive boot instruction segments read by the state machine circuit are consecutive, which means that addresses corresponding to the two consecutive boot instruction segments read by the state machine circuit are consecutive, that is, a storage address corresponding to one of the boot instruction segments read earlier in the flash memory is adjacent to a storage address corresponding to one of the boot instruction segments read later in the flash memory; wherein the state machine circuit reads one boot instruction segment at a time from the flash memory.
On the other hand, in a specific implementation, some boot program data corresponding to jump branches which occur frequently may be stored in the flash memory. For example, for the verification required for starting the MCU, a loop operation needs to be executed or the same function needs to be called repeatedly, and the jump branch corresponding to the function operation is pre-stored in the flash memory. Specifically, the two boot instruction segments read successively by the state machine circuit are not consecutive, which means that addresses corresponding to the two boot instruction segments read successively by the state machine circuit are not consecutive, that is, a storage address corresponding to one boot instruction segment read earlier in the flash memory and a storage address corresponding to one boot instruction segment read later in the flash memory are not adjacent to each other; the state machine circuit reads one guide instruction segment from the flash memory each time, and then determines that a later read guide instruction segment jumps relative to a earlier read guide instruction segment, namely that the later read guide instruction segment generates a conditional branch relative to the earlier read guide instruction segment, and a dynamic instruction is integrally formed.
It should be noted that the boot instruction segment is boot program data pre-stored in the flash memory, specifically boot program data stored before the MCU is started each time, the boot program data configures the upgrade request port of the MCU to enter a boot mode, so as to perform normal read/write operation on the flash memory, and the MCU does not need to directly call a corresponding boot instruction segment from the flash memory, but supports the normal execution of the boot start process of the MCU through the MCU boot system; particularly, after the MCU is booted and started, the upgrade program in the MCU is further configured to take over the SPI interface of the state machine circuit, the SPI interface of the state machine circuit is used as the SPI interface of the MCU boot guidance system, the control authority of the SPI interface of the state machine circuit is handed over to the MCU, the MCU can directly perform read-write operation on the flash memory through the SPI bus, and the read data needs to be cached through the aforementioned alternate cache area in the specific implementation process; therefore, after the MCU is started, the MCU or the MCU starts a guide system to access data in the flash memory in the whole process through SPI bus transmission, wherein an SPI interface of the state machine circuit and the SPI bus reduce data conversion among different bus transmissions, so that the conversion process from the MCU to the state machine circuit or the parallel IO bus of the alternate cache region and the SPI bus can be saved, the guide starting period of the MCU in the prior art is shortened, and the function upgrading period of a small wheeled robot (such as a pet robot and a tumbler robot) using the MCU which does not support the flash memory guide with the SPI interface is shortened.
Preferably, in the two alternative cache regions, when no cache space remains in any of the two alternative cache regions, the boot instruction segment is stopped from being continuously read from the flash memory, and the flash memory is configured to be in a write-protected state. Therefore, the state machine circuit decides whether to continue reading the boot instruction segment from the flash memory or to perform a suspend operation on the flash memory according to the filling condition of each alternate buffer area. It is worth noting that if the boot instruction segment is continuously read from the flash memory, the write protection state of the relevant pin of the flash memory is released, so that the flash memory receives the request instruction parameter from the state machine circuit, the flash memory maintains the release of the write protection state after the MCU is booted and started, so that an upgrade program in the MCU takes over an SPI interface set by the MCU, and the SPI interface of the MCU can perform read-write operation on the flash memory through an SPI bus; if the flash memory is hung, setting a relevant pin of the flash memory to be in a write-protection state, and meanwhile, hanging the alternate buffer area by the state machine circuit, so that the situation that the flash memory or the alternate buffer area cannot be started due to possible accidental situations such as power failure and the like is avoided, and the MCU cannot be correctly guided and upgraded.
Preferably, the rate of reading the boot instruction segments by the state machine circuit through the SPI bus is greater than the rate of extracting the boot instruction segments from the alternate buffer by the MCU, so that the size of the rate of extracting the boot instruction segments from the alternate buffer of the state machine circuit by the MCU is determined by the size of the program data in the boot instruction segments. In one embodiment, the state machine circuit continuously reads the boot instruction segment from the flash memory, and continuously providing the currently cached guidance instruction segment to the MCU through two or one of the alternative cache regions, since the rate of the state machine circuit reading the boot instruction segment from the flash memory through the SPI bus is greater than the rate of the MCU fetching the boot instruction segment from the alternate buffer, therefore, it is ensured that at least one of the alternative buffer areas is not completely read by the MCU, so that the state machine circuit is unable to recognize other access operations of the MCU, and the continuity of the MCU booting system with the SPI interface is ensured, when the MCU boot system continuously boots the MCU for starting, the MCU does not know the specific source of the boot instruction section read by the MCU, that is, the MCU does not recognize that the boot instruction segment is actually stored in the flash memory; the MCU guide system does not identify the model of the MCU before guiding the MCU to start, and only transmits the guide instruction segment to the MCU to be started.
Based on the foregoing embodiment, the present invention further discloses a chip, wherein the MCU guidance system having the SPI interface is disposed inside the chip, and the driving circuit providing the MCU with the guidance function with logic hardware of higher integration level is convenient to assemble in the small wheeled mobile robot or other types of handheld mobile intelligent terminals that need to be guided to upgrade the function, wherein the guidance upgrade of the small wheeled mobile robot or other types of handheld mobile intelligent terminals depends on the start of the MCU therein, and the start of the MCU depends on the guidance of the MCU guidance system; specifically, in the chip, the aforementioned state machine circuit, two alternative buffers and associated configuration registers are all digital circuit modules compiled by a designer using a hardware description language Verilog HDL, or digital circuit modules compiled or compiled by a designer on software having a circuit drawing or compiling function. In addition, the MCU, the functional units and the flash memory in the embodiments of the present invention may be integrated in a main control circuit board to be assembled into a main control board occupying a small space volume inside an electronic device terminal or a mobile robot. The method and the device realize that a set of default boot commands are built in the flash memory to support the MCU, and meet the requirements of booting the MCU, booting the configuration MCU and booting the MCU for upgrading. Meanwhile, the probability of program operation abnormity caused by frequent code skipping is reduced; and further, the upgrade period of small wheeled robots (such as pet robots and tumbler robots) using the partial MCU which does not support SPI NorFlash guidance is shortened.
In the embodiments provided in the present application, it should be understood that the disclosed system and chip may be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Claims (11)
1. The MCU boot system with the SPI interface is characterized by comprising a state machine circuit and two alternate cache regions;
the state machine circuit is connected with a flash memory with an SPI interface through an SPI bus and used for reading a guide instruction segment from the flash memory;
when two guide instruction segments read successively by the state machine circuit are continuous, the state machine circuit is triggered to enter a continuous access state, the state machine circuit is used for sending the two guide instruction segments read successively into one of the alternate cache regions in the continuous access state, and then sending the two guide instruction segments received successively in the one of the alternate cache regions to the MCU;
when two guide instruction segments read successively by the state machine circuit are not continuous, the state machine circuit is triggered to enter a branch access state, and the state machine circuit is used for sending one guide instruction segment read earlier into one of the alternate cache regions and then sending one guide instruction segment read later into the other alternate cache region in the branch access state;
the state machine circuit is further configured to, in a branch access state, trigger one of the alternating cache regions to send a received one of the boot instruction segments to the MCU first, and then trigger the other of the alternating cache regions to send a received one of the boot instruction segments to the MCU, so as to avoid searching for two discontinuous boot instruction segments one by one address unit in the same alternating cache region.
2. The MCU boot system of claim 1, wherein the two alternating buffers are a first alternating buffer and a second alternating buffer, respectively;
if the first guide instruction segment and the second guide instruction segment which are read successively are not continuous and the second guide instruction segment and the third guide instruction segment which are read successively are not continuous, the state machine circuit is used for sending the first guide instruction segment into the first alternate cache region, then sending the second guide instruction segment into the second alternate cache region and then sending the third guide instruction segment into the first alternate cache region in the branch access state; the state machine circuit is further configured to, in a branch access state, trigger the first alternating cache region to send the first guidance instruction segment to the MCU, trigger the second alternating cache region to send the second guidance instruction segment to the MCU, and trigger the first alternating cache region to send the third guidance instruction segment to the MCU, so as to avoid searching for two discontinuous guidance instruction segments one by one address unit in the same alternating cache region in the same timing cycle.
3. The MCU boot system of claim 1, wherein the two alternating buffers are a first alternating buffer and a second alternating buffer, respectively;
if the first guide instruction segment and the second guide instruction segment read successively by the state machine circuit are not continuous, the state machine circuit jumps to the branch access state, and the state machine circuit sends the first guide instruction segment to a first alternate cache region and then sends the second guide instruction segment to a second alternate cache region in the branch access state;
then, if the second leading instruction segment and the third leading instruction segment read successively by the state machine circuit are continuous, the state machine circuit jumps to the continuous access state from the branch access state, and the state machine circuit sends the third leading instruction segment to a second alternate cache region in the continuous access state;
the state machine circuit is further configured to trigger the first alternating cache region to send the first guidance instruction segment to the MCU, and then trigger the second alternating cache region to send the two guidance instruction segments received successively to the MCU in sequence, so as to avoid searching for two discontinuous guidance instruction segments one by one address unit in the same alternating cache region in the same timing cycle.
4. The MCU boot system according to claim 1, wherein when the two consecutive read boot instruction segments of the state machine circuit are consecutive, the state machine circuit enters the continuous access state, and then controls the two consecutive read boot instruction segments to be stored in the same alternate buffer area until the state machine circuit skips to the branch access state and controls the latest read boot instruction segment to be stored in another alternate buffer area when the two consecutive read boot instruction segments of the state machine circuit are not consecutive.
5. MCU boot system according to any of claims 2 to 4, characterized in that in the process of sending a boot instruction segment in an alternate buffer to the MCU, another boot instruction segment is synchronously sent to the alternate buffer or another alternate buffer; the two alternate cache regions are respectively positioned in different storage spaces in the MCU guide system;
the processing process comprises the steps of sending the two successively read guide instruction segments to corresponding alternate cache regions and sending the two successively read guide instruction segments to the MCU from the corresponding alternate cache regions.
6. The MCU guidance system according to any one of claims 2 to 4, wherein an SPI interface is provided in the state machine circuit;
each functional pin of the SPI interface of the flash memory is connected with the corresponding functional pin of the SPI interface of the state machine circuit through an SPI bus; the SPI interface of the flash memory is configured to be in a 4-line reading mode, so that the SPI interface of the state machine circuit is also adaptively adjusted to be in the 4-line reading mode;
the write protection pin and the holding pin of the SPI interface of the state machine circuit are both configured as data input ends so as to form 4 data lines with parallel data receiving and transmitting functions in one SPI interface and read a guide instruction section in one clock cycle;
the state machine circuit is used for performing parallel-to-serial conversion on binary numbers corresponding to the guide instruction segments received by 4 data input ends in parallel in a 4-line read mode of the SPI interface of the state machine circuit, and then transmitting the binary numbers to a corresponding alternate cache region; wherein, the alternate buffer area uses serial interface to receive and transmit data.
7. The MCU guidance system according to claim 6, wherein the two guidance instruction segments read successively by the state machine circuit are consecutive, which indicates that addresses corresponding to the two guidance instruction segments read successively by the state machine circuit are consecutive;
the two leading instruction segments read successively by the state machine circuit are not continuous, which indicates that the addresses corresponding to the two leading instruction segments read successively by the state machine circuit are not continuous, and then a leading instruction segment read later is determined to jump relative to a leading instruction segment read earlier;
the boot instruction segment is boot program data stored in the flash memory in advance, and the boot program data configures an upgrade request port of the MCU to enter a boot mode.
8. The MCU boot system according to any one of claims 2 to 4, wherein in the two alternative buffers, when no buffer space remains in either of the alternative buffers, the flash memory stops reading the boot instruction segment continuously and is configured to be in a write-protected state.
9. The MCU boot system of claim 8, wherein the rate at which the state machine circuit reads the boot instruction segments via the SPI bus is greater than the rate at which the MCU fetches the boot instruction segments from the alternate buffer.
10. The MCU boot system of claim 7, wherein after the MCU is booted and started, the upgrade program in the MCU is further configured to take over an SPI interface of the state machine circuit, so that the MCU performs read-write operations on the flash memory through the SPI interface and an SPI bus connected thereto, thereby reducing data conversion between different bus transmissions.
11. A chip, characterized in that, the MCU boot system with SPI interface of any one of claims 1 to 10 is disposed inside the chip.
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