CN114023855B - Light-emitting diode chip, preparation method thereof and display device - Google Patents
Light-emitting diode chip, preparation method thereof and display device Download PDFInfo
- Publication number
- CN114023855B CN114023855B CN202111136695.2A CN202111136695A CN114023855B CN 114023855 B CN114023855 B CN 114023855B CN 202111136695 A CN202111136695 A CN 202111136695A CN 114023855 B CN114023855 B CN 114023855B
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor layer
- light emitting
- emitting diode
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 170
- 239000000463 material Substances 0.000 claims description 58
- 238000002161 passivation Methods 0.000 claims description 58
- 238000003892 spreading Methods 0.000 claims description 32
- 230000007480 spreading Effects 0.000 claims description 32
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 21
- 238000000059 patterning Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 238000000034 method Methods 0.000 description 28
- 230000008569 process Effects 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 230000000694 effects Effects 0.000 description 11
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 229910002601 GaN Inorganic materials 0.000 description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- BEQNOZDXPONEMR-UHFFFAOYSA-N cadmium;oxotin Chemical compound [Cd].[Sn]=O BEQNOZDXPONEMR-UHFFFAOYSA-N 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- NQBRDZOHGALQCB-UHFFFAOYSA-N oxoindium Chemical compound [O].[In] NQBRDZOHGALQCB-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000005019 vapor deposition process Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
Abstract
The application relates to a light emitting diode chip, a preparation method thereof and a display device. The light emitting diode chip includes at least one light emitting diode. The light emitting diode includes: the semiconductor device comprises a first semiconductor layer, a light emitting layer, a second semiconductor layer, a ring-shaped supporting structure and a first bonding pad. Wherein the first semiconductor layer, the light emitting layer and the second semiconductor layer are sequentially stacked. A groove is provided in the stacked structure of the second semiconductor layer and the light emitting layer, the groove exposing a portion of the first semiconductor layer. The annular supporting structure is arranged in the groove. The first bonding pad is positioned on one side of the annular supporting structure, which is away from the first semiconductor layer, and penetrates through the annular region of the annular supporting structure to be connected with the first semiconductor layer. The light-emitting diode chip and the preparation method thereof can improve the transfer yield of the light-emitting diode chip.
Description
Technical Field
The application relates to the technical field of display and illumination, in particular to a light emitting diode chip, a preparation method thereof and a display device.
Background
Micro light emitting diodes (Micro-LEDs) and Mini light emitting diodes (Mini-LEDs) are miniaturized conventional LEDs. For example, micro-LEDs have a size of 1 μm to 100 μm and Mini-LED chips have a size of 50 μm to 200. Mu.m. The Micro-LED and the Mini-LED have the advantages of small volume, high resolution, high contrast ratio, low power consumption and the like.
The LED chip is integrated as an array of Micro-LEDs or Mini-LEDs, and the LED chip is largely transferred in a transfer mode. For example, using an adapter, the LED chip may be transferred to the back plate. In this way, the LED chip can be fixed on the back plate by bonding the bonding pads in the LED chip with the metal electrodes in the back plate at high temperature. However, as the LED size is reduced again and again, after the LED chips are transferred in large quantities, an abnormality of the LED chips being not firmly fixed easily occurs, resulting in a reduction in the transfer yield of the LED chips.
Therefore, how to improve the transfer yield of the LED chip is a problem to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present application is to provide a light emitting diode chip, a manufacturing method thereof, and a display device, which are aimed at solving the problem of how to increase the transfer yield of the light emitting diode chip.
The embodiment of the application provides a light-emitting diode chip, which comprises at least one light-emitting diode. The light emitting diode includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, a ring-shaped support structure, and a first bonding pad. Wherein the first semiconductor layer, the light emitting layer and the second semiconductor layer are sequentially stacked. A groove is provided in the stacked structure of the second semiconductor layer and the light emitting layer, the groove exposing a portion of the first semiconductor layer. The annular supporting structure is arranged in the groove. The first bonding pad is positioned on one side of the annular supporting structure, which is away from the first semiconductor layer, and penetrates through the annular region of the annular supporting structure to be connected with the first semiconductor layer.
In the above light emitting diode chip, the to-be-connected region of the first semiconductor layer is provided with a groove, and an annular supporting structure is disposed in the groove. Therefore, the first bonding pad and the first semiconductor layer can be connected through the ring-in area of the annular supporting structure, and meanwhile, the annular supporting structure is used for supporting the first bonding pad, so that the situation that the first bonding pad is partially sunken is avoided. Based on the above, in the process of transferring a large amount of light-emitting diode chips, the first bonding pad can have good surface contact effect and larger contact area with the metal layer of the backboard, so that the abnormal condition that the first bonding pad is not firmly fixed with the metal layer of the backboard is avoided, and the transfer yield of the light-emitting diode chips can be effectively improved.
Optionally, the light emitting diode further includes: a current spreading layer, a passivation layer and a second pad. The current spreading layer partially covers the second semiconductor layer. The passivation layer covers the exposed surfaces of the current spreading layer, the second semiconductor layer, the light emitting layer and the first semiconductor layer, and the exposed surface of the annular support structure outside the annular region. The passivation layer has a first opening and a second opening. The first opening exposes the ring-in region, and the first bonding pad is disposed in the first opening. The second opening exposes a portion of the current spreading layer. The second bonding pad is arranged in the second opening and connected with the current expansion layer.
In the light-emitting diode chip, the passivation layer covers the exposed surfaces of the current expansion layer, the second semiconductor layer, the light-emitting layer and the first semiconductor layer, and the exposed surface of the annular supporting structure, which is positioned outside the annular area, is beneficial to ensuring the surface of the passivation layer, which is far away from the first semiconductor layer, to be smooth. Based on the structure, the first bonding pad is arranged in the first opening of the passivation layer, and the second bonding pad is arranged in the second opening of the passivation layer, so that the surfaces of the first bonding pad and the second bonding pad, which are away from the first semiconductor layer, are located on the same plane. Therefore, in the process of transferring a large amount of light-emitting diode chips, the first bonding pad and the second bonding pad can be further ensured to have good surface contact effect and larger contact area with the metal layer of the backboard.
Optionally, a space is provided between the annular supporting structure and the side wall of the groove; portions of the passivation layer fill the spacers. In this way, it is convenient to uniformly distribute the passivation layer forming material in different areas so as to ensure the forming surface of the passivation layer to be flat.
Optionally, the radial dimension of the ring-in region of the annular support structure comprises: 1 μm to 3 μm. The radial dimensions of the groove include: 12-30 μm.
Optionally, the annular support structure comprises: the first annular support layer and the second annular support layer are stacked in a direction away from the first semiconductor layer. The thickness of the first annular supporting layer is the same as that of the light-emitting layer. The thickness of the second annular supporting layer is the same as that of the second semiconductor layer.
In the light emitting diode chip, the annular supporting structure is formed by stacking the first annular supporting layer and the second annular supporting layer, the thickness of the first annular supporting layer is the same as that of the light emitting layer, the thickness of the second annular supporting layer is the same as that of the second semiconductor layer, the surface of the annular supporting structure, which is away from the first semiconductor layer, and the surface of the second semiconductor layer, which is away from the first semiconductor layer, can be ensured to be flush, and further, the surface of the passivation layer formed later is ensured to be relatively flat.
Optionally, the material of the first annular supporting layer is the same as the material of the light emitting layer. The material of the second annular supporting layer is the same as that of the second semiconductor layer.
In the light-emitting diode chip, the annular supporting structure, the light-emitting layer and the second semiconductor layer can be prepared through the same photoetching process, so that the preparation flow of the light-emitting diode chip is simplified, and the production efficiency and the production yield of the light-emitting diode chip are improved.
Based on the same inventive concept, the embodiment of the application also provides a preparation method of the light emitting diode chip, which comprises the following steps.
And growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises a first semiconductor material layer, a luminescent material layer and a second semiconductor material layer which are sequentially stacked.
The light emitting material layer and the second semiconductor material layer are patterned to form a light emitting layer, a second semiconductor layer, and a ring-shaped support structure. The laminated structure of the second semiconductor layer and the light-emitting layer is provided with a groove, and the annular supporting structure is positioned in the groove.
The first semiconductor material layer is patterned to form a first semiconductor layer.
And forming a first bonding pad and a second bonding pad on one side of the annular supporting structure, which is far away from the first semiconductor layer, wherein the second bonding pad is connected with the second semiconductor layer, and the first bonding pad penetrates through the annular region of the annular supporting structure to be connected with the first semiconductor layer.
In the method for manufacturing the light emitting diode chip, after the light emitting material layer and the second semiconductor material layer are patterned, the light emitting layer, the second semiconductor layer and the annular supporting structure can be formed synchronously, so that the etching area of the light emitting material layer and the etching area of the second semiconductor material layer are reduced. Therefore, the first bonding pad and the first semiconductor layer can be connected by utilizing the ring-in area of the annular supporting structure, and meanwhile, the first bonding pad is supported by utilizing the annular supporting structure, so that the situation that the first bonding pad is partially sunken is avoided. Therefore, in the subsequent process of transferring the light-emitting diode chips in a large quantity, the first bonding pad can have good surface contact effect and larger contact area with the metal layer of the backboard, so that the abnormal condition that the first bonding pad is not firmly fixed with the metal layer of the backboard is avoided, and the transfer yield of the light-emitting diode chips can be effectively improved.
In addition, in the preparation method of the light-emitting diode chip, the annular supporting structure, the light-emitting layer and the second semiconductor layer are synchronously formed by utilizing the light-emitting material layer and the second semiconductor material layer, so that the preparation flow of the light-emitting diode chip can be simplified, and the production efficiency and the production yield of the light-emitting diode chip can be improved.
Optionally, before forming the first bonding pad and the second bonding pad on the side of the annular supporting structure facing away from the first semiconductor layer, the method for manufacturing the light emitting diode further includes the following steps.
And forming a current expansion layer on the surface of the second semiconductor layer, which is away from the light-emitting layer.
A passivation layer is formed on exposed surfaces of the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the current spreading layer, and exposed surfaces of the annular support structure outside the annular region. The passivation layer has a first opening and a second opening. The first opening exposes an annular region of the annular support structure, and the second opening exposes a portion of the current spreading layer.
Accordingly, forming a first pad and a second pad on a side of the annular support structure facing away from the first semiconductor layer, comprising: a first bonding pad is formed in the first opening, and a second bonding pad is formed in the second opening, and the second bonding pad is connected with the second semiconductor layer through the current spreading layer.
In the method for manufacturing the light-emitting diode chip, the passivation layer is formed on the exposed surfaces of the current expansion layer, the second semiconductor layer, the light-emitting layer and the first semiconductor layer and the exposed surface of the annular supporting structure, which is positioned outside the annular area, so that the surface of the passivation layer, which is far away from the first semiconductor layer, is smooth. Based on the above, the first bonding pad is formed in the first opening of the passivation layer, and the second bonding pad is formed in the second opening of the passivation layer, so that the surfaces of the first bonding pad and the second bonding pad, which are away from the first semiconductor layer, are located on the same plane. Therefore, in the subsequent process of transferring a large amount of light-emitting diode chips, the first bonding pad and the second bonding pad can be further ensured to have good surface contact effect and larger contact area with the metal layer of the backboard.
Optionally, a space is provided between the annular supporting structure and the side wall of the groove; portions of the passivation layer fill the spacers. In this way, it is convenient to uniformly distribute the passivation layer forming material in different areas so as to ensure the forming surface of the passivation layer to be flat.
Based on the same inventive concept, the embodiment of the application also provides a display device, which comprises a driving circuit and a light emitting unit connected with the driving circuit; wherein the light emitting unit comprises the light emitting diode chip in some embodiments. The technical effects achieved by the led chip can be achieved by the display device, and the detailed description thereof is omitted.
Drawings
FIG. 1 is a schematic cross-sectional view of a light emitting diode chip according to an embodiment;
FIG. 2 is a schematic top view of a light emitting diode chip according to an embodiment;
FIG. 3 is a schematic flow chart of a method for manufacturing a light emitting diode chip according to an embodiment;
FIG. 4 is a schematic flow chart of another method for manufacturing a light emitting diode chip according to an embodiment;
FIG. 5 is a schematic cross-sectional view of the structure obtained in step S100 according to an embodiment;
FIG. 6a is a schematic cross-sectional view of the structure obtained in step S200 according to an embodiment;
FIG. 6b is a schematic top view of the structure obtained in step S200 according to an embodiment;
FIG. 7a is a schematic cross-sectional view of the structure obtained in step S300 according to an embodiment;
FIG. 7b is a schematic top view of the structure obtained in step S300 according to an embodiment;
FIG. 8a is a schematic cross-sectional view of the structure obtained in step S310 according to an embodiment;
FIG. 8b is a schematic top view of the structure obtained in step S310 according to an embodiment;
FIG. 9a is a schematic cross-sectional view of the structure obtained in step S320 according to an embodiment;
FIG. 9b is a schematic top view of the structure obtained in step S320 according to an embodiment;
FIG. 10a is a schematic cross-sectional view of the structure obtained in step S400 according to an embodiment;
fig. 10b is a schematic top view of the structure obtained in step S400 according to an embodiment.
Reference numerals illustrate:
1-a light emitting diode; 10-a substrate; 200-an epitaxial layer; 210-a first semiconductor material layer;
21-a first semiconductor layer; 220-a layer of luminescent material; 22-a light emitting layer;
230-a layer of a second semiconductor material; 23-a second semiconductor layer; 30-an annular support structure;
31-a first annular support layer; 32-a second annular support layer; 41-a first bonding pad;
42-a second bonding pad; 50-a current spreading layer; a 60-passivation layer; g-grooves;
h-ring inner region; k1-a first opening; k2—a second opening;
r1-radial dimension of the groove; radial dimension of the R2-ring inner region.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the application. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Micro light emitting diodes (Micro-LEDs) and Mini light emitting diodes (Mini-LEDs) are miniaturized conventional LEDs. For example, micro-LEDs have a size of 1 μm to 100 μm and Mini-LED chips have a size of 50 μm to 200. Mu.m. The Micro-LED and the Mini-LED have the advantages of small volume, high resolution, high contrast ratio, low power consumption and the like.
The LED chip is integrated as an array of Micro-LEDs or Mini-LEDs, and the LED chip is largely transferred in a transfer mode. For example, using an adapter, the LED chip may be transferred to the back plate. In this way, the LED chip can be fixed on the back plate by bonding the bonding pads in the LED chip with the metal electrodes in the back plate at high temperature. However, as the LED size is reduced again and again, after the LED chips are transferred in large quantities, an abnormality of the LED chips being not firmly fixed easily occurs, resulting in a reduction in the transfer yield of the LED chips.
Based on this, the present application is intended to provide a solution to the above technical problem, the details of which will be described in the following examples.
Referring to fig. 1 and 2, an embodiment of the present application provides a light emitting diode chip, including: at least one light emitting diode 1. The light emitting diode 1 includes: the semiconductor device includes a first semiconductor layer 21, a light emitting layer 22, a second semiconductor layer 23, a ring-shaped support structure 30, a current spreading layer 50, a passivation layer 60, a first pad 41, and a second pad 42.
The first semiconductor layer 21, the light-emitting layer 22, and the second semiconductor layer 23 are stacked in this order. A groove G is provided in the stacked structure of the second semiconductor layer 23 and the light emitting layer 22, the groove G exposing a portion of the first semiconductor layer 21.
Alternatively, the first semiconductor layer 21 is an N-type gallium nitride layer, the light emitting layer 22 is a multiple quantum well layer, and the second semiconductor layer 23 is a P-type gallium nitride layer.
The recess G is used to expose a portion of the first semiconductor layer 21, and penetrates the stacked structure of the second semiconductor layer 23 and the light emitting layer 22. The shape and size of the groove G can be selected and set according to actual requirements.
Alternatively, the groove G is a cylindrical groove, but is not limited thereto.
Optionally, the radial dimension R1 of the groove G includes: 12-30 μm. For example, the radial dimension R1 of the groove G is 12 μm, 15 μm, 20 μm, 25 μm or 30 μm. In the example where the groove G is a non-cylindrical groove, the radial dimension R1 of the groove G refers to a dimension thereof in the cross-sectional direction, for example, a maximum dimension of the groove G in the cross-sectional direction, or a minimum dimension of the groove G in the cross-sectional direction.
The annular support structure 30 is disposed within the recess G. Annular support structure 30 refers to a support structure disposed in a closed loop including, but not limited to, a circular loop or a square loop. The annular support structure 30 has an annular region H, the shape of which is related to the annular shape of the annular support structure 30.
Alternatively, the ring-in region H is columnar, but is not limited thereto.
Optionally, the radial dimension R2 of the ring inner region H comprises: 1 μm to 3 μm. For example, the radial dimension R2 of the in-loop region H is 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm. In the example where the in-loop region H is non-columnar, the radial dimension R2 of the in-loop region H refers to its dimension in the cross-sectional direction, for example, the largest dimension of the in-loop region H in the cross-sectional direction, or the smallest dimension of the in-loop region H in the cross-sectional direction.
Referring to fig. 1, the current spreading layer 50 partially covers the second semiconductor layer 23. That is, the orthographic projection of the current spreading layer 50 on the first semiconductor layer 21 is located within the range of the orthographic projection of the second semiconductor layer 23 on the first semiconductor layer 21.
Alternatively, the current spreading layer 50 is formed by using a transparent conductive material having high visible light transmittance and high conductivity. The transparent conductive material is, for example, indium Tin Oxide (ITO), zinc oxide (ZnO), cadmium Tin Oxide (CTO), indium oxide (InO), indium (In) -doped zinc oxide (ZnO), aluminum (Al) -doped zinc oxide (ZnO), gallium (Ga) -doped zinc oxide (ZnO), or the like. In one example, the current spreading layer 50 is an ITO layer.
The current spreading layer 50 has high conductivity and high visible light transmittance, and can effectively improve the light-emitting efficiency of the light-emitting layer 22.
With continued reference to fig. 1, the passivation layer 60 covers the exposed surfaces of the current spreading layer 50, the second semiconductor layer 23, the light emitting layer 22 and the first semiconductor layer 21, and the exposed surface of the ring-shaped support structure 30 outside the ring-shaped region H. The passivation layer 60 has a first opening K1 and a second opening K2. The first opening K1 exposes the ring inner region H of the annular support structure 30. The second opening K2 exposes a portion of the current spreading layer 50.
Alternatively, the passivation layer 60 is silicon dioxide (SiO 2 ) A layer.
Optionally, the annular support structure 30 is spaced from the side walls of the recess G; portions of passivation layer 60 fill the spaces. In this way, it is facilitated to uniformly distribute the formation material of the passivation layer 60 in different regions, which is advantageous to ensure that the surface of the passivation layer 60 facing away from the first semiconductor layer 21 is planar.
Referring to fig. 1 and 2, the first bonding pad 41 is located on a side of the annular supporting structure 30 facing away from the first semiconductor layer 21, for example, in the first opening K1. The first pad 41 is connected to the first semiconductor layer 21 through the in-loop region H of the loop-shaped support structure 30. The second pad 42 is disposed in the second opening K2 and connected to the current spreading layer 50.
Optionally, the surface of the first pad 41 facing away from the passivation layer 60 and the surface of the second pad 42 facing away from the passivation layer 60 are both higher than the surface of the passivation layer 60 facing away from the substrate 10. In this way, it is convenient to bond the first pads 41 and the second pads 42 correspondingly with external electrical devices (e.g., metal layers of the back plate).
Optionally, the surface of the first pad 41 facing away from the passivation layer 60 and the surface of the second pad 42 facing away from the passivation layer 60 are located on the same plane. In this way, in the subsequent process of transferring a large amount of light emitting diode chips, the first bonding pad 41 and the second bonding pad 42 can have good surface contact effect and larger contact area with the metal layer of the backboard.
In the embodiment of the application, the groove G is formed in the to-be-connected region of the first semiconductor layer 21, and the annular supporting structure 30 is disposed in the groove G, so that the connection between the first bonding pad 41 and the first semiconductor layer 21 can be realized by using the annular region H of the annular supporting structure 30. The annular supporting structure 30 is used for supporting the first bonding pad 41 at the same time, so that the situation that the first bonding pad 41 is partially recessed is avoided. In this way, in the process of transferring a large amount of light emitting diode chips, the first bonding pad 41 can have good surface contact effect and larger contact area with the metal layer of the backboard, so that the abnormal that the first bonding pad 41 is not firmly fixed with the metal layer of the backboard is avoided, and the transfer yield of the light emitting diode chips can be effectively improved.
In some embodiments, with continued reference to fig. 1 and 2, the annular support structure 30 includes: the first annular support layer 31 and the second annular support layer 32 are stacked in a direction away from the first semiconductor layer 21. Wherein the thickness of the first annular supporting layer 31 is the same as the thickness of the light emitting layer 22. The thickness of the second annular supporting layer 32 is the same as the thickness of the second semiconductor layer 23. In this way, the surface of the annular supporting structure 30 facing away from the first semiconductor layer 21 is flush with the surface of the second semiconductor layer 23 facing away from the first semiconductor layer 21, so that it is beneficial to ensure that the surface of the passivation layer formed later is relatively flat.
In some embodiments, referring to fig. 1 and 2, the material of the first annular supporting layer 31 is the same as the material of the light emitting layer 22. The material of the second annular supporting layer 32 is the same as that of the second semiconductor layer 23. In this way, the annular supporting structure 30 and the light-emitting layer 22 and the second semiconductor layer 23 can be prepared by the same photolithography process, so as to simplify the preparation process of the light-emitting diode chip, thereby improving the production efficiency and the production yield of the light-emitting diode chip.
In some embodiments, referring to fig. 1, the light emitting diode chip further includes a substrate 10. The first semiconductor layer 21, the light-emitting layer 22, and the second semiconductor layer 23 are sequentially stacked on the substrate 10.
Alternatively, the substrate 10 is, but is not limited to, a sapphire substrate, a silicon carbide substrate, a silicon substrate, or a gallium nitride substrate.
Referring to fig. 3, an embodiment of the present application further provides a method for manufacturing a light emitting diode chip, which is used for manufacturing the light emitting diode chip in some embodiments. The preparation method comprises the following steps.
And S100, growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises a first semiconductor material layer, a luminescent material layer and a second semiconductor material layer which are sequentially stacked.
And S200, patterning the light-emitting material layer and the second semiconductor material layer to form a light-emitting layer, a second semiconductor layer and a ring-shaped supporting structure. The laminated structure of the second semiconductor layer and the light-emitting layer is provided with a groove, and the annular supporting structure is positioned in the groove.
And S300, patterning the first semiconductor material layer to form a first semiconductor layer.
And S400, forming a first bonding pad and a second bonding pad on one side of the annular supporting structure, which is far away from the first semiconductor layer, wherein the second bonding pad is connected with the second semiconductor layer, and the first bonding pad penetrates through the annular region of the annular supporting structure to be connected with the first semiconductor layer.
In the embodiment of the application, after the luminescent material layer and the second semiconductor material layer are patterned, the luminescent layer, the second semiconductor layer and the annular supporting structure can be synchronously formed, so that the etching area of the luminescent material layer and the second semiconductor material layer is reduced. Therefore, the first bonding pad and the first semiconductor layer can be connected by utilizing the ring-in area of the annular supporting structure, and meanwhile, the first bonding pad is supported by utilizing the annular supporting structure, so that the situation that the first bonding pad is partially sunken is avoided. Therefore, in the subsequent process of transferring the light-emitting diode chips in a large quantity, the first bonding pad can have good surface contact effect and larger contact area with the metal layer of the backboard, so that the abnormal condition that the first bonding pad is not firmly fixed with the metal layer of the backboard is avoided, and the transfer yield of the light-emitting diode chips can be effectively improved.
In addition, in the preparation method of the light-emitting diode chip, the annular supporting structure, the light-emitting layer and the second semiconductor layer are synchronously formed by utilizing the light-emitting material layer and the second semiconductor material layer, so that the preparation flow of the light-emitting diode chip can be simplified, and the production efficiency and the production yield of the light-emitting diode chip can be improved.
As described in some embodiments above, referring to fig. 4, before S400 is performed, that is, before the first bonding pad and the second bonding pad are formed on the side of the annular supporting structure facing away from the first semiconductor layer, the method for manufacturing the LED further includes the following steps.
And S310, forming a current expansion layer on the surface of the second semiconductor layer, which is away from the light-emitting layer.
And S320, forming passivation layers on the exposed surfaces of the first semiconductor layer, the light emitting layer, the second semiconductor layer and the current spreading layer and the exposed surface of the annular supporting structure, which is positioned outside the annular region. The passivation layer has a first opening and a second opening. The first opening exposes an annular region of the annular support structure, and the second opening exposes a portion of the current spreading layer.
Accordingly, forming a first pad and a second pad on a side of the annular support structure facing away from the first semiconductor layer in S400 includes: a first bonding pad is formed in the first opening, and a second bonding pad is formed in the second opening, and the second bonding pad is connected with the second semiconductor layer through the current spreading layer.
In the embodiment of the application, the passivation layer is formed on the exposed surfaces of the current expansion layer, the second semiconductor layer, the light-emitting layer and the first semiconductor layer and the exposed surface of the annular supporting structure, which is positioned outside the annular area, so that the surface of the passivation layer, which is away from the first semiconductor layer, is smooth. Based on the above, the first bonding pad is formed in the first opening of the passivation layer, and the second bonding pad is formed in the second opening of the passivation layer, so that the surfaces of the first bonding pad and the second bonding pad, which are away from the first semiconductor layer, are located on the same plane. Therefore, in the subsequent process of transferring a large amount of light-emitting diode chips, the first bonding pad and the second bonding pad can be further ensured to have good surface contact effect and larger contact area with the metal layer of the backboard.
The following describes in detail the method for manufacturing the led chip according to the embodiment of the present application with reference to fig. 5 to 10 b.
In step S100, referring to fig. 5, an epitaxial layer 200 is grown on a substrate 10, and the epitaxial layer 200 includes a first semiconductor material layer 210, a light emitting material layer 220, and a second semiconductor material layer 230 sequentially stacked.
In some examples, substrate 10 may be, but is not limited to, a sapphire substrate, a silicon carbide substrate, a silicon substrate, or a gallium nitride substrate.
In some examples, the first semiconductor material layer 210, the light emitting material layer 220, and the second semiconductor material layer 230 are sequentially stacked in a direction away from the substrate 10.
Alternatively, the first semiconductor material layer 210 is an N-type gallium nitride layer, the light emitting material layer 220 is a multiple quantum well layer, and the second semiconductor material layer 230 is a P-type gallium nitride layer.
In step S200, referring to fig. 6a and 6b, the light emitting material layer 220 and the second semiconductor material layer 230 are patterned to form the light emitting layer 22, the second semiconductor layer 23, and the annular support structure 30. The stacked structure of the second semiconductor layer 23 and the light emitting layer 22 has a groove G therein, and the annular support structure 30 is located in the groove G.
The recess G is used to expose a portion of the first semiconductor layer 21, and penetrates the stacked structure of the second semiconductor layer 23 and the light emitting layer 22. The shape and size of the groove G can be selected and set according to actual requirements.
Alternatively, the groove G is a cylindrical groove, but is not limited thereto.
Optionally, the radial dimension of the groove G includes: 12-30 μm. For example, the radial dimension R1 of the groove G is 12 μm, 15 μm, 20 μm, 25 μm or 30 μm. In the example where the groove G is a non-cylindrical groove, the radial dimension of the groove G refers to the dimension thereof in the cross-sectional direction, for example, the largest dimension of the groove G in the cross-sectional direction, or the smallest dimension of the groove G in the cross-sectional direction.
The annular support structure 30 is disposed within the recess G. Annular support structure 30 refers to a support structure disposed in a closed loop including, but not limited to, a circular loop or a square loop. The annular support structure 30 has an annular region H, the shape of which is related to the annular shape of the annular support structure 30.
Alternatively, the ring-in region H is columnar, but is not limited thereto.
Optionally, the radial dimension of the in-loop region H includes: 1 μm to 3 μm. For example, the radial dimension of the in-loop region H is 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm. In the example where the in-loop region H is non-columnar, the radial dimension of the in-loop region H refers to its dimension in the cross-sectional direction, for example, the largest dimension of the in-loop region H in the cross-sectional direction, or the smallest dimension of the in-loop region H in the cross-sectional direction.
In step S300, referring to fig. 7a and 7b, the first semiconductor material layer 210 is patterned to form a first semiconductor layer 21.
Here, the profile of the first semiconductor layer 21 may be obtained by an etching process, such as a dry etching process, but is not limited thereto. The etching rate of the dry etching is high, and the edge side erosion phenomenon caused by the dry etching is very small, so that the first semiconductor layer 21 is prepared by adopting the dry etching, the implementation is easy, and the molding contour of the first semiconductor layer 21 can be well controlled.
Furthermore, the profiled contour of the first semiconductor layer 21 may define the profiled contour of the individual light-emitting diodes 1.
In step S310, referring to fig. 8a and 8b, a current spreading layer 50 is formed on a surface of the second semiconductor layer 23 facing away from the light emitting layer 22.
Here, the current spreading layer 50 partially covers the second semiconductor layer 23, and the current spreading layer 50 may be formed using a sputtering process or an evaporation process. The sputtering process is, for example, a magnetron sputtering process or an ion beam sputtering process. The vapor deposition process is, for example, an electron beam vapor deposition process.
Alternatively, the material of the current spreading layer 50 is a transparent conductive material with high visible light transmittance and high conductivity, such as Indium Tin Oxide (ITO), zinc oxide (ZnO), cadmium Tin Oxide (CTO), indium oxide (InO), indium (In) doped zinc oxide (ZnO), aluminum (Al) doped zinc oxide (ZnO), or gallium (Ga) doped zinc oxide (ZnO).
In one example, the current spreading layer 50 is an ITO layer.
In step S320, referring to fig. 9a and 9b, passivation layers 60 are formed on the exposed surfaces of the first semiconductor layer 21, the light emitting layer 22, the second semiconductor layer 23 and the current spreading layer 50, and the exposed surface of the annular support structure 30 outside the annular ring region H. The passivation layer 60 has a first opening K1 and a second opening K2. The first opening K1 exposes an in-loop region of the annular support structure 30 and the second opening K2 exposes a portion of the current spreading layer 50.
Alternatively, the passivation layer 60 is silicon dioxide (SiO 2 ) A layer.
Optionally, the annular support structure 30 is spaced from the side walls of the recess G; portions of passivation layer 60 fill the spaces. In this manner, it is convenient to uniformly distribute the formation material of the passivation layer 60 in different regions to ensure that the formation surface of the passivation layer 60 is flat.
In step S400, referring to fig. 10a and 10b, a first pad 41 is formed in the first opening K1, and the first pad 41 is connected to the first semiconductor layer 21 through the in-loop region H of the annular support structure 30. Meanwhile, a second pad 42 is formed in the second opening K2, and the second pad 42 is connected to the second semiconductor layer 23 through the current spreading layer 50.
Alternatively, the first pad 41 and the second pad 42 are formed using an evaporation process, for example, an electron beam evaporation process.
Optionally, the surface of the first pad 41 facing away from the passivation layer 60 and the surface of the second pad 42 facing away from the passivation layer 60 are both higher than the surface of the passivation layer 60 facing away from the substrate 10. In this way, it is convenient to bond the first and second pads 41 and 42 with the external electrical devices correspondingly.
Optionally, the surface of the first pad 41 facing away from the passivation layer 60 and the surface of the second pad 42 facing away from the passivation layer 60 are located on the same plane, for example, polishing may be performed by chemical mechanical polishing. In this way, in the subsequent process of transferring a large amount of light emitting diode chips, the first bonding pad 41 and the second bonding pad 42 can be further ensured to have good surface contact effect and larger contact area with the metal layer of the backboard.
The embodiment of the application also provides a display device which comprises a driving circuit and a light-emitting unit connected with the driving circuit. Wherein the light emitting unit comprises the light emitting diode chip in some embodiments. The display device is, for example, an LED display panel or an LED back plate. The technical effects achieved by the led chip can be achieved by the display device, and the detailed description thereof is omitted.
It is to be understood that the application is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. A light emitting diode chip, comprising: at least one light emitting diode; the light emitting diode includes:
a first semiconductor layer, a light emitting layer, and a second semiconductor layer which are sequentially stacked; wherein a groove is arranged in the laminated structure of the second semiconductor layer and the light-emitting layer, and the groove exposes a part of the surface of the first semiconductor layer, which is close to the light-emitting layer;
the annular supporting structure is arranged in the groove and is spaced from the side wall of the groove;
a current spreading layer partially covering the second semiconductor layer;
a passivation layer covering exposed surfaces of the current spreading layer, the second semiconductor layer, the light emitting layer, and the first semiconductor layer, and exposed surfaces of the annular support structure outside the annular region and filling the space between the annular support structure and the sidewalls of the recess; the passivation layer has a first opening and a second opening; the first opening exposes the ring inner region, and the second opening exposes a part of the current expansion layer;
the first bonding pad is positioned on one side, away from the first semiconductor layer, of the annular supporting structure, is arranged in the first opening, and is connected with the first semiconductor layer through an annular region of the annular supporting structure;
and the second bonding pad is positioned at one side of the second semiconductor layer away from the light-emitting layer, is arranged in the second opening and is connected with the second semiconductor layer through the current expansion layer.
2. The light emitting diode chip of claim 1, wherein a surface of the passivation layer facing away from the substrate is planar.
3. The light emitting diode chip of claim 1, wherein portions of the passivation layer fill the spacers.
4. A light-emitting diode chip as claimed in any one of claims 1 to 3, wherein,
the radial dimensions of the ring inner region include: 1-3 mu m;
the radial dimensions of the groove include: 12-30 μm.
5. A light emitting diode chip as claimed in any one of claims 1 to 3, wherein the annular support structure comprises: a first annular support layer and a second annular support layer stacked in a direction away from the first semiconductor layer; wherein,
the thickness of the first annular supporting layer is the same as that of the light-emitting layer;
the thickness of the second annular supporting layer is the same as that of the second semiconductor layer.
6. The light emitting diode chip as recited in claim 5, wherein,
the material of the first annular supporting layer is the same as that of the light-emitting layer;
the second annular supporting layer is made of the same material as the second semiconductor layer.
7. A method of manufacturing a light emitting diode chip, comprising:
growing an epitaxial layer on a substrate; the epitaxial layer comprises a first semiconductor material layer, a luminescent material layer and a second semiconductor material layer which are sequentially stacked;
patterning the light emitting material layer and the second semiconductor material layer to form a light emitting layer, a second semiconductor layer, and a ring-shaped support structure; a groove is formed in the laminated structure of the second semiconductor layer and the light-emitting layer; the annular supporting structure is positioned in the groove and is spaced from the side wall of the groove;
patterning the first semiconductor material layer to form a first semiconductor layer;
forming a current spreading layer on the surface of the second semiconductor layer, which is away from the light emitting layer;
forming passivation layers on exposed surfaces of the first semiconductor layer, the light emitting layer, the second semiconductor layer and the current spreading layer, and exposed surfaces of the annular support structure outside the annular region; a portion of the passivation layer fills the space; the passivation layer has a first opening and a second opening; the first opening exposes the ring inner region, and the second opening exposes a part of the current expansion layer;
and forming a first bonding pad in the first opening, forming a second bonding pad in the second opening, wherein the second bonding pad is connected with the second semiconductor layer through the current expansion layer, and the first bonding pad penetrates through the ring-in area of the annular supporting structure to be connected with the first semiconductor layer.
8. The method of manufacturing a light emitting diode chip as claimed in claim 7, wherein the grooves are cylindrical grooves.
9. The method of manufacturing a light emitting diode chip as claimed in claim 8, wherein the annular support structure comprises a support structure having a circular ring or a square ring.
10. A display device, comprising: a driving circuit and a light emitting unit connected to the driving circuit; wherein the light emitting unit comprises the light emitting diode chip as claimed in any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111136695.2A CN114023855B (en) | 2021-09-27 | 2021-09-27 | Light-emitting diode chip, preparation method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111136695.2A CN114023855B (en) | 2021-09-27 | 2021-09-27 | Light-emitting diode chip, preparation method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114023855A CN114023855A (en) | 2022-02-08 |
| CN114023855B true CN114023855B (en) | 2023-11-21 |
Family
ID=80055129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111136695.2A Active CN114023855B (en) | 2021-09-27 | 2021-09-27 | Light-emitting diode chip, preparation method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114023855B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114883469B (en) * | 2022-07-07 | 2022-11-29 | 华灿光电（浙江）有限公司 | Light emitting diode chip for improving current conduction and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004056109A (en) * | 2002-05-27 | 2004-02-19 | Nichia Chem Ind Ltd | Nitride semiconductor light emitting element, light emitting element, element laminate, and light emitting device using them |
| CN109599465A (en) * | 2017-09-30 | 2019-04-09 | 展晶科技(深圳)有限公司 | LED chip construction |
| CN213878129U (en) * | 2020-12-30 | 2021-08-03 | 深圳市辰中科技有限公司 | Light emitting diode chip, backboard and display panel |
| CN113345986A (en) * | 2021-03-08 | 2021-09-03 | 聚灿光电科技（宿迁）有限公司 | Inverted Mini LED chip and manufacturing method thereof |
-
2021
- 2021-09-27 CN CN202111136695.2A patent/CN114023855B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004056109A (en) * | 2002-05-27 | 2004-02-19 | Nichia Chem Ind Ltd | Nitride semiconductor light emitting element, light emitting element, element laminate, and light emitting device using them |
| CN109599465A (en) * | 2017-09-30 | 2019-04-09 | 展晶科技(深圳)有限公司 | LED chip construction |
| CN213878129U (en) * | 2020-12-30 | 2021-08-03 | 深圳市辰中科技有限公司 | Light emitting diode chip, backboard and display panel |
| CN113345986A (en) * | 2021-03-08 | 2021-09-03 | 聚灿光电科技（宿迁）有限公司 | Inverted Mini LED chip and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114023855A (en) | 2022-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11784294B2 (en) | Vertical solid-state transducers having backside terminals and associated systems and methods | |
| US9287479B2 (en) | Luminous devices, packages and systems containing the same, and fabricating methods thereof | |
| CN103222073B (en) | Light-emitting diode chip for backlight unit, package structure for LED and to form above-mentioned method | |
| CN102130260B (en) | Luminous device and manufacturing method thereof | |
| KR20120134338A (en) | A light emitting device | |
| CN114023855B (en) | Light-emitting diode chip, preparation method thereof and display device | |
| CN111129062B (en) | LED display module, LED display screen and manufacturing method | |
| CN110429098B (en) | Display panel, manufacturing method thereof and display device | |
| TWI398967B (en) | Light-emitting diode chip, and manufacturing method therefor | |
| CN112968101B (en) | Micro LED chip and manufacturing method thereof | |
| TW200950132A (en) | Light emitting device package structure and fabricating method thereof | |
| CN215815879U (en) | LED chip structure, display module and electronic equipment | |
| CN215342604U (en) | LED chip structure and display module | |
| CN114725253A (en) | Micro-LED display substrate and manufacturing method thereof | |
| TWI499083B (en) | Method for packaging an led chip, led package and method for making a reflector of an led package | |
| KR100891800B1 (en) | Manufacturing method of light emitting diode array and light emitting diode array | |
| TW202042412A (en) | Planar surface mount micro-led for fluidic assembly and method for making same | |
| CN114023854B (en) | Light-emitting diode chip, preparation method thereof and display device | |
| CN114038952A (en) | Light emitting diode chip, preparation method thereof and display device | |
| CN113270441B (en) | LED chip structure, preparation method thereof, display module and electronic equipment | |
| CN117276304A (en) | Micro light-emitting diode display device and preparation method thereof | |
| CN117153955A (en) | Light-emitting diode and preparation method of electrode thereof | |
| CN117810241A (en) | Light-emitting unit package, manufacturing method thereof and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 402760 No.69, Wushan Road, Biquan street, Bishan District, Chongqing Applicant after: Chongqing Kangjia Optoelectronic Technology Co.,Ltd. Address before: 402760 No.69, Wushan Road, Biquan street, Bishan District, Chongqing Applicant before: Chongqing Kangjia Photoelectric Technology Research Institute Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |