CN114023771A

CN114023771A - Display substrate and display device

Info

Publication number: CN114023771A
Application number: CN202111290554.6A
Authority: CN
Inventors: 杨慧娟; 舒晓青; 廖茂颖; 魏立恒; 李灵通
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-11-02
Filing date: 2021-11-02
Publication date: 2022-02-08

Abstract

A display substrate, comprising: the pixel structure comprises a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of first data fan-out lines, a plurality of second data fan-out lines and a plurality of fan-out compensation lines. The substrate base plate comprises a display area and a frame area at least partially surrounding the display area. The frame area includes: a signal access area located at one side of the display area, and a fan-out area located between the display area and the signal access area. The fan-out region is divided into at least a first region, a second region, and a third region, the second region being located between the first region and the third region in the first direction. The plurality of first data fan-out lines are located in a first region and a third region of the fan-out region. The plurality of second data fan-out lines are positioned in a second area of the fan-out area. The plurality of fan-out compensation lines are located in the first region and the third region of the fan-out region. The at least one fan-out compensation line is connected in parallel with the at least one first data fan-out line.

Description

Display substrate and display device

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and more particularly, to a display substrate and a display device.

Background

With the development of Display technology, the variety of Display products is increasing, for example, Liquid Crystal Displays (LCDs), Organic Light-Emitting diodes (OLEDs), Plasma Display Panels (PDPs), Field Emission Displays (FEDs), and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a display substrate and a display device.

In one aspect, an embodiment of the present disclosure provides a display substrate, including: the pixel structure comprises a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of first data fan-out lines, a plurality of second data fan-out lines and a plurality of fan-out compensation lines. The substrate base plate comprises a display area and a frame area at least partially surrounding the display area. The bezel area includes: the display device comprises a signal access area positioned on one side of the display area and a fan-out area positioned between the display area and the signal access area. The fan-out region includes: a first region, a second region and a third region, the second region being located between the first region and the third region in a first direction. A plurality of sub-pixels and a plurality of data lines are located in the display region, the plurality of data lines extending in a second direction and electrically connected to the plurality of sub-pixels, the plurality of data lines configured to provide data signals to the plurality of sub-pixels. The second direction intersects the first direction. The plurality of first data fan-out lines are located in the first region and the third region of the fan-out region. The plurality of second data fan-out lines are located in a second area of the fan-out area. The plurality of first data fanout lines and the plurality of second data fanout lines are configured to connect the plurality of data lines. A plurality of fan-out compensation lines are located in the first and third regions of the fan-out region. At least one fan-out compensation line of the fan-out compensation lines is connected in parallel with at least one first data fan-out line of the first data fan-out lines.

In some exemplary embodiments, a difference between the resistance value of the first data fanout line and the resistance value of the second data fanout line after being connected in parallel with the fanout compensation line is less than or equal to 3 kilo-ohms.

In some exemplary embodiments, an orthogonal projection of the fan-out compensation line on the substrate base at least partially overlaps an orthogonal projection of the parallel-connected first data fan-out line on the substrate base.

In some exemplary embodiments, the fan-out compensation line is located at a side of the first data fan-out line away from the substrate base plate.

In some exemplary embodiments, the fan-out compensation line is connected in parallel with the first data fanout line through a plurality of connection electrodes, and the connection electrodes are located at sides of the fan-out compensation line and the first data fanout line, which are far away from the substrate.

In some exemplary embodiments, in the first region or the third region, a length of the fan-out compensation line adjacent to the second region is greater than a length of the fan-out compensation line away from the second region.

In some exemplary embodiments, the plurality of second data fanout lines are divided into two groups, the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines have a different layer structure, the orthographic projections of the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines on the substrate do not overlap, and the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines are arranged at intervals.

In some exemplary embodiments, the plurality of first data fanout lines are divided into two groups, the first group of the plurality of first data fanout lines and the second group of the plurality of first data fanout lines have a different layer structure, the orthographic projections of the first group of the plurality of first data fanout lines and the second group of the plurality of first data fanout lines on the substrate do not overlap, and the first group of the plurality of first data fanout lines and the second group of the plurality of first data fanout lines are arranged at intervals.

In some exemplary embodiments, the display area includes at least: the light-emitting device comprises a driving structure layer arranged on the substrate and a light-emitting element arranged on the driving structure layer; the light-emitting element is electrically connected with the driving structure layer. The driving structure layer includes: the first semiconductor layer, the first gate metal layer, the second semiconductor layer, the third gate metal layer and the source drain metal layer are sequentially arranged on the substrate. At least one of the plurality of first data fanout lines and the first gate metal layer or the second gate metal layer are in the same layer structure, at least one of the plurality of second data fanout lines and the first gate metal layer or the second gate metal layer are in the same layer structure, and at least one of the plurality of fan-out compensation lines and the third gate metal layer are in the same layer structure.

In some exemplary embodiments, a connection electrode connecting the fan-out compensation line and the first data fan-out line and the source-drain metal layer are in the same layer structure.

In another aspect, an embodiment of the present disclosure provides a display device including the display substrate as described above.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of one or more of the elements in the drawings are not to be considered as true scale, but rather are merely intended to illustrate the present disclosure.

Fig. 1 is a schematic view of a display substrate according to at least one embodiment of the present disclosure;

fig. 2 is a schematic diagram of a first frame region of a display substrate according to at least one embodiment of the present disclosure;

FIG. 3A is a schematic diagram of a first fan-out region of at least one embodiment of the present disclosure;

fig. 3B is a routing diagram of a first fan-out region according to at least one embodiment of the present disclosure;

FIG. 4 is an enlarged partial view of the area S1 in FIG. 3A;

FIG. 5 is an enlarged partial view of the area S2 in FIG. 3A;

FIG. 6 is a schematic layout of a plurality of fan-out compensation lines according to at least one embodiment of the present disclosure;

FIG. 7 is a schematic partial cross-sectional view taken along line B-B' of FIG. 4;

FIG. 8 is a schematic partial cross-sectional view taken along line Q-Q' of FIG. 4;

FIG. 9 is a schematic partial cross-sectional view taken along the direction R-R' in FIG. 4;

FIG. 10 is a schematic partial cross-sectional view taken along line P-P' of FIG. 5;

FIG. 11 is a schematic partial cross-sectional view taken along line A-A' of FIG. 2;

FIG. 12 is a schematic diagram showing resistance distribution curves before and after resistance compensation of a data fanout line of a display substrate;

fig. 13 is a schematic diagram of resistance distribution curves before and after resistance compensation is performed on the data fanout line of the display substrate according to at least one embodiment of the disclosure;

fig. 14 is another schematic view of a first frame region of a display substrate according to at least one embodiment of the present disclosure;

fig. 15 is a schematic view of a display device according to at least one embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content may be altered into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of one or more constituent elements, the thickness of layers, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of a plurality of components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present disclosure are provided to avoid confusion of the constituent elements, and are not limited in number. "plurality" in this disclosure means two or more than two.

In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode (a gate or a gate electrode terminal), a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other. In addition, the gate electrode may also be referred to as a control electrode.

In the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical action" is not particularly limited as long as it can transmit an electrical signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, another element having one or more functions, and the like.

In the present disclosure, "parallel" refers to a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and thus, may include a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" means a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus may include a state in which an angle is 85 ° or more and 95 ° or less.

In the present disclosure, "film" and "layer" may be interchanged with one another. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

At least one embodiment of the present disclosure provides a display substrate, including: the pixel structure comprises a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of first data fan-out lines, a plurality of second data fan-out lines and a plurality of fan-out compensation lines. The substrate base plate comprises a display area and a frame area at least partially surrounding the display area. The frame area includes: a signal access area located at one side of the display area, and a fan-out area located between the display area and the signal access area. The fan-out region is divided into at least a first region, a second region, and a third region, the second region being located between the first region and the third region in the first direction. The plurality of sub-pixels and the plurality of data lines are located in the display area. The data lines extend along the second direction and are electrically connected with the sub-pixels. The plurality of data lines are configured to supply data signals to the plurality of sub-pixels. The plurality of first data fan-out lines are positioned in the first area and the third area of the fan-out area, and the plurality of second data fan-out lines are positioned in the second area of the fan-out area. The plurality of first data fanout lines and the plurality of second data fanout lines are configured to connect the plurality of data lines. The plurality of fan-out compensation lines are located in the first region and the third region of the fan-out region. At least one fan-out compensation line of the plurality of fan-out compensation lines is connected in parallel with at least one first data fan-out line of the plurality of first data fan-out lines. The second direction intersects the first direction. For example, the second direction is perpendicular to the first direction. However, this embodiment is not limited to this.

According to the display substrate provided by the embodiment, the resistance values of the first data fan-out lines positioned in the first area and the third area of the fan-out area are reduced by using the fan-out compensation lines, so that the resistance value difference between the first data fan-out lines positioned in the first area and the third area and the second data fan-out lines positioned in the second area is reduced, and the display effect of the display substrate is improved.

In some exemplary embodiments, a difference between the resistance value of the first data fanout line and the resistance value of the second data fanout line after being connected in parallel with the fanout compensation line may be less than or equal to 3 kilo-ohms (K Ω). The display substrate provided by the present exemplary embodiment can improve the display effect of the display substrate by reducing the resistance value difference between the first data fanout line and the second data fanout line.

In some exemplary embodiments, an orthogonal projection of the fan-out compensation line on the substrate base at least partially overlaps an orthogonal projection of the first data fan-out line connected in parallel on the substrate base. For example, a line width of the fan-out compensation line and a line width of the first data fanout line may be substantially the same, and orthographic projections of the fan-out compensation line and the first data fanout line on the substrate may overlap. However, this embodiment is not limited to this.

In some exemplary embodiments, the fan-out compensation line is located at a side of the first data fan-out line away from the substrate. However, this embodiment is not limited to this. For example, the fan-out compensation line may be located at a side of the first data fan-out line close to the substrate.

In some exemplary embodiments, the fan-out compensation line is connected in parallel with the first data fan-out line through a plurality of connection electrodes. The connection electrode is positioned on one side of the fan-out compensation line and the first data fan-out line far away from the substrate. The orthographic projection of the connecting electrode on the substrate base plate is overlapped with the orthographic projection of the fan-out compensation line and the orthographic projection of the first data fan-out line on the substrate base plate. However, this embodiment is not limited to this. For example, the fan-out compensation line may be directly electrically connected to the first data fan-out line.

In some exemplary embodiments, in the first region or the third region, a length of the fan-out compensation line adjacent to the second region is greater than a length of the fan-out compensation line distant from the second region. In this example, by controlling the length of the fan-out compensation line connected in parallel to the first data fanout line, the resistance value variation of the first data fanout line may be adjusted, thereby controlling the resistance values of the plurality of adjacent first data fanout lines not to have a sudden change.

In some exemplary embodiments, the plurality of second data fanout lines are divided into two groups, the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines have a different layer structure, the orthographic projections of the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines on the substrate do not overlap, and the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines are arranged at intervals. In this example, the plurality of second data fanout lines are designed to be alternately arranged at two routing layers. However, this embodiment is not limited to this. In some examples, the plurality of second data fanout lines may be located on the same routing layer.

In some exemplary embodiments, the plurality of first data fanout lines are divided into two groups, the first group of the plurality of first data fanout lines and the second group of the plurality of first data fanout lines have a different layer structure, the orthographic projections of the first group of the plurality of first data fanout lines and the second group of the plurality of first data fanout lines on the substrate do not overlap, and the first group of the plurality of first data fanout lines and the second group of the plurality of first data fanout lines are arranged at intervals. In this example, the plurality of first data fanout lines are designed to be alternately arranged at two routing layers. However, this embodiment is not limited to this. In some examples, the plurality of first data fanout lines may be located on the same routing layer.

In some exemplary embodiments, the display area includes at least: the light emitting device comprises a driving structure layer arranged on a substrate, and a light emitting element arranged on the driving structure layer. The light-emitting element is electrically connected with the driving structure layer. The drive structure layer includes: the first semiconductor layer, the first gate metal layer, the second semiconductor layer, the third gate metal layer and the source drain metal layer are sequentially arranged on the substrate. At least one first data fanout line of the plurality of first data fanout lines and the first gate metal layer or the second gate metal layer are in the same layer structure, at least one second data fanout line of the plurality of second data fanout lines and the first gate metal layer or the second gate metal layer are in the same layer structure, and at least one fan-out compensation line of the plurality of fan-out compensation lines and the third gate metal layer are in the same layer structure. However, this embodiment is not limited to this. For example, the fan-out compensation line and the source and drain metal layers can be in the same layer structure.

In some exemplary embodiments, the display substrate of the present embodiment may be a Low Temperature Polycrystalline Oxide (LTPO) display substrate, or may be a Low Temperature Polycrystalline Poly-Silicon (LTPS) display substrate. However, this embodiment is not limited to this.

The display substrate of the present embodiment is exemplified below by some examples. In the following exemplary embodiments, the OLED display substrate is taken as an example of the display substrate. In the drawings, only a part of the data lines and the data fan-out lines or only the positions of the fan-out regions are illustrated, and the number of the data lines and the data fan-out lines is not limited.

Fig. 1 is a schematic view of a display substrate according to at least one embodiment of the present disclosure. As shown in fig. 1, the present exemplary embodiment provides a display substrate including: a display area 100 and a frame area located at the periphery of the display area 100. The frame area includes: a first frame region 200 located at one side of the display region 100, and a second frame region 300 located at the periphery of the display region 100 and far away from the first frame region 200. The first bezel region 200 and the second bezel region 300 are connected to surround the display region 100. In some examples, the first bezel region 200 may be a lower bezel of the display substrate, and the second bezel region 300 may include an upper bezel, a left bezel, and a right bezel of the display substrate. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 1, the display region 100 includes at least a plurality of sub-pixels 1001, a plurality of gate lines (not shown) extending in a first direction D1, and a plurality of Data lines (Data lines) 1002 extending in a second direction D2. The first direction D1 and the second direction D2 intersect, e.g., the first direction D1 is perpendicular to the second direction D2. Orthogonal projections of a plurality of grid lines and a plurality of data lines 1002 on the substrate are crossed to form a plurality of sub-pixel regions, and one sub-pixel 1001 is arranged in each sub-pixel region. The plurality of data lines 1002 are electrically connected to the plurality of sub-pixels 1001, and the plurality of data lines 1002 are configured to supply data signals to the plurality of sub-pixels 1001. A plurality of gate lines are electrically connected to the plurality of subpixels 1001, and the plurality of gate lines are configured to supply scan signals to the plurality of subpixels 1001.

In some exemplary embodiments, one pixel unit may include three sub-pixels, which are a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, one pixel unit may include four sub-pixels, which are a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

In some exemplary embodiments, the shape of the sub-pixel 1001 may be a rectangle, a diamond, a pentagon, or a hexagon. When one pixel unit comprises three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel mode, a vertical parallel mode or a delta-shaped mode; when a pixel unit comprises four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel manner, a vertical parallel manner or a square manner. However, this embodiment is not limited to this.

In some exemplary embodiments, the second bezel region 300 includes at least a gate driving circuit that supplies a scan signal to the plurality of sub-pixels 1001 of the display region 100, and a power line (e.g., a low voltage power line (VSS)) that transmits a voltage signal to the plurality of sub-pixels 1001. However, this embodiment is not limited to this.

Fig. 2 is a schematic view of a first frame region of a display substrate according to at least one embodiment of the disclosure. In some exemplary embodiments, as shown in fig. 2, the first bezel area 200 includes at least: the first fan-out area 201, the signal access area 208 and the bonding connection area 209 are sequentially arranged along a side away from the display area 100 in the second direction D2. In this example, the fan-out area within the first bezel area 200 may include: a first fan-out region 201. The first fan-out area 201 is located between the display area 100 and the signal access area 208. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 2, the first fan-out region 201 is provided with a plurality of data fan-out lines, a first power line, and a second power line. The plurality of data fan-out lines are configured to be electrically connected to the plurality of data lines of the display area 100 in a fan-out routing manner in a one-to-one correspondence. The first power line is configured to be connected to a high voltage power line (VDD) of the display area 100. The second power line is configured to be connected to a low voltage power line (VSS) of the second bezel region 300. The signal access region 208 includes a plurality of signal input pads configured to connect to a driver Integrated Circuit (IC). The driving integrated circuit may be electrically connected to the plurality of data fan-out lines of the first fan-out region 201 through a plurality of signal input pads, and configured to supply data signals to the plurality of data lines of the display region 100. The bonding connection region 209 includes a plurality of bonding pads configured to be bonded to an external Flexible Printed Circuit (FPC).

Fig. 3A is a schematic diagram of a first fan-out region according to at least one embodiment of the present disclosure. Fig. 3B is a routing diagram of a first fan-out region according to at least one embodiment of the disclosure. In some exemplary embodiments, as shown in fig. 3A and 3B, the first fan-out region 201 includes: a first region 201a, a second region 201b, and a third region 201 c. The second region 201b is located between the first region 201a and the third region 201c in the first direction D1, and the second region 201b is adjacent to both the first region 201a and the third region 201 c. The plurality of data fanout lines of the first fanout region 201 may include: a plurality of first data fanout lines positioned in the first and

third regions

201a and 201c, and a plurality of second data fanout lines positioned in the second region 201 b. The plurality of first data fanout lines and the plurality of second data fanout lines are electrically connected to the plurality of data lines of the display region 100, and are configured to provide data signals to the plurality of data lines. In some examples, as shown in fig. 3B, the length of the data fan-out line of the first fan-out region 201 is gradually shortened in a direction from both sides toward the middle region along the first direction D1. The present embodiment is not limited to the ranges of the first region 201a, the second region 201b, and the third region 201 c. In some examples, the respective ranges of the first, second, and third regions may be determined according to a resolution of the display substrate and an outer shape of the display substrate. In this example, since the first and second data fanout lines extend in a fan-out routing manner, it may be determined that the data fanout line belongs to the first area, the second area, or the third area according to a position where a routing portion of the data fanout line along the second direction D2 is located.

The first and second areas of the first fan-out area will be described as an example. For the related description of the third area, reference may be made to the description of the first area, and therefore, the description thereof is omitted.

Fig. 4 is a partially enlarged schematic view of the region S1 in fig. 3A. In some exemplary embodiments, as shown in fig. 4, the plurality of first data fanout lines of the first region 201a may be divided into two groups. The first group of the plurality of first data fanout lines (e.g., the first data fanout line 61a) and the second group of the plurality of first data fanout lines (e.g., the first data fanout line 61b) are in a different layer structure. For example, the first data fanout line 61b may be positioned at a side of the first data fanout line 61a away from the substrate. The orthographic projections of the first group of the plurality of first data fanout lines and the second group of the plurality of first data fanout lines on the substrate are not overlapped, and the first group of the plurality of first data fanout lines and the second group of the plurality of first data fanout lines are arranged at intervals. As shown in fig. 4, in the first region 201a, the first

data fanout lines

61a and 61b located at different routing layers are alternately arranged at intervals. However, this embodiment is not limited to this. For example, the plurality of first data fan-out lines of the first fan-out region may be of the same layer structure.

Fig. 5 is a partially enlarged schematic view of the region S2 in fig. 3A. In some exemplary embodiments, as shown in fig. 5, the plurality of second data fanout lines of the second region 201b may be divided into two groups. The first group of the plurality of second data fanout lines (e.g., the second data fanout line 62a) and the second group of the plurality of second data fanout lines (e.g., the second data fanout line 62b) are in a different layer structure. For example, the second data fanout line 62b may be positioned at a side of the first data fanout line 62a away from the substrate base. The orthographic projections of the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines on the substrate are not overlapped, and the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines are arranged at intervals. As shown in fig. 5, in the second region 201b, the second

data fanout lines

62a and 62b located at different routing layers are alternately arranged at intervals. However, this embodiment is not limited to this. For example, the plurality of second data fanout lines of the first fanout region may be of the same layer structure.

Fig. 6 is a schematic layout diagram of a plurality of fan-out compensation lines according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 6, the first and

third regions

201a and 201c of the first fan-out region are provided with a plurality of fan-out compensation lines 63. The second region 201b is not provided with the fan-out compensation line 63. The plurality of fan-out compensation lines 63 extend in the second direction D2 and are sequentially arranged in the first direction D1. In the first and

third regions

201a and 201c, the plurality of fan-out compensation lines 63 and the plurality of first data fan-out lines may be connected in parallel in a one-to-one correspondence. In this example, the second data fan-out line of the second region 201b of the first fan-out region is a single-layer routing, and the first data fan-out lines of the first region 201a and the third region 201c are connected in parallel with the fan-out compensation line 63, so that a double-layer routing can be realized. In this example, the first data fanout line may reduce a resistance value of the first data fanout line by being connected in parallel with the fanout compensation line, thereby reducing a resistance value difference between the first data fanout line and the second data fanout line.

In some exemplary embodiments, as shown in fig. 6, within the first region 201a, the length of the fan-out compensation line 63 adjacent to the second region 201b (i.e., the length along the second direction D2) may be less than the length of the fan-out compensation line 63 away from the second region 201 b. Within the third region 201c, the length of the fan-out compensation lines 63 adjacent to the second region 201b may be less than the length of the fan-out compensation lines 63 distal from the second region 201 b. The line widths (i.e., the lengths along the first direction D1) of the plurality of fan-out compensation lines 63 may be substantially the same. For example, in the first region 201a, the lengths of the fan-out compensation lines 63 may sequentially decrease from the left side to the right side along the first direction D1; within the third region 201c, the lengths of the fanout compensation lines 63 may sequentially increase from left to right along the first direction D1. In this example, by adjusting the length of the fan-out compensation line to which the first data fan-out lines are connected in parallel, it is ensured that the resistance value of the adjacent first data fan-out lines does not have a sudden change. Moreover, the length of the fan-out compensation line close to the second area is smaller than that of the fan-out compensation line far away from the second area, so that the difference of the resistance values of the second data fan-out line in the middle area and the first data fan-out lines in the two side edge areas can be reduced. However, this embodiment is not limited to this. In some examples, the length of the fan-out compensation line may be adjusted according to a resistance value required for the data fan-out line of the first fan-out region.

In the present disclosure, the length of the trace is a characteristic dimension along the extending direction of the trace, and the line width of the trace can be a characteristic dimension in a direction perpendicular to the extending direction of the trace.

Fig. 7 is a partial cross-sectional view taken along the direction B-B' in fig. 4. Fig. 8 is a partial cross-sectional view taken along the direction Q-Q' in fig. 4. Fig. 9 is a schematic partial cross-sectional view taken along the direction R-R' in fig. 4. Fig. 10 is a partial cross-sectional view taken along the direction P-P' in fig. 5.

In some exemplary embodiments, as shown in fig. 7 to 10, in a direction perpendicular to the display substrate, the first fan-out region 201 may include: a first routing layer, a second routing layer, a third routing layer and a fourth routing layer sequentially disposed on the substrate base plate 30. A first insulating layer 31 and a second insulating layer 32 are arranged between the first wiring layer and the substrate base plate 30, a third insulating layer 33 is arranged between the first wiring layer and the second wiring layer, a fourth insulating layer 34 and a fifth insulating layer 35 are arranged between the second wiring layer and the third wiring layer, and a sixth insulating layer 36 is arranged between the third wiring layer and the fourth wiring layer. In some examples, the first routing layer may include: a first group of the plurality of first data fanout lines 61a and a first group of the plurality of second data fanout lines 62 a. The second routing layer may include: a second group of the plurality of first data fanout lines 61b and a second group of the plurality of second data fanout lines 62 b. The third routing layer may include: a plurality of fan-out compensation lines 63. The fourth routing layer may include: a plurality of connection electrodes 64. In some examples, the first to sixth insulating layers 31 to 36 may all be inorganic insulating layers. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 4 and 8, the sixth insulating layer 36 has a first via K1 and a second via K2 opened thereon. The sixth insulating layer 36, the fifth insulating layer 35, the fourth insulating layer 34, and the third insulating layer 33 in the first via hole K1 are etched away, exposing the surface of the first wiring layer. The sixth insulating layer 36 in the second via hole K2 is etched away, exposing the surface of the third routing layer. The connection electrode 64 is located on the fourth wiring layer. One connection electrode 64 is electrically connected to the first data fan-out line 61a on the first wiring layer through the first via hole K1, and is also electrically connected to one fan-out compensation line 63 on the third wiring layer through the second via hole K2, thereby achieving electrical connection of one ends of the first data fan-out line 61a and the fan-out compensation line 63. The other end of the fan-out compensation line 63 may be electrically connected to the other end of the first data fanout line 61a in a similar manner, thereby achieving the parallel connection of the fan-out compensation line 63 and the first data fanout line 61 a. In some examples, within the first region 201a of the first fan-out region 201, the fan-out compensation line 63 may be electrically connected to the first data fan-out line 61a through the plurality of connection electrodes 64, thereby enabling the fan-out compensation line 63 to be connected in parallel to the first data fan-out line 61 a. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 4, there is an overlap of the orthographic projection of the fan-out compensation line 63 on the substrate and the orthographic projection of the first data fan-out line 61a on the substrate. For example, the line width of the fan-out compensation line 63 and the line width of the first data fan-out line 61a may be substantially the same. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 4 and 9, the sixth insulating layer 36 has a third via K3 and a fourth via K4 opened thereon. The sixth insulating layer 36, the fifth insulating layer 35 and the fourth insulating layer 34 in the third via hole K3 are etched away, exposing the surface of the second routing layer. The sixth insulating layer 36 in the fourth via hole K4 is etched away, exposing the surface of the third routing layer. The connection electrode 64 is located on the fourth wiring layer. One connection electrode 64 is electrically connected to the first data fan-out line 61b on the second routing layer through a third via hole K1, and is also electrically connected to one fan-out compensation line 63 on the third routing layer through a fourth via hole K4, thereby achieving electrical connection of the first data fan-out line 61b and one end of the fan-out compensation line 63. The other end of the fan-out compensation line 63 may be electrically connected to the other end of the first data fanout line 61b in a similar manner, thereby achieving the parallel connection of the fan-out compensation line 63 and the first data fanout line 61 b. There is an overlap between the orthographic projection of the fan-out compensation line 63 on the substrate base and the orthographic projection of the first data fan-out line 61b on the substrate base. For example, the line width of the fan-out compensation line 63 and the line width of the first data fan-out line 61b may be substantially the same. In some examples, within the first region 201a of the first fan-out region 201, the fan-out compensation line 63 may be electrically connected to the first data fan-out line 61b through a plurality of connection electrodes 64, thereby enabling the fan-out compensation line 63 to be connected in parallel with the first data fan-out line 61 b. However, this embodiment is not limited to this.

Fig. 11 is a partial cross-sectional view taken along a-a' of fig. 2. Fig. 11 illustrates only one light-emitting element in the display region 100 and one first-type transistor 401, one second-type transistor 402, and one storage capacitor 403 in one pixel circuit as an example. Also illustrated in fig. 11 are a first data fan-out line 61 and a second data fan-out line 62 of the first fan-out region 201. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 11, in a direction perpendicular to the display substrate, the display area 100 may include: the driving structure layer, the light emitting structure layer, and the encapsulation layer 52 are sequentially disposed on the substrate 30. The driving structure layer may include: the first semiconductor layer, the first gate metal layer, the second semiconductor layer, the third gate metal layer, and the source-drain metal layer are sequentially disposed on the substrate base plate 30. A first insulating layer 31 is arranged between the first semiconductor layer and the substrate base plate 30, a second insulating layer 32 is arranged between the first semiconductor layer and the first gate metal layer, a third insulating layer 33 is arranged between the first gate metal layer and the second gate metal layer, a fourth insulating layer 34 is arranged between the second gate metal layer and the second semiconductor layer, a fifth insulating layer 35 is arranged between the second semiconductor layer and the third gate metal layer, and a sixth insulating layer 36 is arranged between the third gate metal layer and the source drain metal layer. A seventh insulating layer 37 (or called a planarization layer) is disposed between the source-drain metal layer and the light emitting structure layer. The light emitting structure layer may include: a pixel defining layer 408, an anode layer, a cathode layer, and an organic light emitting layer sandwiched between the anode layer and the cathode layer. The light emitting structure layer includes a plurality of light emitting elements. For example, the at least one light emitting element includes an anode 405, a cathode 407, and an organic light emitting layer 406 interposed between the anode 405 and the cathode 407. The organic light emitting layer 406 may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer stacked, and is formed in the pixel opening of the display region 100 to connect the organic light emitting layer 406 and the anode 405. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 11, the first semiconductor layer includes at least: the active layer of the first type transistor 401. The material of the first semiconductor layer may be, for example, polysilicon. The first gate metal layer includes at least: a gate of the first type transistor 401 and a first electrode of the storage capacitor 403. The second gate metal layer includes at least: a second electrode of the storage capacitor 403. The second semiconductor layer includes at least: an active layer of a second type transistor 402. The material of the second semiconductor layer may include, for example, Indium Gallium Zinc Oxide (IGZO). The third gate metal layer includes at least: a gate of the second type transistor 402. The source drain metal layer at least comprises: a first and a second pole of a first type transistor 401 and a first and a second pole of a second type transistor 402. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 11, the first gate metal layer of the display area 100 and the first routing layer of the first fan-out area 201 may be of a same layer structure. The second gate metal layer of the display area 100 and the second routing layer of the first fan-out area 201 are in the same layer structure. The third gate metal layer of the display area 100 and the third routing layer of the first fan-out area 201 are in the same layer structure. The source-drain metal layer of the display area 100 and the fourth routing layer of the first fan-out area 201 are in the same layer structure. However, this embodiment is not limited to this.

In some exemplary embodiments, the side of the pixel defining layer 408 away from the substrate base plate 30 is also provided with an isolation pillar layer 51. The isolation pillar layer 51 may include a plurality of isolation pillars. In some examples, the seventh insulating layer 37, the pixel defining layer 408, and the isolation pillar layer 51 may employ an organic material such as polyimide, acryl, or polyethylene terephthalate.

In some exemplary embodiments, the first insulating layer 31 may also be referred to as a buffer layer, the second, third and fifth insulating

layers

32, 33 and 35 may also be referred to as a gate insulating layer, and the fourth and sixth insulating

layers

34 and 36 may also be referred to as an interlayer insulating layer. The first, second, third, fourth, fifth, and sixth insulating

layers

31, 32, 33, 34, 35, and 36 may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer 31 may be used to improve the water and oxygen resistance of the base substrate 30. The first to fourth routing layers, the first gate metal layer, the second gate metal layer, the third gate metal layer, and the source drain metal layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti. However, this embodiment is not limited to this.

In some example embodiments, the first-type transistor 401 may be a low temperature polysilicon thin film transistor, and the second-type transistor 402 may be an oxide thin film transistor. LTPS is adopted as an active layer of the low-temperature polycrystalline silicon thin film transistor, and Oxide semiconductor (Oxide) is adopted as an active layer of the Oxide thin film transistor. The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, the oxide thin film transistor has the advantages of low leakage current and the like, the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor are integrated on one display substrate to form the LTPO display substrate, the advantages of the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor can be utilized, low-frequency driving can be realized, the power consumption can be reduced, and the display quality can be improved. However, this embodiment is not limited to this. For example, the plurality of transistors of the pixel circuit in the display region may each be a low-temperature polysilicon thin film transistor, or may each be an oxide thin film transistor.

The structure of the display substrate of the present exemplary embodiment is merely an exemplary illustration. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs. For example, the fan-out compensation line may be located at the source-drain metal layer and directly electrically connected to the first data fan-out line. Alternatively, the second semiconductor layer of the display region may be positioned between the first gate metal layer and the second gate metal layer. However, this embodiment is not limited to this.

The preparation process of the exemplary embodiment can be realized by using existing mature preparation equipment, can be well compatible with the existing preparation process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost and high in yield.

Fig. 12 is a schematic diagram of resistance distribution curves before and after resistance compensation of a data fanout line of a display substrate. Fig. 13 is a schematic diagram of a resistance distribution curve before and after performing resistance compensation on the data fanout line of the display substrate according to at least one embodiment of the disclosure. In fig. 12 and 13, the abscissa indicates the order of a plurality of data fanout lines from the left edge to the right edge in the first direction D1 within the first bezel region 200 shown in fig. 1, and the ordinate indicates the resistance value in ohms.

A curve a in fig. 12 and 13 represents a resistance value before resistance compensation is performed on the plurality of data fanout lines from the left edge to the right edge in the first direction D1 along the first bezel region 200. As can be seen from the curve a, the resistance values of the data fanout lines at the left and right edges of the first frame region 200 along the first direction D1 are greatly different from the resistance value of the data fanout line at the middle region (for example, the resistance value difference is about 4 kohms to 10 kohms), which is likely to cause the display yellowing phenomenon at the left and right edges of the display region. In some implementations, to improve the display effect, the resistance of the data fanout line in the middle area of the first frame area 200 is increased to reduce the difference between the resistance of the data fanout line in the edge area and the resistance of the data fanout line in the middle area. Curve b in fig. 12 is a resistance value distribution obtained by increasing the resistance value of the data fanout line in the middle region. As shown in fig. 12, the resistance values of the data fanout lines in the middle area are all increased, which may increase the load of the data lines in the display area, thereby being disadvantageous to the display uniformity of low gray scale.

Curve c in fig. 13 is a distribution of the resistance of the data fanout line of the display substrate of the present embodiment. As shown in fig. 13, a resistance value difference between the first data fanout line positioned at the edge area of the first bezel area and the second data fanout line positioned at the middle area may be less than or equal to 3 kohms. In the exemplary embodiment, the resistance value of the data fanout line in the edge region is reduced by compensating the resistance value of the data fanout line in the edge region, so that the difference between the resistance values of the data fanout line in the edge region and the data fanout line in the middle region is reduced, and thus, not only can the problem of yellowing of the display on the left and right edges of the display region be improved, but also the load of the data line in the display region can be reduced, and the display uniformity of low gray scale can be improved. In addition, as can be seen from the curve c of fig. 13, the resistances of the plurality of data fanout lines in the first frame region can be in a substantially smooth transition, so as to avoid a large abrupt change of the resistance.

Fig. 14 is another schematic view of a first frame region according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 14, the first bezel area 200 may include: the first fan-out region 201, the bending region 202, the second fan-out region 203, the anti-static region 204, the test circuit region 205, the data selection circuit region 206, the third fan-out region 207, the signal access region 208 and the bonding connection region 209 are sequentially arranged along a side away from the display region 100 in the second direction D2. In this example, the fan-out area within the first bezel area 200 may include: a first fan-out region 201, a second fan-out region 203, and a third fan-out region 207. The first fan-out region 201 is located between the display region 100 and the bending region 202, the second fan-out region 203 is located between the bending region 202 and the anti-static region 204, and the third fan-out region 207 is located between the data selection circuit region 206 and the signal access region 208. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 14, a plurality of data fan-out lines may be disposed in each of the first fan-out region 201, the second fan-out region 203, and the third fan-out region 207 of the first bezel region 200 to enable transmission of a data signal or a test data signal. The plurality of data fan-out lines of the first fan-out region 201 are configured to connect the plurality of data lines of the display region 100 in a fan-out routing manner. The bending region 202 is configured to bend a portion of the first bezel region 200 to the back of the display region 100. The bending region 202 is at least provided with a plurality of data connection lines and a plurality of power connection lines. The plurality of data link lines are configured to be connected to the plurality of data fan-out lines of the first fan-out region 201 in a one-to-one correspondence. The plurality of power connection lines may include a first power connection line (e.g., a high voltage power connection line) and a second power connection line (e.g., a low voltage power connection line); the first power connection line is configured to be connected to a first power line of the first fan-out area 201, and the second power connection line is configured to be connected to a second power line of the first fan-out area 201. In some examples, the plurality of data connection lines and the plurality of power connection lines may be disposed at the same layer. The power connection lines may be arranged in the middle of the plurality of data connection lines. The plurality of data fan-out lines of the second fan-out region 203 are configured to connect the plurality of data connection lines of the bending region 202 in a fan-out routing manner, and the plurality of data fan-out lines are connected with the plurality of data connection lines of the bending region 202 in a one-to-one correspondence manner.

In some exemplary embodiments, as shown in fig. 14, the static electricity prevention region 204 includes a static electricity prevention circuit. The test circuit area 205 includes test circuits. The data selection circuit region 206 includes a data selection circuit. The plurality of data fan-out lines of the second fan-out region 203 may be electrically connected to the static electricity prevention circuit, the test circuit, and the data selection circuit in sequence to receive a data signal or a test data signal. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 14, the signal access region 208 includes a plurality of signal input pads configured to connect to a driving integrated circuit. The driving integrated circuit may be connected to the plurality of data fanout lines of the third fanout region 207 through a plurality of signal input pads, and configured to supply data signals to the plurality of data lines of the display region 100. The bonding connection region 209 includes a plurality of bonding pads configured to be bonded with an external FPC.

In some exemplary embodiments, in the first direction D1, the plurality of data fanout lines located at both left and right side edge regions of the first frame region 200 may be alternately arranged at the first routing layer and the second routing layer, and the plurality of data fanout lines located at the middle region of the first frame region 200 may be alternately arranged at the first routing layer and the second routing layer. The first bezel region 200 may be provided with fan-out compensation lines in edge regions on left and right sides of the first direction D1, and the fan-out compensation lines may be connected in parallel with the data fan-out lines in at least one of the first fan-out region, the second fan-out region, and the third fan-out region, thereby reducing a difference in resistance values of the data fan-out lines in the edge regions on the left and right sides and the data fan-out line in the middle region. For example, the fan-out compensation lines may be disposed at both side edge regions of the first fan-out region in the first direction D1 and connected in parallel with the data fan-out lines of the region; alternatively, the fan-out compensation lines may be disposed at both side edge regions of the second fan-out region in the first direction D1, and connected in parallel with the data fan-out lines of the region; alternatively, the fan-out compensation lines may be disposed at both side edge regions of the first and second fan-out regions in the first direction D1 and connected in parallel with the data fan-out lines of the region. However, this embodiment is not limited to this.

In some exemplary embodiments, in edge regions on the left and right sides of the first bezel region 200 in the first direction D1, the length of the fan-out compensation line adjacent to the middle region may be smaller than the length of the fan-out compensation line far from the middle region. For example, in the edge regions on the left and right sides of the first bezel region 200 in the first direction D1, the fan-out compensation lines may increase in a direction away from the middle region. However, this embodiment is not limited to this. In some examples, the first fan-out region is in edge regions on left and right sides of the first direction, and the fan-out compensation lines may decrease in a direction away from the middle region.

In addition, the position relationship and the connection manner of the fan-out compensation line and the data fan-out line can refer to the description of the foregoing embodiments, and therefore, the description thereof is omitted.

The structure (or method) shown in this embodiment mode can be combined with the structure (or method) shown in other embodiment modes as appropriate.

Fig. 15 is a schematic view of a display device according to at least one embodiment of the present disclosure. As shown in fig. 15, the present embodiment provides a display device 91 including: a display substrate 910. The display substrate 910 is the display substrate provided in the foregoing embodiments. The display substrate 910 may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 may be: the OLED display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and other products or components with display functions. However, this embodiment is not limited to this.

The drawings in this disclosure relate only to the structures to which this disclosure relates and other structures may be referred to in the general design. Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

It will be understood by those skilled in the art that various modifications and equivalent arrangements may be made in the present disclosure without departing from the spirit and scope of the present disclosure, and the scope of the appended claims should be accorded the full scope of the disclosure.

Claims

1. A display substrate, comprising:

a substrate comprising a display area and a bezel area at least partially surrounding the display area, the bezel area comprising: the signal access area is positioned on one side of the display area, and the fan-out area is positioned between the display area and the signal access area; the fan-out region is divided into at least a first region, a second region and a third region, the second region being located between the first region and the third region in a first direction;

a plurality of sub-pixels and a plurality of data lines positioned in the display region, the plurality of data lines extending in a second direction and electrically connected to the plurality of sub-pixels, the plurality of data lines configured to supply data signals to the plurality of sub-pixels; the second direction intersects the first direction;

a plurality of first data fanout lines positioned in the first and third areas of the fanout area;

a plurality of second data fan-out lines located in a second region of the fan-out region; the plurality of first data fanout lines and the plurality of second data fanout lines are configured to connect the plurality of data lines;

and the fan-out compensation lines are positioned in the first area and the third area of the fan-out area, and at least one fan-out compensation line in the fan-out compensation lines is connected with at least one first data fan-out line in the first data fan-out lines in parallel.

2. The display substrate of claim 1, wherein a difference between a resistance value of the first data fanout line and a resistance value of the second data fanout line after being connected in parallel with the fanout compensation line is less than or equal to 3 kilo-ohms.

3. The display substrate of claim 1, wherein an orthographic projection of the fan-out compensation line on the substrate at least partially overlaps an orthographic projection of the parallel-connected first data fan-out line on the substrate.

4. The display substrate of claim 1, wherein the fan-out compensation line is located on a side of the first data fan-out line away from the substrate.

5. The display substrate according to claim 1, wherein the fan-out compensation line is connected in parallel with the first data fanout line through a plurality of connection electrodes, the connection electrodes being located on sides of the fan-out compensation line and the first data fanout line away from the substrate.

6. The display substrate of claim 1, wherein in the first region or the third region, a length of the fan-out compensation line adjacent to the second region is greater than a length of the fan-out compensation line away from the second region.

7. The display substrate according to any one of claims 1 to 6, wherein the plurality of second data fanout lines are divided into two groups, the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines are in a different layer structure, orthogonal projections of the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines on the substrate do not overlap, and the first group of the plurality of second data fanout lines and the second group of the plurality of second data fanout lines are arranged at intervals.

8. The display substrate according to any one of claims 1 to 6, wherein the plurality of first data fanout lines are divided into two groups, the first plurality of first data fanout lines of the first group and the second plurality of first data fanout lines of the second group are in a different layer structure, orthogonal projections of the first plurality of first data fanout lines of the first group and the second plurality of first data fanout lines of the second group on the substrate do not overlap, and the first plurality of first data fanout lines of the first group and the second plurality of first data fanout lines of the second group are arranged at intervals.

9. The display substrate according to any one of claims 1 to 6, wherein the display region includes at least: the light-emitting device comprises a driving structure layer arranged on the substrate and a light-emitting element arranged on the driving structure layer; the light-emitting element is electrically connected with the driving structure layer;

the driving structure layer includes: the first semiconductor layer, the first gate metal layer, the second semiconductor layer, the third gate metal layer and the source drain metal layer are sequentially arranged on the substrate;

at least one of the plurality of first data fanout lines and the first gate metal layer or the second gate metal layer are in the same layer structure, at least one of the plurality of second data fanout lines and the first gate metal layer or the second gate metal layer are in the same layer structure, and at least one of the plurality of fan-out compensation lines and the third gate metal layer are in the same layer structure.

10. The display substrate of claim 9, wherein a connection electrode connecting the fan-out compensation line and the first data fan-out line and the source-drain metal layer are in a same layer structure.

11. A display device comprising the display substrate according to any one of claims 1 to 10.