CN114023651A - Preparation method of NMOS (N-channel metal oxide semiconductor) transistor - Google Patents
Preparation method of NMOS (N-channel metal oxide semiconductor) transistor Download PDFInfo
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- CN114023651A CN114023651A CN202111226236.3A CN202111226236A CN114023651A CN 114023651 A CN114023651 A CN 114023651A CN 202111226236 A CN202111226236 A CN 202111226236A CN 114023651 A CN114023651 A CN 114023651A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title description 6
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 77
- 230000008569 process Effects 0.000 claims abstract description 51
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 12
- -1 germanium ions Chemical class 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 77
- 239000011241 protective layer Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 8
- 230000006872 improvement Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a preparation method of an NMOS transistor, which comprises the following steps: providing a substrate with a shallow trench isolation structure and a P-type well region, wherein a grid structure and a first side wall are formed on the substrate; implanting germanium ions into the P-type well regions on two sides of the first side wall to form a silicon germanium region; forming a buffer layer; forming a stress layer; performing an annealing process to create stress memorization in the channel region; and removing the stress layer and the buffer layer and forming a second side wall. According to the method, before the second side wall is formed, the buffer layer is formed, the stress layer is formed, and the annealing process is carried out (the three steps are the SMT process), so that stress memory is generated in the channel region, the distance from the stress layer to the channel region can be reduced, the channel region generates more stress memory, the stress improvement effect of the SMT process on the NMOS transistor is enhanced, the carrier mobility of the NMOS transistor is accelerated, and the speed of an NMOS device is improved.
Description
Technical Field
The application relates to the technical field of CMOS devices, in particular to a preparation method of an NMOS transistor.
Background
As the feature size of CMOS integrated circuit process technology is continuously reduced, the short channel effect is continuously enhanced. At present, by increasing the doping concentration of a device channel and reducing the thickness of a gate oxide layer, a depletion layer between a source and a drain and a substrate can be reduced and the gate control capability can be improved, so that the short channel effect is improved. However, the highly doped channel can increase coulomb scattering, and the enhancement of the gate control capability can form a strong electric field to enhance interface scattering, thereby causing the reduction of carrier mobility and finally reducing the speed of the device. Many studies have proposed using strained silicon technology to improve the carrier mobility of the device, compensate for coulomb scattering caused by high doping and interface scattering caused by strong electric field, and thus increase the speed of the device.
There are two types of strained silicon technologies currently used for NMOS devices, the first is: the method comprises the following steps that (1) a source and drain are embedded into a SiC strain process, but the process has certain difficulty, firstly, the selectivity of the SiC strain material epitaxial growth process is poor, and the SiC strain material epitaxial growth process can grow on non-single crystal regions such as oxide and the like while the bottom wall of a source and drain groove grows, such as the side wall of the source and drain groove and a Shallow Trench Isolation (STI); in addition, the thermal stability of the SiC strained material is poor at high temperature thermal annealing, and at temperatures above 900 ℃, part of the C atoms in the SiC strained material will leave the substitutional lattice and the stress is lost. The second method is as follows: although the SiGe process and the SMT process for increasing the speed of PMOS devices are mature at present, the effect of increasing the speed of NMOS devices is not very good, so a new method for manufacturing NMOS transistors is needed to optimize and improve the existing SMT process.
Disclosure of Invention
The application provides a preparation method of an NMOS transistor, which can solve the problem that the speed of an NMOS device cannot be improved by the existing SMT process.
In one aspect, an embodiment of the present application provides a method for manufacturing an NMOS transistor, including:
providing a substrate, wherein a plurality of shallow trench isolation structures and a P-type well region located between the shallow trench isolation structures are formed in the substrate, and a gate structure and a first side wall located on the side of the gate structure are formed on the substrate;
implanting germanium ions into the P-type well regions on two sides of the first side wall by taking the first side wall as a mask to form a silicon germanium region;
forming a buffer layer, wherein the buffer layer covers the gate structure, the first side wall, the silicon germanium region and the shallow trench isolation structure;
forming a stress layer, wherein the stress layer covers the buffer layer;
performing an annealing process to generate stress memorization in the silicon germanium region and a part of the P-type well region;
removing the stress layer and the buffer layer; and the number of the first and second groups,
and forming a second side wall, wherein the second side wall is positioned on the side of the first side wall.
Optionally, in the preparation method of the NMOS transistor, after the second sidewall is formed, the preparation method of the NMOS transistor further includes:
and forming a protective layer, wherein the protective layer covers the silicon germanium area and the shallow trench isolation structure on the side of the second side wall.
Optionally, in the preparation method of the NMOS transistor, after the protective layer is formed, the preparation method of the NMOS transistor further includes:
and implanting N-type conductive ions into the silicon germanium region under the protective layer by taking the second side wall as a mask to form a shallow doped drain structure.
Optionally, in the preparation method of the NMOS transistor, during the process of implanting germanium ions into the P-type well regions on both sides of the first sidewall to form a silicon germanium region, a dose of the germanium ions is 1E15atoms/cm3～1E16 atoms/cm3The implantation energy is 25KeV to 45 KeV.
Optionally, in the preparation method of the NMOS transistor, the annealing process is a spike annealing process, the process temperature is 800 to 1200 ℃, and the operation time is 60 to 5400 s.
Optionally, in the preparation method of the NMOS transistor, the material of the stress layer is silicon nitride.
Optionally, in the preparation method of the NMOS transistor, the thickness of the stress layer is 30nm to 70 nm.
Optionally, in the preparation method of the NMOS transistor, the buffer layer is made of silicon oxide.
Optionally, in the preparation method of the NMOS transistor, the thickness of the buffer layer is 10nm to 25 nm.
Optionally, in the preparation method of the NMOS transistor, the stress layer and the buffer layer are removed by using a wet cleaning process.
The technical scheme at least comprises the following advantages:
according to the method, before the buffer layer is formed, germanium ion implantation technology is carried out on the P-type well regions on two sides of the first side wall to obtain the silicon germanium regions, so that the surfaces of the P-type well regions can be partially amorphized, and dislocation is generated in crystal lattices, so that the tensile stress of the surface of an NMOS channel region (mainly comprising the P-type well regions and the silicon germanium regions) is improved.
Furthermore, before the second side wall is formed, a buffer layer is formed, a stress layer is formed, and an annealing process (the three steps are an SMT process) is performed to generate stress memory in the channel region, so that the distance from the stress layer to the channel region can be reduced, the channel region generates more stress memory, the stress improvement effect of the SMT process on the NMOS transistor is enhanced, the carrier mobility of the NMOS transistor is accelerated, and the speed of the NMOS device is improved.
In addition, the protective layer is formed after the second side wall is formed, so that the stress memory of the channel region can be effectively reserved, the stress lifting effect of the NMOS transistor is further enhanced, and the speed of the NMOS device is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for fabricating an NMOS transistor according to an embodiment of the invention;
FIGS. 2-8 are schematic views of semiconductor structures in various process steps for fabricating an NMOS transistor according to embodiments of the present invention;
wherein the reference numerals are as follows:
100-substrate, 101-P type well region, 102-silicon germanium region, 110-shallow trench isolation structure, 120-gate structure, 130-first side wall, 140-buffer layer, 150-stress layer, 160-second side wall and 170-protective layer.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present application provides a method for manufacturing an NMOS transistor, please refer to fig. 1, where fig. 1 is a flowchart of a method for manufacturing an NMOS transistor according to an embodiment of the present invention, and the method for manufacturing an NMOS transistor includes:
s10: providing a substrate, wherein a plurality of shallow trench isolation structures and a P-type well region located between the shallow trench isolation structures are formed in the substrate, and a gate structure and a first side wall located on the side of the gate structure are formed on the substrate;
s20: implanting germanium ions into the P-type well regions on two sides of the first side wall by taking the first side wall as a mask to form a silicon germanium region;
s30: forming a buffer layer, wherein the buffer layer covers the gate structure, the first side wall, the silicon germanium region and the shallow trench isolation structure;
s40: forming a stress layer, wherein the stress layer covers the buffer layer;
s50: performing an annealing process to generate stress memorization in the silicon germanium region and a part of the P-type well region;
s60: removing the stress layer and the buffer layer;
s70: and forming a second side wall, wherein the second side wall is positioned on the side of the first side wall.
Specifically, referring to fig. 2 to 8, fig. 2 to 8 are schematic views of semiconductor structures in the process steps of manufacturing an NMOS transistor according to the embodiment of the present invention.
First, as shown in fig. 2, a substrate 100 is provided, a plurality of shallow trench isolation structures 110 and a P-type well region 101 located between the shallow trench isolation structures 110 are formed in the substrate 100, and a gate structure 120 and a first sidewall 130 located at a side of the gate structure 120 are formed on the substrate 100. Specifically, the substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, the substrate 100 may also be gallium arsenide, a silicon gallium compound, and the like, and the substrate 100 may also have a silicon-on-insulator or silicon-on-silicon epitaxial layer structure; the substrate 100 may also be other semiconductor materials, which are not listed here. The gate structure 120 may include: gate oxide, polysilicon gate, etc. The present embodiment does not limit the specific structure (layer) of the gate structure 120, and may be the gate structure 120 commonly used in the NMOS device technology. In this embodiment, a silicon nitride film layer covering the gate structure 120 and the surface of the substrate 100 may be formed first, then the silicon nitride film layer on the top of the gate structure 120 and the surface of the substrate 100 is removed by photolithography and etching processes, and the silicon nitride film layer on the side of the gate structure 120 is retained to obtain the first sidewall 130.
Then, as shown in fig. 3, germanium ions are implanted into the P-well 101 on both sides of the first sidewall 130 using the first sidewall 130 as a mask to form a silicon germanium region 102. Specifically, in the germanium ion implantation process, the dosage of germanium ions can be 1E15atoms/cm3～1E16 atoms/cm3The implantation energy may be 25KeV to 45KeV, the angle may be 10 to 30 °, and the present embodiment does not limit the specific process parameters of the germanium ion implantation process, and the process parameters may be determined according to the specific process conditions. By performing germanium ion implantation process on the P-type well region 101 in the substrate 100 on both sides of the first sidewall 130 before forming the buffer layer 140, the surface of the P-type well region 101 can be partially amorphized, and dislocation is generated in crystal lattices, so that the tensile stress on the surface of an NMOS device channel region (mainly comprising the silicon germanium region 102 and the P-type well region 101) is improved, and the carrier mobility of an NMOS device is improved.
Next, as shown in fig. 4, a buffer layer 140 is formed, wherein the buffer layer 140 covers the gate structure 120, the first sidewall 130, the sige region 101, and the shallow trench isolation structure 110. Specifically, the buffer layer 140 may be formed by a common process such as Chemical Vapor Deposition (CVD), and the buffer layer 140 may be made of silicon oxide. The thickness of the buffer layer 140 is 10nm to 25 nm.
Further, as shown in fig. 5, a stress layer 150 is formed, and the stress layer 150 covers the buffer layer 140. Specifically, the stress layer 150 may be formed by a common process such as Chemical Vapor Deposition (CVD), and the material of the stress layer 150 may be silicon nitride. The stress layer 150 has a thickness of 30nm to 70 nm.
Further, an annealing process is performed on the semiconductor structure formed in the above process steps to generate a stress memorization in the silicon germanium region 102 and a portion of the P-type well region 101 (channel region of NMOS transistor). Specifically, the annealing process can be a spike annealing process, the process temperature is 800-1200 ℃, and the operation time is 60-5400 s. Through the annealing process, the stress is memorized, so that the channel region still retains the stress after the stress layer 150 and the buffer layer 140 are subsequently removed.
Next, as shown in fig. 6, the stress layer 150 and the buffer layer 140 are removed. Specifically, in this embodiment, a wet cleaning process may be adopted to remove the stress layer 150 and the buffer layer 140, a wet cleaning reagent may be phosphoric acid, and the stress layer 150 and the buffer layer 140 are removed at one time by the wet cleaning process, so that surface defects of the gate structure 120 and the first sidewall 130 are eliminated, no impurity is left, and reliability of the device is improved.
Finally, as shown in fig. 7, a second sidewall 160 is formed, where the second sidewall 160 is located at the first sidewall 130 side. Specifically, the material of the second sidewall spacer 160 may include silicon oxide and silicon nitride stacked in sequence. In this embodiment, silicon oxide and silicon nitride covering the gate structure 120, the first sidewall 130 and the surface of the substrate 100 may be formed first, then the silicon oxide and the silicon nitride on the top of the gate structure 120 and the surface of the substrate 100 are removed by photolithography and etching processes, and the stacked silicon oxide and silicon nitride on the side surface of the gate structure 120 (on the first sidewall 130) are retained to obtain the second sidewall 160.
In this embodiment, before the second side walls 160 are formed, the buffer layer 140 is formed, the stress layer 150 is formed, and an annealing process (the three steps are an SMT process) is performed to generate stress memory in the channel region, and the distance from the stress layer 150 to the channel region (the silicon germanium region 102 and the P-type well region 101) can be reduced, so that the channel region generates more stress memory, the stress improvement effect of the SMT process on the NMOS transistor is enhanced, the carrier mobility of the NMOS transistor is increased, and the speed of the NMOS device is increased.
Preferably, as shown in fig. 8, after forming the second sidewall spacers 160, the method for manufacturing the NMOS transistor may further include: forming a protection layer 170, wherein the protection layer 170 covers the silicon germanium region 102 and the shallow trench isolation structure 110 in the substrate 100 on the second sidewall 160 side. Specifically, the protection layer 170 may be a silicon layer or a self-aligned silicide layer, and the protection layer 170 may be formed by a chemical vapor deposition (cvd) process or a Physical Vapor Deposition (PVD) process. The thickness of the protective layer 170 may be 20nm to 100 nm. According to the application, after the second side wall 160 is formed, the protective layer 170 is formed on the silicon germanium region 102 and the shallow trench isolation structure 110, so that stress memory of a channel region can be effectively reserved, the stress lifting effect of an NMOS transistor is further enhanced, and the speed of an NMOS device is further improved.
Preferably, after the forming the protection layer 170, the method for manufacturing the NMOS transistor of the present embodiment further includes: and implanting N-type conductive ions into the sige region 102 under the protection layer 170 by using the second sidewall 160 as a mask to form a shallow doped drain structure (not shown).
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A preparation method of an NMOS transistor is characterized by comprising the following steps:
providing a substrate, wherein a plurality of shallow trench isolation structures and a P-type well region located between the shallow trench isolation structures are formed in the substrate, and a gate structure and a first side wall located on the side of the gate structure are formed on the substrate;
implanting germanium ions into the P-type well regions on two sides of the first side wall by taking the first side wall as a mask to form a silicon germanium region;
forming a buffer layer, wherein the buffer layer covers the gate structure, the first side wall, the silicon germanium region and the shallow trench isolation structure;
forming a stress layer, wherein the stress layer covers the buffer layer;
performing an annealing process to generate stress memorization in the silicon germanium region and a part of the P-type well region;
removing the stress layer and the buffer layer; and the number of the first and second groups,
and forming a second side wall, wherein the second side wall is positioned on the side of the first side wall.
2. The method of claim 1, wherein after forming the second sidewall, the method further comprises:
and forming a protective layer, wherein the protective layer covers the silicon germanium area and the shallow trench isolation structure on the side of the second side wall.
3. The method of claim 2, wherein after the forming the protective layer, the method further comprises:
and implanting N-type conductive ions into the silicon germanium region under the protective layer by taking the second side wall as a mask to form a shallow doped drain structure.
4. The method of claim 1, wherein the dosage of Ge ions is 1E15atoms/cm during the process of implanting Ge ions into the P-well regions on both sides of the first sidewall to form SiGe regions3～1E16 atoms/cm3The implantation energy is 25KeV to 45 KeV.
5. The method of claim 1, wherein the annealing process is a spike annealing process, the process temperature is 800 ℃ to 1200 ℃, and the operation time is 60s to 5400 s.
6. The method of claim 1, wherein the stress layer is made of silicon nitride.
7. The method of claim 1, wherein the stress layer has a thickness of 30nm to 70 nm.
8. The method of claim 1, wherein the buffer layer is made of silicon oxide.
9. The method of claim 1, wherein the buffer layer has a thickness of 10nm to 25 nm.
10. The method of claim 1, wherein the stress layer and the buffer layer are removed by a wet cleaning process.
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| TW201112332A (en) * | 2009-09-28 | 2011-04-01 | United Microelectronics Corp | Method for fabricating a semiconductor device |
| US20120034749A1 (en) * | 2010-08-06 | 2012-02-09 | Samsung Electronics Co., Ltd. | Method for manufacturing a strained semiconductor device |
| US20130023103A1 (en) * | 2011-07-19 | 2013-01-24 | United Microelectronics Corp. | Method for fabricating semiconductor device by using stress memorization technique |
| CN103489781A (en) * | 2012-06-13 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device by utilizing stress memory technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
| TW201112332A (en) * | 2009-09-28 | 2011-04-01 | United Microelectronics Corp | Method for fabricating a semiconductor device |
| US20120034749A1 (en) * | 2010-08-06 | 2012-02-09 | Samsung Electronics Co., Ltd. | Method for manufacturing a strained semiconductor device |
| US20130023103A1 (en) * | 2011-07-19 | 2013-01-24 | United Microelectronics Corp. | Method for fabricating semiconductor device by using stress memorization technique |
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