CN114023236B

CN114023236B - Gate driving device and display panel

Info

Publication number: CN114023236B
Application number: CN202111331413.4A
Authority: CN
Inventors: 罗如君; 黄震铄
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2021-04-21
Filing date: 2021-11-11
Publication date: 2024-04-05
Anticipated expiration: 2041-11-11
Also published as: TW202242826A; TWI774330B; CN114023236A

Abstract

A gate driving device and a display panel are provided, wherein the gate driving device comprises a substrate and a shift register. The N-th shift register includes a pull-up unit. The pull-up unit is provided with a control end for receiving a control signal, and provides a clock signal to the output end according to the control signal so as to generate an N-level grid driving signal. The pull-up unit comprises a first transistor and a second transistor. The first transistors are located at the outermost sides of the pull-up unit, and each first transistor has a length L1 along the column direction. The second transistors are surrounded by the first transistors, each second transistor has a length L2, n×l1+ (n-1) ×2-x 1) =ml2+ (m-1) x2 in the column direction, each first transistor has a pitch x1 in the column direction with one of its neighboring second transistors, and each second transistor has a pitch x2, x2> (x 1-x 2) ×1.3 in the column direction between them.

Description

Gate driving device and display panel

Technical Field

The invention relates to a gate driving device and a display panel.

Background

In recent years, display panels with narrow frames are widely used in various devices for the purpose of maximizing the screen size. A gate driving circuit technology (Gate driver on Array, GOA) has been developed, which is a technology of manufacturing a gate driving circuit of a display panel in a peripheral region of the display panel instead of an external driving chip. However, when a large-sized display panel is operated under high voltage and high current conditions, self-heating effect (self-heating effect) is easily generated in the element of the gate driving circuit, resulting in degradation of the element. Therefore, a method for solving the above problems is needed.

Disclosure of Invention

The invention provides a gate driving device with improved reliability.

The invention relates to a gate driving device, which comprises a glass substrate and a plurality of shift registers. The shift register is formed on the glass substrate, each stage is coupled in series, and generates a plurality of gate driving signals respectively, and the shift register of the Nth stage comprises a pull-up unit. The pull-up unit is provided with a control end for receiving a control signal, and provides a clock signal to the output end according to the control signal so as to generate an N-stage grid driving signal, and comprises a plurality of first transistors and a plurality of second transistors. The first transistors are located at the outermost sides of the pull-up unit, and each first transistor has a length L1 along the column direction. The second transistors are surrounded by the first transistors, wherein each second transistor has a length L2 along the column direction and satisfies n×l1+ (n-1) (x 2-x 1) =ml2+ (m-1) ×x2, each first transistor has a pitch x1 along the column direction with one of the adjacent second transistors, each second transistor has a pitch x2 along the column direction, and satisfies x2> (x 1-x 2) ×1.3.

The invention discloses a grid driving device which comprises a substrate and a plurality of shift registers. The shift register is formed on the glass substrate, each stage is coupled in series, and generates a plurality of gate driving signals respectively, and the shift register of the Nth stage comprises a pull-up unit. The pull-up unit is provided with a control end for receiving a control signal, and provides a clock signal to the output end according to the control signal so as to generate an N-stage grid driving signal, and comprises a plurality of first transistors and a plurality of second transistors. The first transistor is located at the outermost side of the pull-up unit. The second transistors are surrounded by the first transistors, and each of the first transistors and one of the second transistors adjacent thereto are offset in the row direction.

The invention provides a display panel which is provided with a display area and a peripheral area, wherein the peripheral area is positioned on at least one side of the display area and comprises a grid driving device and a pixel array. The gate driving device is located in the peripheral area. The pixel array is located in the display area.

In view of the foregoing, in the gate driving device according to an embodiment of the invention, the second transistors are surrounded by the first transistors, wherein each of the second transistors has a length L2 along the column direction, and satisfies n×l1+ (n-1) ×2-x 1) =ml2+ (m-1) ×2, each of the first transistors and one of the adjacent second transistors has a spacing x1 along the column direction, each of the second transistors has a spacing x2 along the column direction, and satisfies x2> (x 1-x 2) ×1.3, so that a heat dissipation area in a center of the pull-up unit can be increased, and adverse effects on an electrical property of the pull-up unit due to self-heating effect in the center can be avoided. Therefore, the gate driving device of the present invention has improved reliability. For similar reasons, the display panel of the present invention has improved reliability.

Drawings

Various aspects of the disclosure can be appreciated upon reading the following detailed description in conjunction with the corresponding figures. It should be noted that the various features of the drawings are not drawn to scale in accordance with practices standard in the art. In fact, the dimensions of the features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a schematic top view of a gate driving device according to an embodiment of the invention.

Fig. 2 is a schematic block diagram of a gate driving device according to an embodiment of the invention.

FIG. 3 is an equivalent circuit diagram of the N-th shift register.

FIG. 4 is a timing diagram of the N-th stage shift register of FIG. 3.

Fig. 5 is a schematic top view of the circuit layout of the pull-up unit.

Fig. 6 is a schematic cross-sectional view of fig. 5 along section line A-A'.

Fig. 7 is a schematic cross-sectional view of fig. 5 along section line B-B'.

Fig. 8 is a schematic top view of a first transistor according to another embodiment of the invention.

Fig. 9 is a schematic cross-sectional view of section line C-C' of fig. 8.

Fig. 10 is a schematic top view of a second transistor according to another embodiment of the invention.

Fig. 11 is a schematic cross-sectional view of section line D-D' of fig. 10.

Fig. 12 is a schematic top view of a pull-up unit of a gate driving device according to another embodiment of the invention.

Fig. 13 is a schematic top view of the pull-up unit of the comparative example.

Fig. 14 is a schematic top view of a pull-up unit of a gate driving device according to another embodiment of the invention.

Fig. 15 is a schematic cross-sectional view of fig. 12 along section line E-E'.

Fig. 16 is a schematic cross-sectional view of fig. 12 along section line F-F'.

Fig. 17 is a schematic top view of a display panel according to an embodiment of the invention.

Fig. 18 shows a partial cross-sectional view of the pixel array of fig. 17 and a partial cross-sectional view of the gate driving device.

Reference numerals illustrate:

10,20,42: gate driving device

40: display panel

100: substrate board

102: pull-up control unit

104,204 a,304: pull-up unit

106: pull-down unit

108,108a,208 a: first transistor

110,110a,210 a: second transistor

308,408: first transistor

310,410: second transistor

112: gate insulating layer

114: interlayer dielectric layer

116: insulating layer

a1: first direction

a2: second direction

a3: third direction of

a4: fourth direction

AA: display area

AR: pixel array

A-A ', B-B': line of cutting

CH1, CH2, CH5: channel layer

CK: clock signal

C-C ', D-D', E-E ', F-F': line of cutting

D1, D1a, D1b, D1c: drain electrode

D2, D2a, D2b, D2c, D5: drain electrode

d1, d2, d3, d4, d5, d6, d7: distance of

d8, d9, d10, d11, d12: distance of

G1, G1a, G1b, G1c: grid electrode

G2, G2a, G2c, G5: grid electrode

G [ N ]: n-th stage gate driving signal

G [ N-1], G [ N+1]: input signal

GOUT [ N ]: an output terminal

L1, L2: length of

PA: peripheral region

PE: pixel electrode

PX: pixel arrangement

QN: node

R1: region(s)

S1, S1a, S1b, S1c: source electrode

S2, S2a, S2c, S5: source electrode

SR: shift register

STV: start pulse

T1: first switch

T2: second switch

T3: third switch

T4: fourth switch

T5: active device

x1, x2, x3, y1, y2: spacing of

Detailed Description

The present invention will be described more fully hereinafter with reference to the accompanying drawings of this embodiment. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The dimensions and thicknesses of the various components in the figures are appropriately adjusted for clarity, and the invention is not limited thereto. The same or similar reference numerals denote the same or similar elements, and the following paragraphs will not be repeated. In addition, directional terms mentioned in the embodiments, such as: upper, lower, left, right, front or rear, etc., are merely references to the directions of the attached drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the invention.

Fig. 1 is a schematic top view of a gate driving device 10 according to an embodiment of the invention. The gate driving device 10 includes a glass substrate 100 and a plurality of shift registers SR formed on the glass substrate 100, each stage being coupled in series with each other, and generating a plurality of gate driving signals, respectively.

Fig. 2 is a schematic block diagram of a circuit of the gate driving device 10 according to an embodiment of the invention, please refer to fig. 1 and 2 together, in which each shift register SR of the gate driving device 10 has a start pulse, which is denoted as STV. In this embodiment, the start pulse STV is enabled when driving of one frame is started. The gate driving device 10 has at least one bus line (not shown). The bus line (not shown) is used for receiving the clock signal CK. After receiving the clock signal CK from the bus line (not shown), the shift register SR converts the clock signal CK into the gate driving signals G1-Gn corresponding to the scan lines (not shown), and generates the push signals for transferring to the shift register SR of the next stage, thereby driving all the scan lines (not shown) repeatedly. The clock signal CK is disabled until the last shift register SR outputs the gate driving signal Gn. However, the present invention is not limited thereto, and the shift register SR may have other electrode structures or elements.

Fig. 3 is an equivalent circuit schematic diagram of the shift register SR of the nth stage, and fig. 4 is a timing chart of the shift register SR of the nth stage of fig. 3, referring to fig. 3 and 4, the shift register SR of the nth stage includes a pull-up control unit 102, a pull-up unit 104 and a pull-down unit 106. The pull-up control unit 102 includes a first switch T1, the pull-up unit 104 includes a second switch T2, and the pull-down unit 106 includes a third switch T3 and a fourth switch T4.

The pull-up unit 104 has a control terminal for receiving the control signal, and provides a clock signal to the output terminal according to the control signal to generate an N-th gate driving signal G [ N ]. For example, the first switch T1 receives an input signal G [ N-1], and the fourth switch T4 receives an input signal G [ N+1]. The input signal G [ N-1] and the input signal G [ N+1] come from the input ends of the shift register SR of the previous stage and the next stage. The first terminal (one of the source/drain terminals) of the second switch T2 receives the clock signal CK, the control terminal of the second switch T2 is coupled to the node QN, and the second terminal (the other of the source/drain terminals) of the second switch T2 is coupled to the output terminal GOUT [ N ] of the N-th shift register SR for outputting the N-th gate driving signal G [ N ].

The first end of the fourth switch T4 is coupled to the node QN, the first end of the third switch T3 is coupled to the output end GOUT [ N ] of the shift register SR, and the second end of the fourth switch T4 and the second end of the third switch T3 are both coupled to the system voltage end VSS. The potential of the system voltage terminal VSS may be the same as the gate low voltage VGL. The input signal G [ N+1] is transmitted to the control terminal of the fourth switch T4 and the control terminal of the third switch T3 to control the opening and closing of the fourth switch T4 and the third switch T3. The clock signal CK is switched between the gate high voltage VGH and the gate low voltage VGL.

Fig. 5 is a schematic top view of the circuit layout of the pull-up unit 104. Fig. 6 is a schematic cross-sectional view of fig. 5 along section line A-A'. Fig. 7 is a schematic cross-sectional view of fig. 5 along section line B-B'. Referring to fig. 5 to fig. 7, the pull-up unit 104 includes a plurality of first transistors 108 and a plurality of second transistors 110. In other words, the second switch T2 is formed by the plurality of first transistors 108 and the plurality of second transistors 110 (see fig. 3). The first transistor 108 is located at the outermost side of the pull-up unit 104. For example, at least one side of the first transistor 108 is not configured with the first transistor 108 and not configured with the second transistor 110. Each first transistor 108 has a length L1 along the column direction. For convenience of explanation, fig. 5 shows a first direction a1 and a second direction a2, and the first direction a1 and the second direction a2 intersect. For example, the first direction a1 and the second direction a2 may be substantially perpendicular to each other. In the present embodiment, the column direction is, for example, the first direction a1 in fig. 5. The second transistor 110 is surrounded by the first transistor 108. For example, the second transistor 110 or the first transistor 108 is disposed on four sides of the second transistor 110. Each of the second transistors 110 has a length L2 along the column direction, and satisfies nl1+ (n-1), (x 2-x 1) =ml2+ (m-1) ×2, and each of the first transistors 108 and one of the adjacent second transistors 110 has a pitch x1 along the column direction. Each of the second transistors 110 has a pitch x2 along the column direction, and satisfies x2> (x 1-x 2) by 1.3. Therefore, the heat dissipation area in the center of the pull-up unit 104 can be increased without affecting the area of the pull-up unit 104 in the shift register SR (see fig. 1), so as to avoid the negative effect of self-heating effect on the electrical property in the center of the pull-up unit 104, and improve the reliability of the gate driving device 10 (see fig. 1). For example, the change of the threshold voltage (threshold voltage; vth) of the second transistor 110 due to the self-heating effect can be avoided, and the degradation of the start-up current (Ion) of the second transistor 110 due to the self-heating effect can be reduced. When the gate driving device 10 (see fig. 1) is applied to a large-sized display panel requiring high voltage and high current to operate, the above-mentioned adverse effects caused by the self-heating effect can be effectively reduced.

The first transistor 108 may include a source S1, a drain D1, a gate G1, and a channel layer CH1. The length L1 of each first transistor 108 in the column direction is equivalent to the length of its channel layer CH1 in the column direction. The second transistor 110 may include a source S2, a drain D2, a gate G2, and a channel layer CH2. The length L2 of each second transistor 110 along the column direction is equivalent to the length of its channel layer CH2 along the column direction. The materials of the channel layers CH1 and CH2 include low temperature polysilicon (low temperature crystalline silicon, LTPS), oxide semiconductors such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), or the like, based on the consideration of electron mobility. The channel layer CH1 and the channel layer CH2 are disposed on the glass substrate 100.

The pull-up unit 104 further includes a gate insulating layer 112, an interlayer dielectric layer 114, and an insulating layer 116. The gate insulating layer 112 is disposed between the channel layer CH1 and the gate G1 and between the channel layer CH2 and the gate G2. For example, in the present embodiment, the gate G1 of the first transistor 108 is disposed above the channel layer CH1, and the gate G2 of the second transistor 110 is disposed above the channel layer CH2 to form a top-gate thin film transistor (top-gate TFT), but the invention is not limited thereto. According to other embodiments, the gate G1 of the first transistor 108 may also be disposed under the channel layer CH1, and the gate G2 of the second transistor 110 may also be disposed under the channel layer CH2, i.e., the gates G1 and G2 are located between the channel layer CH1, the channel layer CH2 and the glass substrate 100, so as to form a bottom-gate thin film transistor (bottom-gate TFT).

The interlayer dielectric layer 114 covers the gates G1 and G2, and the sources S1 and S2 and the drains D1 and D2 penetrate through the interlayer dielectric layer 114 and the gate insulating layer 112 to be electrically connected to the channel layers CH1 and CH2, respectively. The insulating layer 116 is disposed on the interlayer dielectric layer 114 to cover the sources S1 and S2 and the drains D1 and D2. In the present embodiment, the materials of the gate insulating layer 112, the interlayer dielectric layer 114 and the insulating layer 116 may be inorganic materials or organic materials or a combination thereof. The inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride or a stacked layer of at least two of the above materials, but the invention is not limited thereto.

In the present embodiment, one of each of the first transistors 108 and the second transistor 110 adjacent thereto has a spacing y1 along the row direction, and x2> y1 is satisfied. In the present embodiment, the row direction is, for example, the second direction a2 in fig. 5. Accordingly, the heat dissipation area in the center of the pull-up unit 104 can be increased.

In the present embodiment, each of the second transistors 110 has a pitch y2 along the row direction, and y2> y1 is satisfied. For example, y2>1.3 x y1 is satisfied. Accordingly, the heat dissipation area in the center of the pull-up unit 104 can be increased.

Fig. 8 is a schematic top view of a first transistor 108a according to another embodiment of the invention, fig. 9 is a schematic cross-sectional view of a section line C-C' of fig. 8, and the first transistor 108a of the present embodiment is different from the first transistor 108 of fig. 6 in that the first transistor 108a of the present embodiment has a first gate G1a, a first source S1a and a first drain D1a, and a distance D1 between the first drain D1a and the first gate G1a is greater than a distance D2 between the first source S1a and the first gate G1 a. Therefore, the first drain electrode D1a can be efficiently dissipated. When the gate driving device 10 is applied to a large-sized display panel requiring high voltage and high current for operation, the adverse effect of the self-heating effect on the first drain D1a of the first transistor 108a can be effectively reduced, and the pull-up unit employing the first transistor 108a of the present embodiment is suitable for unidirectional operation.

Fig. 10 is a schematic top view of a second transistor 110a according to another embodiment of the invention, fig. 11 is a schematic cross-sectional view of a section line D-D' of fig. 10, and the second transistor 110a of the present embodiment is different from the second transistor 110 of fig. 7 in that the second transistor 110a of the present embodiment has a second gate G2a, a second source S2a and a second drain D2a, and a distance D3 between the second drain D2a and the second gate G2a is greater than a distance D4 between the second source S2a and the second gate G2 a. Therefore, the second drain electrode D2a can be effectively dissipated. When the gate driving device 10 is applied to a large-sized display panel requiring high voltage and high current for operation, the adverse effect of the self-heating effect on the second drain D2a of the second transistor 110a can be effectively reduced, and the pull-up unit employing the second transistor 110a of the present embodiment is suitable for unidirectional operation.

Fig. 12 is a schematic top view of a pull-up unit 204 of a gate driving device 20 according to another embodiment of the invention, and fig. 13 is a schematic top view of a pull-up unit 304 of a comparative example. Referring to fig. 12, the pull-up unit 204 of the present embodiment includes a plurality of first transistors 208 and a plurality of second transistors 210. The first transistor 208 is located at the outermost side of the pull-up unit 204. The second transistors 210 are surrounded by the first transistors 208, wherein each of the first transistors 208 and one of the second transistors 210 adjacent thereto are offset in the row direction. Next, referring to fig. 13, one of the first transistor 308 and the second transistor 310 adjacent thereto of the comparative example is not shifted along the row direction. As shown in fig. 12 and 13, when the pull-up unit 204 and the pull-up unit 304 are divided into a plurality of rectangular regions R1 along the column direction, the coverage area of the first transistor 208 and the second transistor 210 in fig. 12 in each region R1 is smaller than the coverage area of the first transistor 308 and the second transistor 310 in fig. 13 in each region R1. In other words, the occupied area of the first transistor 208 and the second transistor 210 of the pull-up unit 204 of the present embodiment is smaller than that of the first transistor 308 and the second transistor 310 of the pull-up unit 304 of the comparative example, so that the heat dissipation area of the pull-up unit 204 of the present embodiment is increased, and the distance x3 between the first transistor 208 and one of the adjacent second transistors 210 is increased, thereby avoiding the negative effect on the electrical property of the center of the pull-up unit 204 due to the self-heating effect, and improving the reliability of the gate driving device. The distance x3 refers to a connection distance between the top side of the first transistor 208 and the top side of the second transistor 210 adjacent thereto or a connection distance between the bottom side of the first transistor 208 and the bottom side of the second transistor 210 adjacent thereto in a top view. Other components of the gate driving device of the present embodiment are similar to those of the gate driving device of fig. 1, and are not described herein.

Fig. 14 is a schematic top view of a pull-up unit 204a of a gate driving device according to another embodiment of the invention. The difference between the pull-up unit 204a of the present embodiment and the pull-up unit 204 of fig. 12 is that the second transistors 210a are arranged in the 1 st to n th rows, n is a positive integer greater than or equal to 2, and the second transistors 210a in two adjacent rows are offset along the row direction. As described above, the center of the pull-up unit 204a can be prevented from negatively affecting the electrical property due to the self-thermal effect, so that the reliability of the gate driving device can be improved.

Returning to fig. 12, the structure of the first transistor 208 of fig. 12 may be similar to the structure of the first transistor 108 of fig. 6 or the first transistor 108a of fig. 9, and the structure of the second transistor 210 of fig. 12 may be similar to the structure of the second transistor 110 of fig. 7 or the second transistor 110a of fig. 11. For example, fig. 15 is a schematic cross-sectional view along a section line E-E 'in fig. 12, fig. 16 is a schematic cross-sectional view along a section line F-F' in fig. 12, and fig. 15 and 16 show examples in which the structure of the first transistor 208 and the structure of the second transistor 210 in fig. 12 are similar to the structure of the first transistor 108a and the structure of the second transistor 110a in fig. 9 and 11, respectively, referring to fig. 15 and 16, each first transistor 208 has a first gate G1b, a first source S1b and a first drain D1b, and a distance D5 between the first drain D1b and the first gate G1b is greater than a distance D6 between the first source S1b and the first gate G1 b. Each of the second transistors 210 has a second gate G2b, a second source S2b, and a second drain D2b, wherein a distance D7 between the second drain D2b and the second gate G2b is greater than a distance D8 between the second source S2b and the second gate G2 b. Thus, the first drain D1b and the second drain D2b can be effectively dissipated. When the gate driving device is applied to a large-sized display panel requiring high voltage and high current for operation, the negative effects of the self-heating effect on the first drain D1b of the first transistor 208 and the second drain D2b of the second transistor 210 can be effectively reduced, and the pull-up unit 204 employing the first transistor 208 and the second transistor 210 of the present embodiment is suitable for unidirectional operation.

Fig. 17 is a schematic top view of a display panel 40 according to an embodiment of the invention. The display panel 40 has a display area AA and a peripheral area PA, and the peripheral area PA is located at least on one side of the display area AA. The display panel 40 includes at least one gate driving device 42, and the gate driving device 10 is located at the peripheral area PA. The pixel array AR is located in the display area AA. The configuration of the gate driving device 42 is similar to that of the gate driving device 10 of the previous embodiment, and thus the display panel 40 of the present invention has improved reliability for similar reasons.

Fig. 18 shows a partial cross-sectional view of the pixel array AR of fig. 17 and a partial cross-sectional view of the gate driving device 42. Referring to fig. 17 and 18, as described above, the gate driving device 42 includes a plurality of first transistors 408 and a plurality of second transistors 410. In an embodiment, the first transistor 408 has a first gate G1c, a first source S1c and a first drain D1c, and a distance D9 between the first drain D1c and the first gate G1c is greater than a distance D10 between the first source S1c and the first gate G1 c. Therefore, the first drain electrode D1c can be effectively dissipated. When the gate driving device 42 is applied to a large-sized display panel requiring high voltage and high current for operation, the adverse effect of the self-heating effect on the first drain D1c of the first transistor 408 can be effectively reduced, and the gate driving device 42 of the present embodiment is suitable for unidirectional operation. The second transistor 410 has a second gate G2c, a second source S2c and a second drain D2c, wherein a distance D11 between the second drain D2c and the second gate G2c is greater than a distance D12 between the second source S2c and the second gate G2 c. Therefore, the second drain electrode D2c can be effectively dissipated. When the gate driving device 42 is applied to a large-sized display panel requiring high voltage and high current for operation, the adverse effect of the self-heating effect on the second drain D2c of the second transistor 410 can be effectively reduced, and the gate driving device 42 of the present embodiment is suitable for unidirectional operation.

The pixel array AR includes a plurality of pixels PX. For convenience of explanation, fig. 17 shows a third direction a3 and a fourth direction a4, and the third direction a3 is different from the fourth direction a4, for example, the third direction a3 and the fourth direction a4 are the lateral direction and the longitudinal direction of fig. 17, respectively, and are in an orthogonal relationship with each other. The pixels PX are arranged along the third direction a3 and the fourth direction a 4.

Each pixel PX may include an active device T5 and a pixel electrode PE electrically connected to the active device T5. The active device T5 is disposed on the glass substrate 100 and has a gate G5, a source S5, a drain D5, and a channel layer CH5. The gate insulating layer 112 is disposed between the channel layer CH5 and the gate G5. For example, the gate G5 of the active device T5 may be selectively disposed above the channel layer CH5 to form a top gate thin film transistor (top gate TFT), but the invention is not limited thereto. According to other embodiments, the gate G5 of the active device T5 may also be disposed under the channel layer CH5, i.e., the gate G5 is located between the channel layer CH5 and the glass substrate 100 to form a bottom gate thin film transistor (bottom gate TFT).

The material of the channel layer CH5 of the active device T5 includes low temperature polysilicon (low temperature crystalline silicon, LTPS), an oxide semiconductor (e.g., indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), etc.), or the like, based on the consideration of electron mobility. The channel layer CH5 is disposed on the glass substrate 100. In the present embodiment, one of the channel layer CH1 of the first transistor 108 and the channel layer CH5 of the active device T5 is low-temperature polysilicon (low temperature crystalline silicon, LTPS), wherein the other is an oxide semiconductor (e.g., indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or the like), that is, the display panel 40 is a low-temperature polysilicon oxide (Low Temperature Polycrystalline Oxide, LTPO) display panel.

The interlayer dielectric 114 covers the gate G5 of the active device T5. The source S5 and the drain D5 of the active device T5 are disposed on the interlayer dielectric 114. For example, the source S5 and the drain D5 of the active device T5 penetrate the interlayer dielectric 114 and the gate insulating layer 112 to electrically connect to the channel layer CH5.

In summary, in the gate driving device according to an embodiment of the invention, the second transistors are surrounded by the first transistors, wherein each of the second transistors has a length L2 along the row direction and satisfies n×l1+ (n-1) ×l2+ (m-1) x2, each of the first transistors and one of the adjacent second transistors has a spacing x1 along the row direction, each of the second transistors has a spacing x2 along the row direction and satisfies x2> (x 1-x 2) x 1.3, so that a heat dissipation area in the center of the pull-up unit can be increased, and adverse effects on the electrical properties of the pull-up unit due to self-heating effect in the center of the pull-up unit can be avoided. Therefore, the gate driving device of the present invention has improved reliability. For similar reasons, the display panel of the present invention has improved reliability.

Claims

1. A gate driving apparatus, comprising:

a glass substrate; and

The shift registers are formed on the glass substrate, each stage is coupled in series, and respectively generate a plurality of gate driving signals, wherein the shift register of the Nth stage comprises:

a pull-up unit having a control terminal for receiving a control signal and providing a clock signal to an output terminal according to the control signal to generate an nth stage gate driving signal, the pull-up unit comprising:

a plurality of first transistors located at the outermost side of the pull-up unit, each of the first transistors having a length L1 along the column direction; and

The second transistors are surrounded by the first transistors, wherein each second transistor has a length L2 along the row direction and satisfies nL1+ (n-1), (x 2-x 1) =mL2+ (m-1) ×2, each first transistor and one of the adjacent second transistors have a spacing x1 along the row direction, each second transistor has a spacing x2 along the row direction, and satisfies x2> (x 1-x 2) ×1.3, m >0, n >0.

2. The gate driving device according to claim 1, wherein each of the first transistor and one of the second transistors adjacent thereto has a pitch y1 along a row direction and satisfies x2> y1.

3. The gate driving device according to claim 2, wherein each of the second transistors has a pitch y2 along the row direction, and y2>1.3 x y1 is satisfied.

4. The gate driving device of claim 1, wherein each of the first transistors has a first gate, a first source and a first drain, and a distance between the first drain and the first gate is greater than a distance between the first source and the first gate.

5. The gate driving device of claim 1, wherein each of the second transistors has a second gate, a second source and a second drain, and a distance between the second drain and the second gate is greater than a distance between the second source and the second gate.

6. A gate driving apparatus, comprising:

a glass substrate; and

a plurality of first transistors located at the outermost side of the pull-up unit; and

The plurality of second transistors are surrounded by the first transistors, wherein each of the first transistors and one of the second transistors adjacent to the first transistor are staggered along the row direction, and the first transistors and the second transistors are not arranged in a straight line but are arranged in a bending or zigzag manner along the row direction.

7. The gate driving device according to claim 6, wherein the second transistors are arranged in 1 st to n th rows, n being a positive integer greater than or equal to 2, and the second transistors of two adjacent rows are offset in a row direction.

8. The gate driving device of claim 6, wherein each of the first transistors has a first gate, a first source and a first drain, and a distance between the first drain and the first gate is greater than a distance between the first source and the first gate.

9. The gate driving device of claim 6, wherein each of the second transistors has a second gate, a second source and a second drain, and a distance between the second drain and the second gate is greater than a distance between the second source and the second gate.

10. A display panel is provided with a display area and a peripheral area, wherein the peripheral area is positioned on at least one side of the display area and comprises:

a gate driving device according to any one of claims 1 to 9, located in the peripheral region; and

And a pixel array positioned in the display area.