CN114020139A - CPU power consumption management method, computer device and computer readable storage medium - Google Patents

CPU power consumption management method, computer device and computer readable storage medium Download PDF

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CN114020139A
CN114020139A CN202111308013.1A CN202111308013A CN114020139A CN 114020139 A CN114020139 A CN 114020139A CN 202111308013 A CN202111308013 A CN 202111308013A CN 114020139 A CN114020139 A CN 114020139A
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core
cpu
power
cpu core
cluster
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樊卿华
朱振华
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Allwinner Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU

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Abstract

The invention provides a CPU power consumption management method, a computer device and a computer readable storage medium, wherein the method comprises the steps of setting a plurality of working states of a CPU core in a switch core wake-up mode; the target CPU core enters a pre-power-down state after receiving a closing instruction sent by a user mode application program, and enters a core power-down state after closing a local interrupt wake-up source; when all CPU cores of a CPU core cluster enter a core power-down state, all CPU cores of the cluster enter a cluster power-down state; when any CPU core of the CPU core cluster receives a kernel opening instruction sent by a user mode application program, all CPU cores of the cluster exit from the cluster power-down state to a core power-down state; if the core opening instruction aims at the target CPU core, or a newly generated core opening instruction aiming at the target CPU core occurs, the target CPU core exits from the core power-down state to the power-up state. The invention also provides a computer device and a computer readable storage medium for realizing the method. The invention can improve the compatibility of the electronic equipment to the low-power consumption processing of the CPU.

Description

CPU power consumption management method, computer device and computer readable storage medium
Technical Field
The invention relates to the technical field of power management of electronic equipment, in particular to a CPU power consumption management method, a computer device for realizing the method and a computer readable storage medium.
Background
Electronic devices such as smart phones, tablet computers, set-top boxes, automobile data recorders, and the like are common electronic devices. With the increasing functions of electronic devices, more functional modules are needed to be installed in the electronic devices, for example, besides a multi-core CPU, a GPU (graphics processing unit) is often installed, and a DDR memory is also needed to be installed. Because the electronic equipment needs to realize more functions, the electricity consumption of each module is more and more, and the endurance capacity of the electronic equipment is greatly influenced.
Generally, the power consumption of an integrated circuit mainly consists of dynamic power consumption and static power consumption, wherein the dynamic power consumption is mainly generated by a logic gate turning process in the circuit and is generally proportional to the operating frequency of the circuit, and the static power consumption is mainly generated by static leakage and is generally related to voltage and temperature. In the field of Linux operating systems, the following two techniques are generally used to manage the power consumption of a CPU: CPU interrupt wake (CPU idle) technology and CPU switch core wake (CPU hot plug) technology.
The CPU interrupt wakeup technology is to perform power consumption processing in the micro-domain, and mainly allows the CPU to control the dynamic power consumption of the CPU by turning off its clock and/or power supply at an idle time, for example, when the CPU is in an idle state in a certain micro time slice, i.e., "no matter is done", the operating system sets the CPU in a certain low power consumption state to reduce the dynamic power consumption and the static power consumption of the CPU. When the interrupt comes on, the CPU can be quickly awakened and resume performing tasks. From the macro perspective of the user-mode application, the CPU is always running.
The CPU switching core awakening technology focuses on power consumption processing in the macroscopic field, the number of CPU cores in a working state at the current moment is determined by measuring CPU load, and the technology directly turns off clocks and power supplies of CPUs which do not need to work so as to control dynamic power consumption and static power consumption of the CPUs. Specifically, the technical user mode application program provides an option for switching on and off the CPU, and if the computing capacity requirement of the CPU in the current operation scene is not high, the user mode application program can select to close part of CPU cores to reduce the CPU power consumption, including dynamic power consumption and static power consumption. When the computing power requirement of the operating system is high, the user mode application program can reopen the closed CPU core to improve the performance of the operating system.
However, the two technologies are independent and incompatible in the real process, which results in higher cost of the CPU power consumption processing scheme of the electronic device, and poor compatibility in response to the operating speed of the electronic device.
Disclosure of Invention
The first purpose of the invention is to provide a method for managing the CPU power consumption, which can realize that the CPU interrupt awakening technology and the CPU switch core awakening technology are unified on the bottom layer.
The second purpose of the present invention is to provide a computer device for implementing the above CPU power consumption management method.
A third object of the present invention is to provide a computer-readable storage medium for implementing the above CPU power consumption management method.
In order to achieve the first object of the present invention, the CPU power consumption management method provided by the present invention includes setting a plurality of operating states of a CPU core in a switch core wake-up mode: the working state comprises a power-on state, a pre-power-off state, a core power-off state and a cluster power-off state; in the switch core wake-up mode: after the target CPU core receives a closing instruction sent by a user mode application program, the target CPU core sets a pre-power-down mark and enters a pre-power-down state, and after a local interrupt wake-up source is closed, the target CPU core enters a core power-down state; in a CPU core cluster where a target CPU core is located, after all CPU cores enter a core power-down state, all CPU cores of the cluster enter a cluster power-down state; when any CPU core of a CPU core cluster where a target CPU core is located receives a core opening instruction sent by a user mode application program, all CPU cores of the cluster exit from a cluster power-down state to a core power-down state; and if the received core opening instruction sent by the user mode application program is directed at the target CPU core, or a newly generated core opening instruction directed at the target CPU core occurs, the target CPU core exits from the core power-down state to the power-up state.
According to the scheme, under the CPU switch core wake-up mode, a plurality of working states of the CPU are the same as a plurality of working states under the CPU interrupt wake-up mode, so that the CPU switch core wake-up mode can be realized by controlling the conversion of the CPU among the plurality of states to realize the bottom layer unification of the CPU interrupt wake-up mode and the CPU switch core wake-up mode, the realization cost of the low-power-consumption solution of the electronic equipment is reduced, and the running speed of the electronic equipment can be increased.
And in the CPU switch core wake-up mode, the CPU core switches the working state according to a core opening instruction and a core closing instruction sent by a user mode application program, so that the CPU switch core wake-up mode is compatible with the traditional CPU switch core wake-up technology.
In a preferred scheme, the target CPU core performs a context protection operation after the local interrupt wake source is turned off.
Therefore, by performing protection operation on the context, the work site can be protected before the CPU core is closed, so that the CPU can be recovered to the previous site after being powered on.
The further scheme is that if the core opening instruction is not directed to the target CPU core and a newly generated core opening instruction directed to the target CPU core does not occur, the target CPU core is kept in a core power-down state.
It can be seen that if the open core instruction is not for the target CPU core, the target CPU core remains in the core power-down state to avoid powering up the target CPU core, so as to ensure that the CPU core can operate in a low power consumption mode.
In a further aspect, the plurality of operating states of the CPU core in the switch core wake mode are the same as the plurality of operating states of the CPU core in the interrupt wake mode.
In a preferred embodiment, in the interrupt wake-up mode: when the time that the target CPU core is in the idle state exceeds a preset threshold value, a pre-power-down mark is set, the target CPU core enters a pre-power-down state, and the target CPU core enters a core power-down state; in a CPU core cluster where a target CPU core is located, after all CPU cores enter a core power-down state, all CPU cores of the cluster enter a cluster power-down state; when any CPU core of the CPU core cluster where the target CPU core is positioned receives an interrupt request, all CPU cores of the cluster exit from the cluster power-down state to a core power-down state; if the interrupt request instruction is directed to the target CPU core, or a newly generated interrupt request instruction directed to the target CPU core occurs, the target CPU core exits from the core power-down state to the power-up state.
In a further scheme, in the switch core wake-up mode, if the target CPU core is in the cluster power-down state, the target CPU core is kept in the cluster power-down state when receiving the interrupt request instruction.
Therefore, the interrupt request instruction in the switch core wake-up mode does not wake up the CPU core, and is consistent with the working requirement of the conventional switch core wake-up mode, so as to ensure that the user-mode application program correctly controls the CPU to work in the switch core wake-up mode.
In a further scheme, each CPU core in the same CPU core cluster is provided with an independent primary buffer. Furthermore, a plurality of CPU cores in the same CPU core cluster use the same secondary buffer.
In order to achieve the second object, the present invention provides a computer device including a processor and a memory, wherein the memory stores a computer program, and the computer program implements the steps of the CPU power consumption management method when executed by the processor.
To achieve the third objective, the present invention provides a computer-readable storage medium having a computer program stored thereon, where the computer program is executed by a processor to implement the steps of the CPU power consumption management method.
Drawings
Fig. 1 is a topological diagram of a plurality of CPUs to which an embodiment of the CPU power consumption management method of the present invention is applied.
Fig. 2 is a state transition diagram of a CPU core according to an embodiment of the CPU power consumption management method of the present invention.
Fig. 3 is a state transition diagram of a plurality of CPU cores in a power-on or wake-up state according to an embodiment of the CPU power consumption management method of the present invention.
Fig. 4 is a state transition diagram of a plurality of CPU cores in a shutdown or hibernation state in an embodiment of the CPU power consumption management method of the present invention.
Fig. 5 is a schematic block diagram of CPU operating mode selection in an embodiment of the CPU power consumption management method of the present invention.
The invention is further explained with reference to the drawings and the embodiments.
Detailed Description
The CPU power consumption management method is applied to electronic equipment, such as a vehicle event data recorder, a set top box and other electronic equipment, so as to manage the power consumption of the CPU and reduce the implementation cost of the CPU low power consumption scheme. Preferably, the electronic device is provided with a processor and a memory, the memory having stored thereon a computer program, and the processor implements the CPU power consumption management method by executing the computer program.
The embodiment of the CPU power consumption management method comprises the following steps:
the embodiment is applied to an electronic device, a CPU of the electronic device has a plurality of CPU cores, and as shown in fig. 1, the CPU provided in the electronic device is an SMP CPU with dual cores and dual clusters. The CPU topology is shown in fig. 1. The CPU includes two independent CPU core clusters 11 and 12, each including two CPU cores, for example, the CPU core cluster 11 includes a CPU core 0 and a CPU core 1, and the CPU core cluster 12 includes a CPU core 2 and a CPU core 3. Moreover, each CPU core is provided with an independent primary buffer, i.e., L1 cache, and a plurality of CPU cores of the same CPU core cluster share one secondary buffer, i.e., L2 cache. For example, CPU core 0 and CPU core 1 of CPU core cluster 11 share second level buffer 15, and CPU core 2 and CPU core 3 of CPU core cluster 12 share second level buffer 16. And each CPU core can independently control a power switch, namely the power of each CPU core can be independently turned on or off, and when a plurality of CPU cores of the same CPU core cluster are powered off, the power of the CPU core cluster is also turned off.
In this embodiment, the operating states of the CPU cores in the two modes are unified, that is, the same operating state is switched regardless of which mode the CPU core is managed in.
The following describes the operation state transition flow of each CPU core in the present embodiment with reference to fig. 2. Each CPU core has four states, Power on C0, Power for idle C0', core Power Down C1, and Cluster Power Down C2.
The following description will be given taking the CPU core 0 as an example. In the initial state, both the CPU core 0 and the CPU core 1 are in the power-on state C0, and when the CPU core 0 meets a specific condition, for example, the time that the CPU core 0 is in the idle state exceeds a preset threshold, or the operating system sends a shutdown instruction to the CPU core 0, the CPU core 0 will execute the P0 process, and enter the pre-power-off state C0' from the power-on state C0. At this time, the CPU core 0 sets a pre-power-down flag, that is, sets an idle state flag, and executes a pre-power-down instruction at the same time. Then, the CPU core 0 performs a context protection operation, and if the CPU core is in the switch core wake mode, the local interrupt wake source needs to be turned off, and the core power down state C1 is triggered to enter, and the process of entering the core power down state C1 from the pre-power down state C0' is a P1 process. Upon entering core power down state C1, the power to CPU core 0 is turned off, thereby reducing the power consumption of CPU core 0.
If the CPU core 1 also enters the core power down state C1 at this time, the CPU core 0 will execute the P3 process from the core power down state C1 to the cluster power down state C2. When both CPU cores of the CPU core cluster 11 are powered off, the CPU core cluster 11 will also turn off the power supply.
After the CPU core cluster 11 is powered off, if the CPU core cluster 11 meets a preset condition, for example, any one CPU core of the CPU core cluster 11 receives an interrupt request instruction or receives a core opening instruction sent by a user mode application program, all CPU cores of the CPU core cluster 11 exit from the cluster powered-off state C2 to the core powered-off state C1 state, that is, the process P3 is executed.
If the interrupt request instruction received by the CPU core cluster 11 is for the CPU core 0, or a new interrupt request instruction for the CPU core 0 is received, or the core opening instruction received by the CPU core cluster 11 is for the CPU core 0, or a new core opening instruction for the CPU core 0 is received, the CPU core 0 exits from the core power down state C1 to the power up state C0.
The various operating states and transition procedures of the CPU core are shown in table 1.
TABLE 1 multiple operating states and transition procedures for CPU cores
Figure BDA0003340841060000061
For the CPU interrupt wake mode, the operating state transition process of the CPU core is as follows. Taking the CPU core 0 as an example, referring to fig. 2, when the CPU core 0 is in the power-on state C0, if the time that the CPU core 0 is in the idle state exceeds a preset threshold, for example, is lower than a preset threshold, the CPU core 0 will execute the P0 process, and enter the pre-power-down state C0' from the power-on state C0. At this time, the CPU core 0 sets a pre-power-down flag, and executes a pre-power-down instruction at the same time. Also, CPU core 0 performs a context protection operation and triggers entry into core power down state C1.
If the CPU core 1 also enters the core power down state C1 at this time, the CPU core 0 enters the cluster power down state C2 from the core power down state C1. Moreover, when both CPU cores of the CPU core cluster 11 are powered off, the CPU core cluster 11 will also turn off the power supply.
When the CPU core cluster 11 is powered off, if any one of the CPU cores of the CPU core cluster 11 receives the interrupt request instruction, all the CPU cores of the CPU core cluster 11 exit from the cluster powered-off state C2 to the core powered-off state C1.
If the interrupt request instruction received by the CPU core cluster 11 is for CPU core 0, or a new interrupt request instruction is received for CPU core 0, then CPU core 0 exits from core power down state C1 to power up state C0.
In the CPU interrupt wake-up mode, the CPU core 0 does not receive a shutdown instruction or a core opening instruction sent by the user mode application program, and the CPU core 0 enters the pre-power-down state if the time that the CPU core 0 is in the idle state exceeds a preset threshold, which may be considered that the CPU core 0 "does nothing" in a certain time period, so that the power supply of the CPU core 0 may be shut down to save the power consumption of the electronic device. Once the CPU core 0 receives the interrupt request instruction, the CPU core 0 enters the power-on state immediately, and therefore, the condition for the CPU core 0 to exit from the core power-off state to the power-on state is that the interrupt request instruction for the CPU core 0 is received. In the CPU interrupt wake mode, the user mode application program always considers the CPU core 0 to be in the running state, and therefore, for the user mode application program, it is not perceived that the CPU core enters or exits the CPU interrupt wake mode.
For the CPU switch core wake mode, the operating state transition process of the CPU core is as follows. Taking the CPU core 0 as an example, referring to fig. 2, when the CPU core 0 is in the power-on state C0, if a user needs to turn off a part of the CPU core, and may turn off the part of the CPU core to reduce power consumption, the user mode application program sends an instruction to turn off the CPU core to the operating system, and the operating system initiates an operation to turn off the CPU core, for example, sends a turn-off instruction to the CPU core 0. When the CPU core 0 receives the shutdown instruction, it enters the pre-power-down state C0' from the power-on state C0. At this time, the CPU core 0 sets a pre-power-down flag, and executes a pre-power-down instruction at the same time. Also, CPU core 0 performs a context protection operation while turning off the local interrupt wake source and triggering entry into core power down state C1. It should be noted that once the CPU core 0 enters the core power-down state C1, even if an interrupt request instruction for the CPU core 0 is received, the CPU core 0 does not exit the power-down state, but remains in the power-down state.
After the CPU core 0 enters the core power down state C1, if the CPU core 1 also enters the core power down state C1 at this time, the CPU core 0 enters the cluster power down state C2 from the core power down state C1. Moreover, when both CPU cores of the CPU core cluster 11 are powered off, the CPU core cluster 11 will also turn off the power supply.
When the CPU core cluster 11 is powered off, if any one of the CPU cores of the CPU core cluster 11 receives the core opening instruction, all the CPU cores of the CPU core cluster 11 exit from the cluster powered-off state C2 to the core powered-off state C1. And, if the core power-off instruction is for CPU core 0, or a new core power-off instruction for CPU core 0 is received, CPU core 0 exits from core power-down state C1 to power-up state C0.
It can be seen that, in the CPU switch core wake-up mode, the condition that the CPU core 0 enters the pre-power-down state C0' is to receive a shutdown instruction sent by the user-mode application program, and the condition that the CPU core 0 exits from the power-down state to the power-up state is to receive a core-opening instruction sent by the user-mode application program. Therefore, the CPU core 0 is powered off or powered on according to the instruction sent by the user mode application program, and for the user mode application program, the CPU core can sense the power on and power off.
The following describes the state transition process of multiple CPU cores at power-on or wake-up with reference to fig. 3. In an initial state, the CPU core 0 is in the power-on state C0, the other three CPU cores are in the power-down state, and since the CPU core 0 is in the power-on state C0, the CPU core 1 is in the core power-down state C1, and the CPU cores 2 and 3 are in the cluster power-down state C2. When the operating system judges that the current operation capability is insufficient and the CPU core 1 needs to be started, the CPU core 1 exits from the core power-down state C1 to the power-up state C0, and at this time, the CPU core 2 and the CPU core 3 are still in the cluster power-down state C2.
After the user-mode application program sends the core opening instruction to the CPU core 2, both the CPU core 2 and the CPU core 3 exit to the core power-down state C1, and the CPU core 2 determines that the current core opening instruction is directed to the CPU core 2, and exits to the power-up state C0, but the CPU core 3 still maintains the core power-down state C1, until the CPU core 3 also receives the core opening instruction directed to the CPU core 3, the CPU core 3 exits to the power-up state C0.
The following describes a state transition process of a plurality of CPU cores when the CPU cores are powered off or hibernated, with reference to fig. 4. In the initial state, the four CPU cores are all in the power-on state C0. When the user mode application program sends an instruction to close the CPU core 3 and the operation state executes an action to close the CPU core 3, the CPU core 3 enters the pre-power-down state C0' from the power-on state C0, and performs operations such as context protection and the like, and enters the core power-down state C1. At this time, the CPU core 2 is still in the power-on state C0.
If the user-mode application program issues an instruction to close the CPU core 2, and the operating state executes an action to close the CPU core 2, the CPU core 2 also enters the pre-power-down state C0' from the power-on state C0, and performs operations such as context protection, and enters the core power-down state C1. At this time, since the CPU core 3 is already in the core power-down state C1, the CPU cores 2 and 3 will enter the cluster power-down state C2.
If the user-mode application program sends out an instruction for closing the CPU core 1, and the operation state executes an action for closing the CPU core 1, the CPU core 1 enters the pre-power-down state C0' from the power-on state C0, and performs operations such as context protection, and enters the core power-down state C1. At this point, CPU core 0 is still in the powered-on state C0. If the user mode application program sends an instruction to close the CPU core 0, the operating state executes an action to close the CPU core 0, and the CPU core 0 also enters the pre-power-down state C0' from the power-on state C0, and performs operations such as context protection, and enters the core power-down state C1. At this time, since CPU core 1 is already in core power down state C1, CPU core 0, CPU core 1 will enter cluster power down state C2. So far, all four CPU cores enter a cluster power-down state, and the two CPU core clusters are powered off.
Therefore, the CPU can operate in the CPU interrupt wake mode or the CPU switch core wake mode, and referring to fig. 5, the CPU power management logic is similar to the mode of selecting the CPU operation through one selection switch 30, that is, selecting the CPU to operate in the CPU interrupt wake mode or the CPU switch core wake mode, and controlling the operation modes of the plurality of CPU cores of the CPU core clusters 11 and 12 according to the corresponding modes.
It can be seen that, in this embodiment, the working states of the CPUs in the CPU interrupt wake-up mode and the CPU switch core wake-up mode are unified, that is, multiple working states in the CPU interrupt wake-up mode are also applicable to the working states in the CPU switch core wake-up mode, so that the electronic device only needs to set one state machine of each CPU, and for two different modes, the entry conditions and the exit conditions of the various working states are unified, so that the CPU interrupt wake-up mode and the CPU switch core wake-up mode are compatible with each other, so that the electronic device can implement two low power consumption modes at low cost, and can improve the response speed of the electronic device, and has good compatibility.
The embodiment of the computer device comprises:
the computer device of this embodiment may be an electronic device such as a car recorder or a set-top box, and the computer device includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the processor executes the computer program, the steps of the CPU power consumption management method are implemented.
For example, a computer program may be partitioned into one or more modules that are stored in a memory and executed by a processor to implement the modules of the present invention. One or more of the modules may be a series of computer program instruction segments capable of performing certain functions, which are used to describe the execution of the computer program in the terminal device.
The Processor may be a Central Processing Unit (CPU), or may be other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, a discrete hardware component, or the like. The general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the terminal device and connecting the various parts of the entire terminal device using various interfaces and lines.
The memory may be used to store computer programs and/or modules, and the processor may implement various functions of the terminal device by running or executing the computer programs and/or modules stored in the memory and invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
A computer-readable storage medium:
the computer program stored in the computer device may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, all or part of the flow in the method according to the above embodiment may be implemented by a computer program, which may be stored in a computer readable storage medium and used for implementing the steps of the CPU power consumption management method when being executed by a processor.
Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
Finally, it should be emphasized that the present invention is not limited to the above-described embodiments, for example, the number of CPU cores set for each CPU core cluster or the number of buffers set for each CPU core, etc., and these changes should also be included in the protection scope of the claims of the present invention.

Claims (10)

  1. A CPU power consumption management method, comprising:
    setting a plurality of working states of the CPU core in a switch core wake-up mode: the working states comprise a power-on state, a pre-power-off state, a core power-off state and a cluster power-off state;
    in the switch core wake-up mode: after a target CPU core receives a closing instruction sent by a user mode application program, the target CPU core sets a pre-power-down mark and enters a pre-power-down state, and after a local interrupt wake-up source is closed, the target CPU core enters a core power-down state;
    in the CPU core cluster where the target CPU core is located, after all CPU cores enter a core power-down state, all CPU cores of the cluster enter a cluster power-down state;
    when any CPU core of a CPU core cluster where a target CPU core is located receives a core opening instruction sent by a user mode application program, all CPU cores of the cluster exit from the cluster power-down state to the core power-down state;
    and if the core opening instruction aims at a target CPU core, or a newly generated core opening instruction aiming at the target CPU core occurs, the target CPU core exits from the core power-down state to the power-on state.
  2. 2. The CPU power consumption management method according to claim 1, wherein:
    and after the target CPU core closes the local interrupt wake-up source, the target CPU core carries out context protection operation.
  3. 3. The CPU power consumption management method according to claim 1, wherein:
    and if the core opening instruction is not directed to the target CPU core and no newly-generated core opening instruction directed to the target CPU core occurs, the target CPU core is kept in the core power-down state.
  4. 4. The CPU power consumption management method according to claim 1, wherein:
    the plurality of working states of the CPU core in the switch core wake-up mode are the same as the plurality of working states of the CPU core in the interrupt wake-up mode.
  5. 5. The CPU power consumption management method according to claim 4, wherein:
    in the interrupt wake-up mode: when the time of the target CPU core in the idle state exceeds a preset threshold value, a pre-power-down mark is set, the target CPU core enters the pre-power-down state, and the target CPU core enters the core power-down state;
    in the CPU core cluster where the target CPU core is located, after all CPU cores enter a core power-down state, all CPU cores of the cluster enter the cluster power-down state;
    when any CPU core of a CPU core cluster where a target CPU core is positioned receives an interrupt request, all CPU cores of the cluster exit from the cluster power-down state to the core power-down state;
    if the interrupt request instruction is directed to a target CPU core, or a newly generated interrupt request instruction directed to the target CPU core occurs, the target CPU core exits from the core power-down state to the power-up state.
  6. 6. The CPU power consumption management method according to any one of claims 1 to 5, wherein:
    in the switch core wake-up mode, if the target CPU core is in a cluster power-down state, when receiving an interrupt request instruction, the target CPU core is maintained in the cluster power-down state.
  7. 7. The CPU power consumption management method according to any one of claims 1 to 5, wherein:
    each CPU core in the same CPU core cluster is provided with an independent primary buffer.
  8. 8. The CPU power consumption management method according to claim 7, wherein:
    and a plurality of CPU cores in the same CPU core cluster use the same secondary buffer.
  9. 9. Computer arrangement, characterized in that it comprises a processor and a memory, said memory storing a computer program that, when executed by the processor, carries out the steps of the CPU power consumption management method according to any one of claims 1 to 8.
  10. 10. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program, when executed by a processor, implements the steps of the CPU power consumption management method of any of claims 1 to 8.
CN202111308013.1A 2021-11-05 2021-11-05 CPU power consumption management method, computer device and computer readable storage medium Pending CN114020139A (en)

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