CN114020095B - Dual-processor lock step system based on clock alignment and synchronization - Google Patents
Dual-processor lock step system based on clock alignment and synchronization Download PDFInfo
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- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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Abstract
The invention discloses a clock alignment and synchronization-based dual-processor lock step system, which comprises a main control CPU and a monitoring CPU, wherein the main control CPU and the monitoring CPU are configured as follows: the homologous clock module drives the main control CPU and the monitoring CPU to be powered on and reset simultaneously; setting clock alignment detection points at a Module OS entrance, a MajorFrame beginning and a partition switching beginning respectively, sending time stamps to a main control CPU by a monitoring CPU through a PCIe bus or an Ethernet, comparing by the main control CPU, if the clock drift accumulation of the main control CPU and the monitoring CPU is t and exceeds a threshold value set by the precision requirement, increasing the step length t in a DEC timer interrupt processing function of an operation lead CPU, so that the system time stamps of the main control CPU and the monitoring CPU are aligned and synchronous when the clock is interrupted next time. The invention cancels the synchronous checking hardware of the peripheral extension of the processor and realizes the high integrity requirement of 10 ‑9 stages with lower cost.
Description
Technical Field
The invention belongs to the field of avionic systems, and particularly relates to a clock alignment and synchronization-based double-processor lockstep system, which meets the requirements of civil avionic equipment on high integrity and high reliability.
Background
Based on civil aircraft safety theory, the integrity of core equipment is required to reach 10 -9, and the integrity index of the product is determined by the integrity index of each link of the product architecture and data processing. The integrity index of a single link is based on the basic reliability of the product, and the integrity of the link is improved by increasing the complexity of data verification in the link. Based on the reliability of the current components and the complexity of product design, the basic reliability of the product is generally in the level of 10 -3 to 10 -5, and the improvement of the integrity of a specific link by simply increasing the complexity of a verification algorithm (such as CRC, ECC and the like) can lead to the substantial improvement of the design complexity, and even can not be realized in engineering. Lockstep (Lockstep) is an effective means of addressing the high integrity requirements of avionics as a safety critical technique. Related theories exist in academia, and nowadays, with technological progress, the industry repeatedly and iteratively innovates to form products which are applied to IMA (integrated modular avionics system) of passenger plane projects such as Boeing 777, boeing 787 and the like. The application of the technology has important influence on the improvement of the safety and reliability of the flight and the development of the computer redundancy management technology.
Referring to fig. 1, a typical processor Lockstep framework is shown, and the core is a dual redundancy system composed of two identical processors, in which a Master CPU (Master CPU) is generally designed, and another is a Monitor CPU (Monitor CPU) which is responsible for monitoring the operation of the Master CPU, and in the Lockstep state, the two processors operate the same computing task. A Check component (such as CPLD, FPGA, etc.) is extended from the periphery of the dual processors, the calculation results of the two processors are periodically checked, and if the calculation results are consistent, the main control CPU outputs the calculation results outwards; if an inconsistency is found, indicating a failure, the system is shut down, preventing errors from propagating to the upper layer system. In early foreign countries, the mode is adopted, the design is simple, but the Lockstep detection strategy is imperfect, different hardware circuits are required to be additionally expanded outside the processor for synchronous calibration, the efficiency is low, and the CPU processing capacity is reduced.
With the development of CPU technology, there are also dual-core processors with manufacturer customized lockstep functions, which can make synchronous check at instruction level between dual cores, and can rapidly locate faults and isolate them. The customization instruction level has fine granularity of lock step, can simplify the system design, but needs to have the capability of designing and manufacturing an independent processor chip, has complex design verification and high cost, has small market scale in the field, does not have the willingness of manufacturers to provide the goods shelf products, and is difficult to realize in China at present.
Disclosure of Invention
The invention aims to provide a double-processor lockstep system based on clock alignment and synchronization, which cancels synchronous checking hardware of peripheral extension of a processor, designs internal checking verification of the double processor, remarkably reduces performance reduction caused by lockstep, and can purchase commercial goods shelf products by the processor and realize high-integrity requirement of 10 -9 stages with lower cost.
The invention is realized by the following technical scheme:
the double-processor lock step system based on clock alignment and synchronization comprises a homologous clock module, a main control CPU and a monitoring CPU, wherein the main control CPU and the monitoring CPU are configured as follows:
a) The phase-locked loop module of the main control CPU and the monitoring CPU is connected with the homologous clock module, so that the homologous clock module drives the main control CPU and the monitoring CPU to be powered on and reset simultaneously;
b) The main control CPU and the monitoring CPU run VxWorks 653 operating systems, and a first clock alignment detection point is set at a Module OS entrance so that the main control CPU and the monitoring CPU enter the Module OS simultaneously;
c) Setting a clock alignment detection point at the beginning of each Major Frame period, so that a main control CPU and a monitoring CPU start a new round of partition scheduling at the same time each time; wherein, the Major Frame is a main time Frame scheduled by VxWorks 653, and the first partition of the Major Frame is designed as a null (spark) partition;
d) Setting a clock alignment detection point again at the partition switching start position in the Major Frame period, so that the main control CPU and the monitoring CPU start partition switching each time simultaneously;
e) And at each clock alignment detection point, the monitoring CPU sends a time stamp to the main control CPU through a PCIe bus or an Ethernet, the main control CPU performs comparison, and if the clock drift accumulation of the main control CPU and the monitoring CPU is t and exceeds a threshold value set by the precision requirement, the step length t is increased in a DEC timer interrupt processing function of the running advanced CPU, so that the system time stamps of the main control CPU and the monitoring CPU are aligned and synchronized when the clock is interrupted next time.
Preferably, the homologous clock module comprises a homologous clock crystal oscillator and a clock buffer, the homologous clock crystal oscillator ensures synchronous reset of the master control CPU and the monitoring CPU by monitoring reset output of two paths of watchdog and a power state indication signal, and ensures clock consistency of the two CPUs by the clock buffer.
Compared with the prior proposal, the invention has the beneficial effects that:
a) Due to the adoption of the design of the homologous clock module, the consistency of the initial states of the processor cores at the two sides can be ensured, meanwhile, in order to eliminate the accumulated errors of the fine differences of the core clocks at the two sides, the module can periodically output synchronous signals to the processor, and the VxWorks 653 system clock interrupt is utilized to finish the periodic correction of the operation errors of the two paths of processors, so that the continuous consistency of the data processing at the two sides is ensured.
B) Because the peripheral synchronous calibration component is cancelled, the calibration verification is carried out on the main control CPU side, compared with an external FPGA component, the design is greatly simplified, the performance loss is reduced, the synchronous precision can be controlled through the clock aligned threshold value, different high-integrity application scenes can be met, and the comprehensive efficiency of the system is improved.
Drawings
FIG. 1 is a lockstep frame of a conventional, typical processor.
Fig. 2 is a schematic diagram of a dual processor lockstep system based on clock alignment and synchronization according to the present embodiment.
Fig. 3 is a VxWorks 653 software framework.
Fig. 4 is an application example of a dual processor lockstep system based on clock alignment and synchronization.
FIG. 5 is a timing diagram of a clock alignment detection point.
Fig. 6 is a clock alignment schematic.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
As shown in fig. 2, the dual processor lockstep system based on clock alignment and synchronization in this embodiment includes a homologous clock module, a master CPU, and a monitor CPU, where the homologous clock module is used as a core clock source of the master CPU and the monitor CPU, and provides a core clock, homologous reset, and synchronous operation trigger source for the master CPU and the monitor CPU. The homologous clock module comprises a homologous clock crystal oscillator and a clock buffer, wherein the homologous clock crystal oscillator ensures synchronous reset of the master control CPU and the monitoring CPU by monitoring reset output of two paths of watchdog and a power state indication signal. The homologous clock module ensures the clock consistency of the master control CPU and the monitoring CPU through the clock buffer. Through the measures, the consistency of the initial states of the two paths of CPU channels is ensured.
In contrast to the illustration of fig. 1, this embodiment employs a homologous clock module, which differs from fig. 1 in that the peripheral synchronization proofing component is eliminated. The main control CPU and the monitoring CPU can exchange data through PCIe bus or Ethernet. By combining the same-source input clock and the clock alignment design based on the time-sharing partition operating system, the verification of the calculation results of the double processors can be completed at the main control CPU end, so that the complexity of hardware design can be greatly reduced, and the performance loss of the processors can be reduced.
The core of the lock step of the dual processor is the checking and verifying of the data at the two sides, and the premise of the checking and verifying is to ensure that the data at the two sides has comparability, eliminate the false alarm caused by the inconsistency of the data at the upper period and the data at the lower period, and the key is that the core clocks at the two sides can ensure the alignment synchronization. The homologous clock module provides the consistency of the kernel input clock and the initial state for two paths of processor channels of the main control CPU and the monitoring CPU. The difference of clock paths and phase-locked loops of the master control CPU and the monitoring CPU may cause subtle differences of working clocks, and the subtle differences may accumulate more than one or a plurality of instruction working periods after the CPU core runs for a long time, so that data calibration between the master control CPU and the monitoring CPU is not comparable. Therefore, the key design of the invention is that the core clocks of the main control CPU and the monitoring CPU must be periodically detected, if the clock drift of the main control CPU and the monitoring CPU exceeds a certain threshold value, the clock calibration of the core running in advance is needed, and the clock synchronization is realized by aligning the cores of the two CPUs again similar to the clock of the slow-down running clock. To achieve this, it is desirable to combine the time-sharing partition characteristics of the processor core clock timer and the operating system.
In the embodiment, a VxWorks 653 time-sharing partition operating system is operated on a processor, a main control CPU and a monitoring CPU are driven by a homologous clock module to be started simultaneously, and the same task application is operated. VxWorks 653 is a time-division partition operating system that meets the ARINC 653 standard. ARINC 653 is an industry standard in the field of international on-board real-time operating systems, and both civilian and military aircraft use real-time operating systems that meet the ARINC 653 standard.
As shown in fig. 3, the software running the VxWorks 653 operating system is divided into MOS (Module OS), POS (Partition OS), partition Application layers. Each Application is combined with a POS to form a partition Application, and is isolated from other partitions in address space and running time. The Module OS is responsible for the running schedule for all partitions. The invention is to adopt three layers of Check points to ensure the alignment and synchronization of the core clocks of the main control CPU and the monitoring CPU. Firstly, the clock interruption of the VxWorks 653 operating system is correlated through an external synchronous trigger source, so that the consistency of the scheduling period and the phase of the operating system is ensured; secondly, designing an empty partition (Spare Partiton), sequencing the empty partition on the head of all partitions, aligning the core clocks of a main control CPU and a monitoring CPU when each scheduling period starts, and ensuring that the task time slices of the other partitions are not occupied by the existence of the empty partition; thirdly, when one Partition time slice is finished and the next Partition operation, namely Partition switching (Partition Switch), clock alignment is performed again, so that consistency of Partition operation time sequences on a main control CPU and a monitoring CPU can be guaranteed, and comparability of data proofreading on two sides can be guaranteed.
To realize alignment synchronization of kernel clocks at two sides of a main control CPU and a monitoring CPU, how to apply VxWorks 653 to the correlation of the clock interrupt of an operating system and a kernel clock timer of a processor is studied. Modern processor cores typically have a number of clock timers with different functions, such as TB (Time Base), DEC (Decrementer). The TB timer is driven by the phase-locked loop module, providing a reference clock period (Tick) for the core instruction to run, and the DEC timer is typically used as a down counter for operating system clock interrupts. In the invention, when Check Point is detected, if clock difference accumulation of a main control CPU and a monitoring CPU exceeds a threshold value, the clock of one side which runs fast is slowed down to wait for the other side by modifying the step length of the VxWorks 653 system clock interruption, so that alignment is realized, and clocks of two sides are synchronized again.
An application of a dual processor lockstep system based on clock alignment and synchronization is illustrated below.
Referring to fig. 4, the master control CPU and the monitor CPU adopt P2010 CPUs of fliskal corporation, and the homologous clock module is composed of a crystal oscillator and a CPLD clock Buffer, and provides a clock input source. The main control CPU and the monitoring CPU conduct data checking through a PCIe bus or an Ethernet communication mode. Unlike fig. 2, this embodiment uses avionics ethernet (AFDX, avionics Full Duplex SWITCHED EHERNET) for data interaction with external system devices according to project real-world needs. The AFDX terminal is realized by using an FPGA design based on ARINC664 standard. As shown in fig. 4, the a664 terminals are hung on the P2010 CPU through PCIe, the a664 terminals on both sides also use synchronous clocks to ensure the same input frequency, and data proofreading between the terminals is performed through the SPI bus. After the key data are synchronously processed by the processors at the two sides, firstly performing calibration on the main control CPU, sending the calibration to the A664 terminals if the key data are consistent, finishing calibration again by the two A664 terminals after the logic processing is finished, and sending the calibration to other devices if the key data are consistent through the A664 network; if the proofreading is inconsistent, the frame data is discarded to prevent the fault from spreading.
Referring to fig. 5, the timing design of the clock alignment detection Point Check Point in the present embodiment is shown, and the configuration of the master CPU and the monitor CPU is as follows:
And 1, the phase-locked loop module of the main control CPU and the monitoring CPU is connected with the homologous clock module, so that the homologous clock module drives the main control CPU and the monitoring CPU to be simultaneously powered on and reset. When the hardware is designed, the core clocks of the two processors, the reference clock of the DDR controller and the working clock of the CPLD are all generated by the same crystal oscillator excitation, so that the two CPUs can enter the power-on reset instruction at the same time.
2, The main control CPU and the monitoring CPU run VxWorks 653 operating systems, and a first clock alignment detection point is set at a Module OS entrance, so that the main control CPU and the monitoring CPU enter the Module OS simultaneously.
And 3, setting a clock alignment detection point at the beginning of each Major Frame period, so that the main control CPU and the monitoring CPU start a new round of partition scheduling at the same time each time. The Major Frame is a main time Frame scheduled by VxWorks 653, the first partition of the Major Frame is designed as a space partition, as shown in fig. 6, and a clock alignment detection point is set at the start of the spark partition, so as to ensure that two CPUs synchronously enter the Major Frame.
4, Performing clock alignment detection again at the beginning of partition switching in the Major Frame, and enabling the main control CPU and the monitoring CPU to start partition switching each time simultaneously as shown in fig. 6.
And (5) performing DATA CHECK at the end of application partition, and sending the consistency to the A664 terminal.
The 6A664 terminal outputs DATA CHECK again when outputting, and outputs to the outside.
At each clock alignment detection point, the monitoring CPU sends a signal to the main control CPU through a PCIe bus or Ethernet, and the main control CPU detects the signal. Fig. 6 is an illustration of clock alignment at Check Point. If at the beginning of Major Framek, the clock drift of the main control CPU and the monitoring CPU is detected to accumulate as t and exceed the threshold value set by the precision requirement, the main control CPU is currently running ahead, the step length t is increased in the interrupt processing function of the DEC timer of the main control CPU, which is equivalent to the step length of slow core clock shifting, and when the clock drift of the two CPUs is controlled to be within the precision requirement range to MajorFrame next time, the purpose of clock alignment and synchronization is achieved.
The dual processor lockstep system based on clock alignment and synchronization provided by the embodiment realizes, for example, a comprehensive modularized avionics system. The design method greatly enriches the lock-step technology implementation form with high integrity requirements. The application of the invention is independent of a hardware platform, has wide application range and obvious market prospect and economic benefit.
In summary, the preferred embodiments of the present invention are not intended to limit the scope of the present invention, but all equivalent variations and modifications in shape, construction, characteristics and spirit according to the scope of the claims should be included in the scope of the claims.
Claims (2)
1. The utility model provides a dual processor lockstep system based on clock alignment and synchronization, contains homologous clock module, master control CPU, its characterized in that: the configuration of the main control CPU and the monitoring CPU is as follows:
a) The phase-locked loop module of the main control CPU and the monitoring CPU is connected with the homologous clock module, so that the homologous clock module drives the main control CPU and the monitoring CPU to be powered on and reset simultaneously;
b) The main control CPU and the monitoring CPU run VxWorks 653 operating systems, and a first clock alignment detection point is set at a Module OS entrance so that the main control CPU and the monitoring CPU enter the Module OS simultaneously;
c) Setting a clock alignment detection point at the beginning of each Major Frame period, so that a main control CPU and a monitoring CPU start a new round of partition scheduling at the same time each time; the method comprises the steps that a Major Frame is a main time Frame scheduled by VxWorks 653, and a first partition of the Major Frame is designed to be a space partition;
d) Setting a clock alignment detection point again at the partition switching start position in the Major Frame period, so that the main control CPU and the monitoring CPU start partition switching each time simultaneously;
e) And at each clock alignment detection point, the monitoring CPU sends a time stamp to the main control CPU through a PCIe bus or an Ethernet, the main control CPU performs comparison, and if the clock drift accumulation of the main control CPU and the monitoring CPU is t and exceeds a threshold value set by the precision requirement, the step length t is increased in a DEC timer interrupt processing function of the running advanced CPU, so that the system time stamps of the main control CPU and the monitoring CPU are aligned and synchronized when the clock is interrupted next time.
2. The dual processor lockstep system based on clock alignment and synchronization of claim 1, wherein the homologous clock module comprises a homologous clock crystal oscillator and a clock buffer, the homologous clock crystal oscillator ensures synchronous reset of the master control CPU and the monitor CPU by monitoring reset output of two paths of watchdog and a power state indication signal, and ensures clock consistency of the outputs to the two CPUs by the clock buffer.
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| US8156371B2 (en) * | 2009-06-16 | 2012-04-10 | Honeywell International Inc. | Clock and reset synchronization of high-integrity lockstep self-checking pairs |
| US10946866B2 (en) * | 2018-03-31 | 2021-03-16 | Intel Corporation | Core tightly coupled lockstep for high functional safety |
| CN113253796B (en) * | 2021-07-01 | 2021-10-08 | 北京智芯微电子科技有限公司 | Asynchronous input signal synchronization method and device, central processing unit and chip |
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| "Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems";Emre Ozer等;《2018 51st Annual IEEE/ACM International Symposium on Microarchitecture》;20181213;全文 * |
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