CN114005862A

CN114005862A - Array substrate, display panel and display device

Info

Publication number: CN114005862A
Application number: CN202111277592.8A
Authority: CN
Inventors: 郑启涛; 张立涛; 张金方; 韩珍珍
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2022-02-01

Abstract

The embodiment of the application provides an array substrate, display panel and display device, array substrate have the display area and lie in the non-display area of display area week side, and array substrate includes: a substrate; the data module is arranged on the substrate and positioned in the non-display area, and comprises a plurality of data fanout lines; the clock module is positioned in the non-display area and is stacked with the data module along the thickness direction of the array substrate, and the clock module comprises a plurality of clock signal lines; the orthographic projection of the data module on the substrate and the orthographic projection of the clock module on the substrate at least partially overlap. The data module and the clock module are stacked in the thickness direction, and at least part of orthographic projection of the data module on the substrate and at least part of orthographic projection of the clock module on the substrate are overlapped, so that the size of a non-display area occupied by the data module and the clock module can be reduced, the size of a frame is further reduced, and the problem of wider frames in the display panel can be solved.

Description

Array substrate, display panel and display device

Technical Field

The application relates to the technical field of display equipment, in particular to an array substrate, a display panel and a display device.

Background

Organic Light-Emitting diodes (OLEDs) are active Light-Emitting devices. Compared with the traditional Liquid Crystal Display (LCD) Display mode, the OLED Display technology does not need a backlight lamp and has the self-luminous characteristic. The OLED adopts a thin organic material film layer and a glass substrate, and when a current flows, the organic material can emit light. Therefore, the OLED display panel can save electric energy remarkably, can be made lighter and thinner, can endure a wider range of temperature variation than the LCD display panel, and has a larger visual angle. The OLED display panel is expected to become a next-generation flat panel display technology following the LCD, and is one of the technologies that receives the most attention among the flat panel display technologies at present.

The OLED display panel needs to drive each sub-pixel, and generally, the OLED display panel includes a scan line and a data line, where a signal is input to the sub-pixel in the same row through the scan line, and a data signal is input to the sub-pixel in the same column through the data line, and when the sub-pixel receives a signal input from both the scan line and the data line, the sub-pixel can emit light. Because each row is correspondingly provided with a scanning line, and each column is correspondingly provided with a data line, the number of signal lines in the OLED display panel is large, and the narrow frame is difficult to realize.

Disclosure of Invention

The embodiment of the application provides an array substrate, a display panel and a display device, and aims to solve the problem that a frame in the display panel is wide.

An embodiment of a first aspect of the present application provides an array substrate, the array substrate has a display area and a non-display area located on a peripheral side of the display area, and the array substrate includes: a substrate; the data module is arranged on the substrate and positioned in the non-display area, and comprises a plurality of data fanout lines; the clock module is positioned in the non-display area and is stacked with the data module along the thickness direction of the array substrate, and the clock module comprises a plurality of clock signal lines; the orthographic projection of the data module on the substrate and the orthographic projection of the clock module on the substrate at least partially overlap.

According to an embodiment of the first aspect of the present application, the orthographic projection of the clock module on the substrate is located within the orthographic projection of the data module on the substrate.

According to any one of the embodiments of the first aspect of the present application, the array substrate includes two or more conductive layers disposed on the substrate and stacked in a thickness direction of the array substrate, and the plurality of data fanout lines are disposed in the two or more conductive layers.

According to any of the foregoing embodiments of the first aspect of the present application, the plurality of data fanout lines are located in two or more adjacent conductive layers, the plurality of clock signal lines are located in the same conductive layer, and the conductive layer where the plurality of clock signal lines are located is located on a side of the conductive layer where the plurality of data fanout lines are located, the side facing toward or away from the substrate.

According to any one of the foregoing embodiments of the first aspect of the present application, the display device further includes data lines located in the display area, the data lines are connected to the data fanout lines in a one-to-one correspondence, and the data fanout lines connected to two adjacent data lines are located in different conductive layers.

According to any one of the preceding embodiments of the first aspect of the present application, the data lines are formed to extend along the first direction, and the data module and the clock module are located on one side of the display area in the first direction.

According to any one of the previous embodiments of the first aspect of the present application, the scanning line is formed to extend along a second direction, and the second direction intersects with the first direction;

the two data modules and the two clock modules are equally distributed on two sides of the non-display area in the second direction.

According to any one of the foregoing embodiments of the first aspect of the present application, the display area includes a first sub-display area and a second sub-display area distributed along the second direction, the data line in the first sub-display area is connected to the data module located on a side of the first sub-display area facing away from the second sub-display area, the scan line in the first sub-display area is connected to the clock module located on a side of the first sub-display area facing away from the second sub-display area, the data line in the second sub-display area is connected to the data module located on a side of the second sub-display area facing away from the first sub-display area, and the scan line in the second sub-display area is connected to the clock module located on a side of the second sub-display area facing away from the first sub-display area.

According to any of the preceding embodiments of the first aspect of the present application, the first sub-display area and the second sub-display area are equal in area.

According to any of the preceding embodiments of the first aspect of the present application, the two or more conductive layers comprise: the first conductive layer comprises a shielding line positioned in the display area and a part of data fanning-out line positioned in the non-display area.

According to any of the embodiments of the first aspect of the present application, the two or more conductive layers further include a second conductive layer located on a side of the first conductive layer away from the substrate, and the plurality of data fanout lines are respectively disposed on the first conductive layer and the second conductive layer.

According to any of the foregoing embodiments of the first aspect of the present application, the two or more conductive layers further include a third conductive layer located on a side of the second conductive layer away from the substrate, and the plurality of data fanout lines are respectively disposed on the first conductive layer, the second conductive layer, and the third conductive layer.

According to any of the preceding embodiments of the first aspect of the present application, the two or more conductive layers further include a fourth conductive layer located on a side of the third conductive layer facing away from the substrate, and the plurality of clock signal lines are located on the fourth conductive layer.

According to any of the preceding embodiments of the first aspect of the present application, there is a first gap between adjacent data fanout lines, and at least part of the orthographic projection of the clock signal line on the substrate and the orthographic projection of the first gap on the substrate at least partially overlap.

According to any one of the preceding embodiments of the first aspect of the present application, a second gap exists between two adjacent clock signal lines, and a width of the second gap is greater than a width of the first gap.

Embodiments of the second aspect of the present application further provide a display panel, including the array substrate of any of the embodiments of the first aspect.

Embodiments of the third aspect of the present application further provide a display device, including the display panel of the embodiments of the second aspect.

In the array substrate provided by the embodiment of the application, the array substrate comprises a substrate, and a data module and a clock module which are arranged on the substrate. The data module and the clock module are both positioned in the non-display area. The data module comprises a plurality of data fan-out lines for transmitting data driving signals to the display area through the data fan-out lines. The clock module includes a plurality of clock signal lines to transmit clock driving signals to the display region through the clock signal lines. The data module and the clock module are stacked in the thickness direction, and at least part of orthographic projection of the data module on the substrate and at least part of orthographic projection of the clock module on the substrate are overlapped, so that the size of a non-display area occupied by the data module and the clock module can be reduced, the size of a frame is further reduced, and the problem of wider frames in the display panel can be solved.

Drawings

Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like or similar reference characters identify the same or similar features.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application;

FIG. 2 is a schematic view of a portion of the enlarged structure at I in FIG. 1;

FIG. 3 is a cross-sectional view taken at A-A of FIG. 1;

fig. 4 is a schematic structural diagram of an array substrate according to another embodiment of the first aspect of the present application;

fig. 5 is a schematic structural diagram of an array substrate according to yet another embodiment of the present disclosure;

FIG. 6 is a cross-sectional view taken at A-A of FIG. 1 in another embodiment of the first aspect of the present application;

fig. 7 is a cross-sectional view taken at a-a of fig. 1 in yet another embodiment of the first aspect of the present application.

Description of reference numerals:

10. an array substrate;

100. a substrate;

200. a data module; 210. a data fanout line;

300. a clock module; 310. a clock signal line;

400. a conductive layer; 410. a first conductive layer; 420. a second conductive layer; 430. a third conductive layer; 440. a fourth conductive layer;

500. a data line;

600. scanning a line;

700. a drive circuit; 710. a thin film transistor; 711. a semiconductor layer;

800. a shift register;

900. shielding the wire;

AA. A display area; AA1, first sub-display area; AA2, second sub-display area; NA, non-display area; y, a first direction; x, a second direction; z, thickness direction.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the dimensions of some of the structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the description of the present application, it is to be noted that, unless otherwise specified, "a plurality" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," and the like, indicate an orientation or positional relationship that is merely for convenience in describing the application and to simplify the description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

The directional terms appearing in the following description are directions shown in the drawings and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be directly connected or indirectly connected. The specific meaning of the above terms in the present application can be understood as appropriate by one of ordinary skill in the art.

For better understanding of the present application, the array substrate, the display panel and the display device according to the embodiments of the present application are described in detail below with reference to fig. 1 to 7.

Referring to fig. 1 to fig. 3, fig. 1 is a schematic structural diagram of an array substrate 10 according to an embodiment of the first aspect of the present disclosure. Fig. 2 is a schematic view of a partially enlarged structure at I in fig. 1. Fig. 3 is a cross-sectional view at a-a in fig. 1.

As shown in fig. 1 to 3, the array substrate 10 has a display area AA and a non-display area NA located at a peripheral side of the display area AA, and the array substrate 10 includes: a substrate 100; a data module 200 disposed on the substrate 100 and located in the non-display area NA, the data module 200 including a plurality of data fanout lines 210; the clock module 300 is located in the non-display area NA and is stacked with the data module 200 along the thickness direction Z of the array substrate 10, and the clock module 300 includes a plurality of clock signal lines 310; the orthographic projection of the data module 200 on the substrate 100 and the orthographic projection of the clock module 300 on the substrate 100 at least partially overlap.

The data module 200 and the clock module 300 are enclosed by dashed lines in fig. 1 and 2, and the dashed lines do not form a structural limitation of the array substrate 10 according to the embodiment of the present application. Some of the data fanout lines 210 in fig. 1 and 2 are not shown because they are on the bottom layer. The relative position relationship between a portion of the data fanout line 210 and the clock signal line 310 is illustrated in fig. 1 and 2, and does not indicate that the data fanout line 210 and the clock signal line 310 are located in the same layer.

In the array substrate 10 provided in the embodiment of the present application, the array substrate 10 includes a substrate 100, and a data module 200 and a clock module 300 disposed on the substrate 100. The data module 200 and the clock module 300 are both located in the non-display area NA. The data module 200 includes a plurality of data fanout lines 210 to transmit data driving signals to the display area AA through the data fanout lines 210. The clock module 300 includes a plurality of clock signal lines 310 to supply clock driving signals to the display area AA through the clock signal lines 310. The data module 200 and the clock module 300 are stacked in the thickness direction Z, and the orthographic projection of the data module 200 on the substrate 100 and the orthographic projection of the clock module 300 on the substrate 100 are at least partially overlapped, so that the size of a non-display area NA occupied by the data module 200 and the clock module 300 can be reduced, the size of a frame is reduced, and the problem of wider frame in a display panel can be solved.

In some alternative embodiments, continuing to refer to fig. 1 and 2, the orthographic projection of the clock module 300 on the substrate 100 is within the orthographic projection of the data module 200 on the substrate 100. I.e. the dashed box in fig. 1 and 2 in which the clock module 300 is located within the dashed box in which the data module 200 is located.

Generally, the number of clock signal lines 310 is smaller than the number of data fanout lines 210, and thus the size of the data module 200 is larger than that of the clock module 300. In these alternative embodiments, the orthographic projection of the clock module 300 on the substrate 100 is arranged in the orthographic projection of the data module 200 on the substrate 100, so that the space occupied by the clock module 300 and the data module 200 can be further reduced, and the size of the frame can be reduced.

In the embodiment of the present application, the data module 200 refers to a module including the data fanout line 210, and specifically may refer to a layer structure of a region where the data fanout line 210 is located and the data fanout line 210, for example, please refer to fig. 2 continuously, the data module 200 may further include a first gap d1 between two adjacent data fanout lines 210, and the data module 200 may further include a conductive layer 400 where the data fanout line 210 is located and an insulating layer between two adjacent data fanout lines 210.

In the embodiment of the present application, the clock module 300 refers to a module including the clock signal line 310, and may specifically refer to the layer structure of the region where the clock signal line 310 is located and the clock signal line 310, for example, please continue to refer to fig. 2, and the clock module 300 may further include a second gap d2 between two adjacent clock signal lines 310.

In some alternative embodiments, the width of the second gap d2 is greater than the width of the first gap d 1. The width of the second gap d2 refers to the distance between two adjacent clock signal lines 310, and the width of the first gap d1 refers to the distance between two adjacent data fanout lines 210. When the width of the second gap d2 is greater than the width of the first gap d1, the distance between two adjacent clock signal lines 310 is greater, so that on one hand, the parasitic capacitance formed between two adjacent clock signal lines 310 can be improved, and the stability of signal transmission on the clock signal lines 310 can be improved.

In some alternative embodiments, continuing to refer to fig. 1 and 2, at least a portion of the orthographic projection of the clock signal line 310 on the substrate 100 and the orthographic projection of the first gap d1 on the substrate 100 at least partially overlap. The stacking area of the data fanout line 210 and the clock signal line 310 can be reduced, and the parasitic capacitance generated thereby can be reduced, improving the stability of signal transmission.

Optionally, the orthographic projection of the clock signal line 310 on the substrate 100 is located within the orthographic projection of the first gap d1 on the substrate 100, that is, the clock signal line 310 and the data fanout line 210 are completely misaligned, so that the stacking area of the data fanout line 210 and the clock signal line 310 can be further reduced, the parasitic capacitance generated thereby can be reduced, and the stability of signal transmission can be improved.

In some alternative embodiments, referring to fig. 3, the array substrate 10 includes two or more conductive layers 400 disposed on the substrate 100 and stacked along the thickness direction Z of the array substrate 10, and the plurality of data fanout lines 210 are disposed in the two or more conductive layers 400.

In these alternative embodiments, the plurality of data fanout lines 210 are disposed in more than two conductive layers 400, so that the number of the data fanout lines 210 in the same conductive layer 400 can be reduced, the space occupied by the data fanout lines 210 in the conductive layer 400 is further reduced, and the size of the frame is further reduced.

Optionally, referring to fig. 3, the data fanout lines 210 are located in two or more adjacent conductive layers 400, the clock signal lines 310 are located in the same conductive layer 400, and the conductive layer 400 where the clock signal lines 310 are located is located on a side of the conductive layer 400 where the data fanout lines 210 are located, the side facing or deviating from the substrate 100.

In these alternative embodiments, the data fanout line 210 is disposed adjacent to two or more conductive layers 400, and the clock signal line 310 is disposed on one side of the conductive layer 400 where the data fanout line 210 is disposed. The two or more conductive layers 400 where the data fanout line 210 is located are adjacent to each other, so that the crossing between the data fanout line 210 and the clock signal line 310 can be reduced, the length of the data fanout line 210 can be shortened, and the wiring of the array substrate 10 can be simplified.

In some alternative embodiments, referring to fig. 1 to fig. 3, the array substrate 10 further includes data lines 500 located in the display area AA, the data lines 500 are connected to the data fanout lines 210 in a one-to-one correspondence, and the data fanout lines 210 connected to two adjacent data lines 500 are located in different conductive layers 400. In fig. 1 and 2, since some of the data fanout lines 210 are located at the bottom layer, the connection relationship of all the data lines 500 and the data fanout lines 210 is not shown.

In these alternative embodiments, the data fanout lines 210 connected to two adjacent data lines 500 are located in different conductive layers 400, so that the distance between the data lines 500 and the data fanout lines 210 connected thereto can be reduced, the wiring distance is further reduced, and the wiring of the array substrate 10 is simplified.

Optionally, with reference to fig. 1, the column substrate further includes a plurality of driving circuits 700 arranged in rows and columns, and each driving circuit 700 is used for driving each sub-pixel to display. The driving circuits 700 of the same column are used to connect to the same data line 500. For example, the column direction is the first direction Y and the row direction is the second direction X. The data line 500 is extended and formed in the first direction Y. Optionally, the array substrate 10 further includes a scan line 600 extending along the second direction X, and the same scan line 600 is used for connecting a plurality of driving circuits 700 located in the same row.

In some alternative embodiments, with continued reference to fig. 1 and fig. 2, the data module 200 and the clock module 300 are located at one side of the display area AA in the first direction Y. The distance between the data module 200 and the data line 500 can be reduced, and the end of the data line 500 extending along the first direction Y is directly connected to the data fanout line 210 in the data module 200, so that the data line 500 does not need to be wound to one side of the display area AA in the second direction X to be connected to the data fanout line 210, and the wiring structure of the array substrate 10 can be simplified.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an array substrate 10 according to another embodiment of the first aspect of the present application.

In some alternative embodiments, as shown in fig. 4, two data modules 200 and two clock modules 300 are provided, and the two data modules 200 and the two clock modules 300 are respectively disposed on two sides of the non-display area NA in the second direction X.

In these alternative embodiments, first, the two data modules 200 and the clock module 300 are respectively disposed at both sides of the non-display area NA in the second direction X, and a gap can be formed between the two clock modules 300 and the data modules 200, and the gap can be disposed with other conductive lines such as voltage signal lines. In addition, two clock modules 300 are provided, and the two clock modules 300 can transmit signals to the scan lines 600 from two sides of the display area AA in the second direction X, so as to implement dual-edge driving.

In some alternative embodiments, please continue to refer to fig. 4, the display area AA includes a first sub-display area AA1 and a second sub-display area AA2 distributed along the second direction X, the data line 500 in the first sub-display area AA1 is connected to the data module 200 located at a side of the first sub-display area AA1 away from the second sub-display area AA2, the scan line 600 in the first sub-display area AA1 is connected to the clock module 300 located at a side of the first sub-display area AA1 away from the second sub-display area AA2, the data line 500 in the second sub-display area AA2 is connected to the data module 200 located at a side of the second sub-display area AA2 away from the first sub-display area AA1, and the scan line 600 in the second sub-display area AA2 is connected to the clock module 300 located at a side of the second sub-display area AA2 away from the first sub-display area AA 1.

That is, the data line 500 in the first sub-display area AA1 is connected to the data module 200 at the left side of the view direction shown in fig. 4, and the scan line 600 in the first sub-display area AA1 is connected to the clock module 300 at the left side of the view direction shown in fig. 4. The data lines 500 in the second sub-display area AA2 are connected to the data module 200 at the right side of the view shown in fig. 4, and the scan lines 600 in the second sub-display area AA2 are connected to the clock module 300 at the right side of the view shown in fig. 4. The distance between the data line 500 and the data fanout line 210 connected thereto can be further reduced, and the wiring distance can be shortened. The distance between the clock module 300 and the scan line 600 can be reduced. Fig. 4 illustrates a boundary between the first sub-display area AA1 and the second sub-display area AA2 by a dotted line, which is not sufficient to limit the structure of the array substrate 10 according to the embodiment of the present disclosure.

Alternatively, with continued reference to fig. 4, the areas of the first sub-display area AA1 and the second sub-display area AA2 are equal. The number of the driving circuits 700 and the number of the data lines 500 provided in the first sub-display area AA1 and the second sub-pixel area are equal, so that the wirings of the array substrate 10 can be symmetrically provided, and the wirings of the array substrate 10 are simplified.

Optionally, referring to fig. 4, two scan lines 600 are disposed in the same row, wherein one scan line 600 is located in the first sub-display area AA1 and is used for transmitting signals to the driving circuit 700 located in the first sub-display area AA1, and the other scan line 600 is located in the second sub-display area AA2 and is used for transmitting signals to the driving circuit 700 located in the second sub-display area AA 2. With this arrangement, the extension path of the same scanning line 600 can be shortened, and signal transmission can be accelerated.

Referring to fig. 5, fig. 5 is a schematic structural diagram of an array substrate 10 according to another embodiment of the present disclosure.

In some optional embodiments, as shown in fig. 5, the array substrate 10 further includes a shift register 800, the shift register 800 is disposed on at least one side of the display area AA in the second direction X, the scan line 600 is connected to one end of the shift register 800, the clock signal line 310 is connected to the other end of the shift register 800, and the clock signal line 310 transmits signals to the scan line 600 through the shift register 800.

Optionally, referring to fig. 5, a plurality of shift registers 800 are provided, the plurality of shift registers 800 are respectively disposed on two sides of the display area AA in the second direction X, and one or more shift registers 800 located on the same side of the display area AA are connected to a plurality of clock signal lines 310 of the same clock module 300.

Referring to fig. 1 and 6, fig. 6 is a cross-sectional view taken along line a-a of fig. 1 in another embodiment of the first aspect of the present application.

In some alternative embodiments, as shown in fig. 6, two or more conductive layers 400 include: the first conductive layer 410 includes a shielding line 900 located in the display area AA and a portion of the data fanout line 210 located in the non-display area NA. In these embodiments, the first conductive layer 410 is provided with both the shielding line 900 and the data fanout line 210, which does not increase the thickness of the array substrate 10.

In some alternative embodiments, with reference to fig. 6, the driving circuit 700 includes a thin film transistor 710, the thin film transistor 710 includes a semiconductor layer 711, the shielding line 900 is located on a side of the semiconductor layer 711 facing the substrate 100, and the shielding line 900 is used for shielding light incident from the substrate 100 to the semiconductor layer 711, so as to improve a lifetime of the thin film transistor 710.

In some optional embodiments, referring to fig. 6, the two or more conductive layers 400 further include a second conductive layer 420 located on a side of the first conductive layer 410 away from the substrate 100, and the plurality of data fanout lines 210 are separately disposed on the first conductive layer 410 and the second conductive layer 420, so that a size of a space occupied by the plurality of data fanout lines 210 can be reduced, and a size of a non-display area NA can be reduced.

Optionally, referring to fig. 6, the clock module 300 is located on a side of the second conductive layer 420 away from the substrate 100, so that the first conductive layer 410 and the second conductive layer 420 for disposing the data fanout line 210 can be disposed adjacently, and the wiring of the array substrate 10 is simplified.

Referring to fig. 7, fig. 7 is a cross-sectional view taken along line a-a of fig. 1 in yet another embodiment of the first aspect of the present application.

In some optional embodiments, as shown in fig. 7, two or more of the conductive layers 400 further include a third conductive layer 430 located on a side of the second conductive layer 420 facing away from the substrate 100, and the data fanout lines 210 are respectively disposed on the first conductive layer 410, the second conductive layer 420 and the third conductive layer 430. The size of the space occupied by the plurality of data fanout lines 210 can be further reduced, and the size of the non-display area NA can be reduced.

Referring to fig. 7, when the array substrate 10 includes the third conductive layer 430, the clock module 300 is located on a side of the third conductive layer 430 away from the substrate 100, so that the first conductive layer 410, the second conductive layer 420 and the third conductive layer 430 for disposing the data fanout line 210 can be disposed adjacently, thereby simplifying the wiring of the array substrate 10.

With reference to fig. 7, the two or more conductive layers 400 further include a fourth conductive layer 440 disposed on a side of the third conductive layer 430 facing away from the substrate, and the plurality of clock signal lines 310 are disposed on the fourth conductive layer 440.

In these alternative embodiments, the data fanout line 210 is located at the adjacent first, second, and third

conductive layers

410, 420, and 430, which can simplify the wiring complexity. The clock signal line 310 is located at 440 farthest from the substrate 100, and the clock signal line 310 and the data fanout line 210 are located at different conductive layers 400, so that the size of the non-display area NA can be reduced, and a narrow bezel design can be realized.

Optionally, the non-display area NA further includes a pad (not shown in the figure), the pad is located on a side of the data module 200 and the clock module 300 away from the display area AA, the pad includes a data pad and a clock pad, and the data pad is used for connecting the data fanout line 210, so that the data fanout line 210 can be electrically connected with the outside through the data pad. The clock pad is used to connect the clock signal line 310 so that the clock signal line 310 can be electrically connected to the outside through the clock pad.

Embodiments of the second aspect of the present application further provide a display panel, including the array substrate 10 of any of the embodiments of the first aspect. Since the display panel of the embodiment of the present application includes the array substrate 10, the display panel of the embodiment of the present application has the beneficial effects of the array substrate 10, and details are not repeated herein.

Embodiments of the third aspect of the present application further provide a display device, including the display panel described above. The display device in the embodiment of the present invention includes, but is not limited to, a mobile phone, a Personal Digital Assistant (PDA), a tablet computer, an electronic book, a television, a door lock, a smart phone, a console, and other devices having a display function.

While the application has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the application. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. The present application is not intended to be limited to the particular embodiments disclosed herein but is to cover all embodiments that may fall within the scope of the appended claims.

Claims

1. An array substrate, wherein the array substrate has a display area and a non-display area located on a peripheral side of the display area, the array substrate comprising:

a substrate;

the data module is arranged on the substrate and positioned in the non-display area, and comprises a plurality of data fanout lines;

the clock module is positioned in the non-display area and is stacked with the data module along the thickness direction of the array substrate, and the clock module comprises a plurality of clock signal lines;

the orthographic projection of the data module on the substrate and the orthographic projection of the clock module on the substrate at least partially overlap.

2. The array substrate of claim 1, wherein the orthographic projection of the clock module on the substrate is within the orthographic projection of the data module on the substrate.

3. The array substrate of claim 1, wherein the array substrate comprises two or more conductive layers disposed on the substrate and stacked in a thickness direction of the array substrate, and the plurality of data fanout lines are disposed in the two or more conductive layers;

preferably, the plurality of data fanout lines are located in more than two adjacent conductive layers, the plurality of clock signal lines are located in the same conductive layer, and the conductive layer where the plurality of clock signal lines are located is located on one side, facing towards or deviating from the substrate, of the conductive layer where the plurality of data fanout lines are located.

4. The array substrate of claim 3, further comprising data lines in the display region, wherein the data lines are connected to the data fanout lines in a one-to-one correspondence, and the data fanout lines connected to two adjacent data lines are located in different conductive layers.

5. The array substrate of claim 4, wherein the data lines are formed to extend along a first direction, and the data module and the clock module are located on one side of the display area in the first direction.

6. The array substrate of claim 5, further comprising a scan line extending along a second direction, wherein the second direction intersects the first direction;

the number of the data modules and the number of the clock modules are two, and the two data modules and the two clock modules are arranged on two sides of the non-display area in the second direction in an evenly distributed mode;

preferably, the display area includes a first sub-display area and a second sub-display area distributed along the second direction, the data line in the first sub-display area is connected to the data module located on a side of the first sub-display area facing away from the second sub-display area, the scan line in the first sub-display area is connected to the clock module located on a side of the first sub-display area facing away from the second sub-display area, the data line in the second sub-display area is connected to the data module located on a side of the second sub-display area facing away from the first sub-display area, and the scan line in the second sub-display area is connected to the clock module located on a side of the second sub-display area facing away from the first sub-display area;

preferably, the first sub-display area and the second sub-display area have equal areas.

7. The array substrate of claim 3, wherein the two or more conductive layers comprise: the first conducting layer comprises a shielding line positioned in the display area and a part of the data fanout line positioned in the non-display area;

preferably, the two or more conductive layers further include a second conductive layer located on a side of the first conductive layer away from the substrate, and the data fanout lines are respectively disposed on the first conductive layer and the second conductive layer;

preferably, the two or more conductive layers further include a third conductive layer located on a side of the second conductive layer away from the substrate, and the data fanout lines are respectively disposed on the first conductive layer, the second conductive layer, and the third conductive layer;

preferably, the two or more conductive layers further include a fourth conductive layer located on a side of the third conductive layer facing away from the substrate, and the plurality of clock signal lines are located on the fourth conductive layer.

8. The array substrate of claim 1, wherein a first gap exists between adjacent data fanout lines, and at least a portion of the orthographic projection of the clock signal line on the substrate and the orthographic projection of the first gap on the substrate at least partially overlap;

preferably, a second gap exists between two adjacent clock signal lines, and the width of the second gap is greater than the width of the first gap.

9. A display panel comprising the array substrate according to any one of claims 1 to 8.

10. A display device characterized by comprising the display panel according to claim 9.