CN113987979A - Sub-circuit matching method for analog integrated circuit - Google Patents
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Abstract
The invention provides a sub-circuit matching method for an analog integrated circuit, which comprises the following steps: reading a circuit netlist file, and distinguishing element node definition node labels in a circuit; respectively carrying out topology on the elements to generate a directed circuit topological graph; sequencing the node searching sequence of the sub-circuit, and dynamically selecting a plurality of nodes of the analog integrated circuit according to the node searching sequence, so as to form a plurality of node pairs and organize the node pairs into a searching tree, wherein one tree node of the searching tree represents one sub-graph state; adding the node pairs into the tree nodes to form a new sub-graph state, and when the node pairs consisting of the nodes of the same sub-circuit and the nodes of different analog integrated circuits are added, forming different branches in the search tree; pruning invalid branches in the search tree to quickly match nodes of the sub-circuit and the analog integrated circuit. The invention has the effect of realizing circuit matching with high accuracy and low computation complexity.
Description
Technical Field
The invention relates to the technical field of analog integrated circuit design, in particular to a sub-circuit matching method for an analog integrated circuit.
Background
With the development of semiconductor process technology, especially System on Chip (SoC), the number of transistors integrated in a Chip becomes larger and larger, which makes the circuit structure on the Chip more and more complex, and especially increases the challenge of analog integrated circuit design. The traditional analog integrated circuit design is finished by related personnel through pure manual design, and a layout is drawn manually, so that the design period of the analog integrated circuit is long and the efficiency is low. Therefore, analog circuit design is Aided by analog cad (computer Aided design) software, and the automatic process of analog integrated circuits is realized. However, because the analog circuit has poor anti-interference performance, high flexibility of the circuit structure and complicated performance indexes, compared with a digital circuit CAD tool, the traditional analog circuit design is more based on experience and knowledge of designers and a heuristic design process. Currently, no mature commercial CAD tool fully supports the automated process of analog circuit design and layout design. Design automation of analog integrated circuits has become a bottleneck in integrated circuit design.
Matching circuit identification problems often arise in circuit design as analog integrated circuits develop and circuit feature process sizes continue to decrease. The circuit mismatch can affect the performance parameters of the circuit such as common mode rejection ratio, offset, linearity and the like, and the circuit performance is rapidly deteriorated. The matching circuit identification problem considers whether a template circuit of a specified function or structure is present in a target circuit. The method is widely applied to works such as layout and schematic diagram consistency check (LVS), sequential circuit design, reverse engineering logic synthesis and the like, and plays an important role in design simulation of CAD tools. Currently, many expert scholars have proposed research methods for extracting sub-circuits in large-scale circuits. The SubGemini algorithm is a classical algorithm for solving the problem of subgraph isomorphism on a circuit, and firstly, all positions which accord with the subgraph isomorphism relation with a sub-circuit are found in a main circuit diagram through a division algorithm. The specific operation is to find a key node in the sub-circuit diagram, correspondingly find all nodes matched with the key node in the main circuit diagram to form a candidate set, and sequentially judge whether the sub-circuit isomorphism relationship is met in the candidate set. The SA (self-adapting) algorithm, which is commonly used to perform inaccurate map matching, modifies the objective function associated with circuit identification on a SubGemini basis. In the sub-graph isomorphic algorithm, most recently proposed algorithms follow three different approaches: tree search, constraint performance, and Graph Indexing. The problem is expressed as a search space by an algorithm based on tree search, the search space is usually accessed in a depth-first order, and a heiristics is used for avoiding useless parts in the space, so that the Ullmann and RI algorithm provided based on the method can effectively solve the sub-graph isomorphism problem.
However, the above methods are relatively expensive to calculate, slow and inefficient to identify, and have low accuracy when compared to each other.
In view of this, it is important to design a sub-circuit matching method with high accuracy and low computational complexity.
Disclosure of Invention
In order to solve the technical problems of low accuracy and high computational complexity of a matching circuit identification method in the prior art, the invention provides a sub-circuit matching method for an analog integrated circuit, which is used for solving the technical problems so as to realize circuit matching with high accuracy and low computational complexity.
The application provides a sub-circuit matching method for an analog integrated circuit, which comprises the following steps:
s1, reading a circuit netlist file, and defining node labels for element nodes in the sub-circuit and the analog integrated circuit to distinguish different types of elements;
s2, respectively carrying out topology on the elements in the sub-circuit and the analog integrated circuit, and generating directed circuit topological graphs of the sub-circuit and the analog integrated circuit;
s3, sequencing the node searching sequence of the sub-circuit, dynamically selecting a plurality of nodes of the analog integrated circuit according to the node searching sequence of the sub-circuit, respectively organizing the nodes of the sub-circuit and the nodes of the analog integrated circuit into a plurality of node pairs, organizing a search tree according to the node pairs, wherein one tree node in the search tree represents a sub-graph state;
s4, adding the node pair into the tree node to form a new sub-graph state, wherein when the node pair consisting of the node of the same sub-circuit and the node of different analog integrated circuits is added, the search tree forms different branches; and
and S5, pruning invalid branches in the search tree, and thus carrying out quick matching identification on the nodes of the sub-circuit and the analog integrated circuit.
The method comprises the steps of setting node labels for elements in a circuit to distinguish different types of elements, adopting different graph topology forms for the different types of elements, optimizing topological characteristic expression of a circuit structure, establishing a search tree, sequentially adding node pairs for searching by utilizing a tree search scheme and adopting a proper pruning rule, ensuring high-efficiency search, simultaneously having good pruning quality and enabling time complexity to be far less than exponential growth. The method and the device can correctly search the matching result in the analog integrated circuits of small, medium, large-scale and various mixed elements, and have short detection time.
Preferably, the step S1 of defining node labels for the sub-circuit and the component node in the analog integrated circuit specifically includes:
defining signal end node labels, and defining the node labels of the power supply node and the ground node as 0 and N respectively; and
defining a component node label, and giving a unique node label to a specific port of the component.
Node labels are arranged on nodes of the signal end and the components, so that the signal end and different components in the circuit are distinguished.
Preferably, the step S2 of performing topology on the elements in the sub-circuit and the integrated circuit respectively specifically includes: and establishing the topological structure of the element by taking the ports of the element as nodes and taking the connection relation among the ports of the element as edges. By carrying out directed graph topology on the elements, the topological characteristic expression of the circuit structure is further optimized, and the matching accuracy is improved.
Further preferably, the step of establishing the topology of the element specifically includes:
establishing a topological structure of an active device, wherein all ports of the active device are connected in a unilateral and directional manner, and all ports of the active device are connected with ports of other elements in a bilateral and directional manner; and
and establishing a topological structure of the passive device, wherein the ports of the passive device are connected in a bilateral directional mode.
By adopting different topological modes for the active device and the passive device, the generation of multiple groups of matching results contradictory with an actual circuit in the circuit matching process can be avoided.
Preferably, the step S2 of generating the directed circuit topology of the sub-circuit and the analog integrated circuit is embodied as follows: and sequencing and labeling the port nodes of each element in a mode of increasing the serial number. And according to the topological structure of the elements, setting sequence number labels to the port nodes of each element in an incremental mode, thereby generating the directed circuit topological graph.
Further preferably, after the step S2 and before the step S3, the method further includes: and carrying out classification labeling on port nodes of the elements of different types, adopting the same label for the same port node of the elements of the same type, and generating a circuit topology label graph of the sub-circuit and the analog integrated circuit. The port nodes of different types of elements are classified and labeled, and the same port nodes of the same type of elements adopt the same label, so that all elements can be identified by a subsequent algorithm.
Preferably, the step S3 of sorting the node matching sequence of the sub-circuit in the search tree specifically includes:
calculating the probability, namely calculating the number of corresponding nodes which have the same node labels with the nodes of the sub-circuit and are found in the analog integrated circuit, wherein the smaller the number of the corresponding nodes in the analog integrated circuit is, the higher the probability of finding the corresponding nodes meeting the isomorphic requirement of the sub-circuit is, and the higher the searching priority of the nodes corresponding to the sub-circuit is; and
comparing the node degrees, and calculating the out-degree and the in-degree of the sub-circuit nodes, wherein the higher the out-degree and the in-degree is, the higher the node search priority corresponding to the sub-circuit is;
wherein the priority of the probability calculation is greater than the priority of the comparison node degree.
The node matching sequence of the sub-circuits is determined by probability calculation and comparison of the node degrees, so that the redundancy degree of searching can be reduced, the calculation complexity is reduced, and the matching time is shortened.
Further preferably, the step S3 of dynamically selecting a plurality of nodes of the analog integrated circuit according to the node search sequence of the sub-circuit specifically includes: according to the node searching sequence of the sub-circuit, the last searching node is determined to be a father node of the current searching node, so that the candidate node searched at present is selected in the node searching process of the analog integrated circuit, wherein the selection principle of the candidate node is as follows:
the sequential relationship of the current search node of the sub-circuit with its parent node is the same as the sequential relationship of the candidate node with its parent node.
In the process of searching the nodes of the analog integrated circuit, the range of matching search in the nodes of the analog integrated circuit can be greatly reduced by restricting the candidate nodes, so that the computational complexity is reduced.
Preferably, the pruning the invalid branch of the search tree in the step S5 specifically includes: and judging whether the subgraph state of the currently searched tree node meets feasibility rules, if not, judging the tree node to be an invalid node and giving up the search of the tree node branch. By pruning branches of the tree nodes, the range of the nodes of the analog integrated circuit which need to be subjected to matching search is further narrowed, and the matching efficiency is improved.
Further preferably, the feasibility rule specifically includes:
after the new node pair is added to the tree node of the search tree, the node labels of the corresponding nodes in the analog integrated circuit and the sub-circuit are all the same, and the current sub-graph state, the sub-graph state of the next step and the sub-graph states of the next two steps of the search tree are all kept in a consistent state, wherein the consistent state is specifically represented as:
and after adding the new node pairs into the tree nodes of the search tree, all the node pairs in the current subgraph state meet the subgraph isomorphic relation.
After each tree node of the search tree is added with a new node pair, the method cuts off the branch with low possibility by predicting the possibility whether the branch can find the matching result or not, and abandons the search of the branch, thereby improving the matching search efficiency.
The application provides a sub-circuit matching method for an analog integrated circuit, which is characterized in that node labels are set for nodes of elements in a circuit to distinguish different types of elements, then different graph topology forms are adopted for the different types of elements, and classification labels are carried out on port nodes of the different types of elements to generate a circuit topology label graph, so that the topological characteristic expression of a circuit structure is optimized, and the more accurate symmetrical matching can be carried out on the different types of elements. And then, by establishing a search tree, sequentially adding node pairs for searching by using a tree search scheme and adopting a proper pruning rule, converting the circuit matching problem into a sub-graph isomorphism problem, ensuring high-efficiency search and simultaneously ensuring that the time complexity is far less than the exponential increase. The method and the device can correctly search the matching result in the analog integrated circuits of small, medium, large-scale and various mixed elements, and have short detection time.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain the principles of the invention. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
FIG. 1 is a flow diagram of a sub-circuit matching method for an analog integrated circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a circuit netlist file according to one embodiment of the invention;
fig. 3 is a circuit configuration diagram of a differential amplifying circuit according to an embodiment of the present invention;
fig. 4(a) is a device structure diagram of a MOS transistor according to an embodiment of the invention;
fig. 4(b) is a device internal topology structure diagram of a MOS transistor according to an embodiment of the invention;
FIG. 5(a) is a diagram of a device structure of a resistor according to an embodiment of the present invention
FIG. 5(b) is a diagram of a device internal topology of a resistor in accordance with one embodiment of the present invention;
FIG. 6 is a circuit topology diagram of a differential amplifier circuit according to a specific embodiment of the present invention;
FIG. 7 is a circuit topology label diagram of a differential amplification circuit in accordance with a specific embodiment of the present invention;
FIG. 8 is a flow diagram of a tree search in accordance with a specific embodiment of the present invention.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the list of additional identical elements in a process, method, article, or apparatus that comprises the element.
Fig. 1 shows a flow chart of a sub-circuit matching method for an analog integrated circuit according to an embodiment of the present invention, and as shown in fig. 1, the matching method includes the following steps:
and S1, reading the circuit netlist file, and defining node labels for the component nodes in the sub-circuit and the analog integrated circuit so as to distinguish different types of components.
In a specific embodiment, reading the circuit netlist file includes reading circuit information of a circuit signal terminal and a circuit component, that is, defining a node tag includes defining a signal terminal node tag and defining a component node tag. Wherein in the define signal end node label section, the node labels of the power supply node and the ground node are defined as 0 and N, respectively; in the define component node tag section, a unique node tag is given to a particular port of a component. The concrete description is as follows:
FIG. 2 is a schematic diagram of a circuit netlist file according to an embodiment of the invention, where the second row in the circuit netlist file shows port names and attributes in the circuit, as shown in FIG. 2. Wherein, I represents an input port, O represents an output port, and B represents an input/output port. In the subsequent circuit topological graph structure process, if the input end node and the output end node are extracted, an expected matching result cannot be obtained due to the collision of node labels when the subgraph isomorphism problem is solved. Therefore, in this embodiment, only two signal terminals, i.e., the power node and the ground node, are extracted, and node tags of the power node and the ground node are set to 0 and N, respectively (N is a tag different from ports of all types of components in a circuit, and in this embodiment, N is 99), so that it is ensured that no duplication with node tags of other components occurs.
With continued reference to fig. 2, the circuit netlist file fully expresses the connection topology relationship and the attribute information of the entire circuit device. When the circuit is designed, the model of the element is determined while the process is determined, so that the element can be determined to belong to an active element P-type field effect transistor PMOS, an N-type field effect transistor NMOS, a triode BJT or a passive element capacitor, resistor, inductor and the like through the circuit netlist information. Two methods can be used to distinguish the types of components: the first method is to judge through the names of the first column of components in the circuit network table file, and the names of the common components start with the letters of the component types, for example, most MOS active devices start with M, and most resistor passive devices start with R; the second method is to confirm according to the process type names of various components in the circuit netlist information, in this embodiment, ND in the circuit netlist file indicates that the component is an NMOS transistor, and PD indicates that the component is a PMOS transistor. In this embodiment, the first method is specifically adopted to determine the type of the component, and the process type and the process parameter of the component are used as the parameter information thereof, and the matching circuit is identified according to whether the corresponding component parameter is considered.
And S2, respectively carrying out topology on the elements in the sub-circuit and the analog integrated circuit to generate a directed circuit topological graph of the sub-circuit and the analog integrated circuit.
In a specific embodiment, the ports of the elements are used as nodes, and the connection relations among the ports of the elements are used as edges, so that the elements are subjected to topology, the topological structures of the elements are established, and the topological structures of a plurality of elements are combined into a directed circuit topological graph of a corresponding sub-circuit and a simulation integrated circuit. The topology structure of the element includes an active device topology structure and a passive device topology structure, which will be described in the following with a specific circuit.
Fig. 3 is a circuit diagram of a differential amplifier circuit according to an embodiment of the present invention, and as shown in fig. 3, the differential amplifier circuit includes 2 PMOS transistors M1, M2, and 3 NMOS transistors M3, M4, and M5, and includes a power signal port VDD, a ground signal port GND, three input signal ports Vin, Vip, Vb1, and an output signal port VDD. The MOS transistor comprises four ports, D, G, S, B respectively, and only the connection state of the end of the MOS transistor D, G, S is concerned in circuit identification, and the substrate end is ignored. In the present embodiment, the MOS transistor is therefore represented as a three-port device for topological representation of the figure. However, in consideration of the diversity of port connections of the active component and the passive component in the actual circuit, a topology representation mode of the node cluster is established in this embodiment.
The definition for the active device topology and the passive device topology is as follows:
fig. 4(a) shows a device structure diagram of a MOS transistor according to an embodiment of the present invention, and fig. 4(b) shows a device internal topology structure diagram of a MOS transistor according to an embodiment of the present invention, and as shown in fig. 4(a) and fig. 4(b), the MOS transistor expands into a node cluster structure in which three nodes are connected, where each node represents D, G and S three ports thereof, and the three ports are connected with other elements in a circuit in a bilateral directional manner; if the connection mode of the non-directional side is also adopted in the active device, a plurality of groups of matching results inconsistent with the actual circuit can be generated, so that the connection in the active device needs to be redefined, and the connection between the internal ports of the MOS tube is connected in a single-sided directional mode. The MOS tube is mapped according to an internal connection mode that the G end points to the D end and the G end points to the S end. It should be noted that, for the triode BJT, the NPN and PNP devices are defined similarly to the MOS transistor, and are not described herein again.
Fig. 5(a) shows a device structure diagram of a resistor according to an embodiment of the present invention, and fig. 5(b) shows a device internal topology diagram of a resistor according to an embodiment of the present invention, and as shown in fig. 5(a) and fig. 5(b), if a single-sided directional connection manner is adopted inside a passive component, it would violate its bidirectionality in a circuit structure. Therefore, the internal ports of the capacitor, the resistor and the inductor adopt a bilateral directional connection mode. The diode is also a two-port component, and the positive end and the negative end of the diode can not be replaced, so that the diode is different from a resistor internal mapping mode, and a unilateral and directional connection mode is adopted between the two ports of the diode.
According to the method of mapping the internal connection of the components and the external port connection, fig. 6 shows a circuit topology diagram of the differential amplifier circuit according to an embodiment of the present invention, as shown in fig. 6, node 0 represents a power signal port node, node 16 represents a ground signal port node, nodes 1, 2, 3, 4, 5, and 6 represent port nodes of PMOS transistors, and nodes 7, 8, 9, 10, 11, 12, 13, 14, and 15 represent port nodes of NMOS transistors. In the embodiment, according to the device information in the circuit netlist file, the port nodes of each element are sorted and labeled in a mode of increasing the serial number. If the device is an MOS tube, according to the arrangement sequence of the port information of the device in the netlist being D, G, S, carrying out serial number increasing operation on the device, and marking three continuous serial numbers of the device; if the device is a resistor, serial number numbering is carried out on the device according to the port information arrangement sequence of the device in the netlist, namely Min and Plus. And by parity of reasoning, numbering of all components in the circuit is completed.
In a preferred embodiment, port nodes of different kinds of elements in the circuit are class labeled, and the same port nodes of the same kind of elements use the same label. With specific reference to table 1:
TABLE 1
Referring to table 1, fig. 7 shows a circuit topology tag diagram of a differential amplifier circuit according to an embodiment of the present invention, as shown in fig. 7, in the process of performing circuit topology, different element node differentiation can be performed in a classified manner, which is also an important basis for subsequently determining whether two diagrams are sub-graph isomorphism. And if the labels of the corresponding nodes in the two matched graphs are the same, the matching result meets one of the constraints of the sub-graph isomorphism. Therefore, according to the properties of the elements in the circuit, different ports of the MOS tube cannot be replaced, and the positive and negative ports of the similar resistor can be replaced, so that all the elements can be identified by a subsequent algorithm.
S3, sorting the node searching sequence of the sub-circuit, dynamically selecting a plurality of nodes of the analog integrated circuit according to the node searching sequence of the sub-circuit, organizing the nodes of the sub-circuit and the nodes of the analog integrated circuit into a plurality of node pairs respectively, organizing a searching tree according to the node pairs, and enabling one tree node in the searching tree to represent a sub-graph state.
The node searching sequence of the sub-circuit and the analog integrated circuit is determined, a searching tree is organized according to a plurality of node pairs, and then the nodes of the sub-circuit and the analog integrated circuit are searched in a tree searching mode. Fig. 8 is a flowchart illustrating tree searching according to an embodiment of the present invention, and as shown in fig. 8, step S3 specifically includes the following steps:
and S31a, determining the node searching sequence of the subcircuits through probability calculation.
In the probability calculation, the number of corresponding nodes which have the same node labels with the nodes of the sub-circuits in the analog integrated circuit is calculated, and if the number of the corresponding nodes in the analog integrated circuit is less, the probability of finding the corresponding nodes which meet the requirement of the sub-graph isomorphism in the corresponding nodes with the same node labels is higher, so that the searching priority of the nodes of the corresponding sub-circuits is higher, the searching redundancy degree can be reduced, the calculation complexity is reduced, and the matching time is shortened.
And S31b, determining the node searching order of the sub-circuits by comparing the node degrees.
If one wants to find a node in an analog integrated circuit that matches a node in a sub-circuit, three conditions must be met: 1. the node labels of the analog integrated circuit node and the sub-circuit node are the same; 2. the in-degree of the analog integrated circuit node is not less than that of the sub-circuit node; 3. the output of the analog integrated circuit node is not less than the output of the sub-circuit node. Wherein, the degree of entry of a node refers to the number of arcs (edges) which end at the node by taking the node as an arc head; the out-degree of a node refers to the number of arcs (edges) starting from the node with the node as the arc tail. Therefore, in the comparison of the node degrees, the higher the out-degree and the in-degree of the sub-circuit node are calculated, which means that the probability of finding the node corresponding to the sub-circuit in the analog integrated circuit to meet the requirement of the sub-graph isomorphism is higher, and thus the search priority of the corresponding sub-circuit node is higher. In the present embodiment, in determining the node search order of the sub circuit, the priority of the probability calculation is higher than the priority of the comparison node degree, and therefore, if the node search order of the sub circuit has already been determined in step S31a, step S31b is not necessary.
And S32, according to the node searching sequence of the sub-circuit, the last searching node is determined to be the father node of the current searching node, and therefore the candidate node of the current searching is selected in the node searching process of the analog integrated circuit.
By introducing the concept of the father node, when the sequential relationship between the current search node of the sub-circuit and the father node of the sub-circuit is the same as the sequential relationship between the candidate node and the father node of the sub-circuit, the node is used as the candidate node for searching, so that the range of matching search in the nodes of the analog integrated circuit can be greatly reduced, and the calculation complexity is reduced.
And S33, organizing the nodes of the sub-circuit and the plurality of nodes of the analog integrated circuit into a plurality of node pairs respectively, and organizing a search tree according to the node pairs.
In the process of dynamically selecting the nodes of the analog integrated circuit according to the node searching sequence of the sub-circuit, one node of the sub-circuit corresponds to a plurality of nodes of a plurality of analog integrated circuits, so that a plurality of node pairs can be organized between the node and the node, a searching tree is organized according to the node pairs, and then the nodes of the sub-circuit and the analog integrated circuit can be searched in the searching tree.
And S4, adding the node pairs into the tree nodes to form a new subgraph state, wherein when the node pairs consisting of the nodes added into the same sub-circuit and the nodes added into different analog integrated circuits are searched to form different branches.
In step S32, in the process of dynamically selecting the nodes of the analog integrated circuit according to the node search order of the sub-circuit, one node of the sub-circuit corresponds to a plurality of nodes of the plurality of analog integrated circuits, so that the search tree is continuously increased and a plurality of branches are formed as the node pairs are gradually added.
And S5, pruning invalid branches in the search tree, and performing quick matching identification on the nodes of the sub circuit and the analog integrated circuit.
In the matching process, the node pair selected each time is added into the tree node to form a new sub-graph state which is not necessarily appropriate, so that some invalid branches need to be pruned, the range of the nodes of the analog integrated circuit which need to be subjected to matching search is further reduced, and the matching efficiency is further improved.
With continued reference to fig. 8, in particular, step S5 includes the following steps:
s51, judging whether the sub-graph state corresponding to the currently searched tree node meets the feasibility rule, if so, entering the step S52; if not, the process proceeds to step S53.
And S52, reserving the search for the tree node branch.
And S53, pruning the tree node branch and abandoning the search of the tree node branch.
For step S51, in order to better describe the definition of the sub-graph isomorphism, it is explained in detail by the mathematical set relationship in the present embodiment. Assuming that the sub-circuit and the analog integrated circuit are separateIs G1＝(V1，E1) And G2＝(V2，E2) Wherein V is1And V2Set of nodes in sub-circuits and analog integrated circuits, respectively, E1And E2Respectively, a collection of edges in a sub-circuit and an analog integrated circuit. Drawing G1Middle node and graph G2The middle node correspondences are represented as a set M, i.e.
If node u ∈ V1Then μ (vu) ∈ V2Denotes G corresponding to node u2A node in (1); if the node V is equal to V2Then μ-1(u)∈V1Denotes G corresponding to node v1Of the node (b). Wherein mu is
Is a single mapping function, when the graph G1And G2When the following 6 constraints are met, the two graphs are considered to belong to the sub-graph isomorphism relationship. The 6 constraints are as follows:
(1)
(u, mu (u)). epsilon.M; i.e. for G1In each node, G2There is a corresponding node to which it corresponds and such a pair of nodes constitutes the set M.
(2)
I.e. G1Any two different nodes in the network, their corresponding G2Cannot be the same.
(3)
I.e. G1Each side of G2One edge corresponds to the other edge, and nodes at two ends of the edge correspond to one another.
(4)
I.e. G1Any two nodes if they correspond to G2Has an edge between nodes in, then G1There must also be an edge between these two nodes.
(5)
I.e. the node labels of each pair of corresponding nodes are to be identical.
(6)
I.e. the node labels of each pair of corresponding edges are identical.
In the process of pruning invalid branches in a search tree, the following two states are defined for each node of the tree search according to the subgraph isomorphic constraint in the embodiment: (a) the target state, the current sub-graph state contains all nodes in the sub-circuit, which means that the sub-structure and the sub-circuit in an analog integrated circuit are found to be isomorphic; (b) in the consistent state, the number of existing nodes in the current sub-graph state does not reach all the number of nodes in the sub-circuit, but the owned node pairs meet 6 constraints of the sub-graph isomorphism. And under the consistent state, judging whether the node pair is added into the tree node to form a new subgraph state or not according to the feasibility rule, thereby determining whether to prune the tree node branch or not.
The feasibility rule contains the following four conditions:
1. after a new node pair is added to a tree node of the search tree, node labels of corresponding nodes in the analog integrated circuit and the sub-circuit are all the same;
2. after a new node pair is added to a tree node of the search tree, the state of the search tree in the current sub-graph is a consistent state;
3. after a new node pair is added to a tree node of the search tree, the subgraph state of the search tree searched in one step in the future is a consistent state;
4. after new node pairs are added to tree nodes of the search tree, the subgraph state of the search tree in the next two steps is a consistent state.
The feasibility rule predicts the possibility of successful matching by judging the currently searched subgraph state and the subgraph states of future one-step search and two-step search, and cuts off some tree node branches which are basically impossible to be successfully matched, thereby ensuring the pruning quality (namely improving the matching accuracy), greatly reducing the calculation complexity in the matching process and shortening the matching period.
And S6, according to the node matching output results of the sub-circuit and the analog integrated circuit, carrying out error screening and elimination on the output results of the matched elements, wherein the nodes of the elements do not belong to the same element.
In the output matching result, the condition that the matched element nodes do not belong to the same device can occur, at this time, judgment needs to be made, and the error condition is eliminated, so that the accurate output result is more accurately screened out.
The invention provides a sub-circuit matching method facing an analog integrated circuit, which is characterized in that node labels are arranged on nodes of components in the sub-circuit and the analog integrated circuit to distinguish different types of components, then different graph topology forms are adopted for the different types of components, and classification labels are carried out on port nodes of the different types of components to generate circuit topology label graphs of the sub-circuit and the analog integrated circuit, so that the topological characteristic expression of a circuit structure is optimized, and the components of different types can be symmetrically matched more accurately. And then, by establishing a search tree, sequentially adding node pairs for searching by using a tree search scheme and adopting a proper pruning rule, converting the circuit matching problem into a sub-graph isomorphism problem, ensuring high-efficiency search and simultaneously ensuring that the time complexity is far less than the exponential increase. The method and the device can correctly search the matching result in the analog integrated circuits of small, medium, large-scale and various mixed elements, and have short detection time.
In the embodiments of the present application, it should be understood that the disclosed technical contents may be implemented in other ways. The above-described embodiments of the apparatus/system/method are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit and scope of the invention. In this way, if these modifications and changes are within the scope of the claims of the present invention and their equivalents, the present invention is also intended to cover these modifications and changes. The word "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims shall not be construed as limiting the scope.
Claims (10)
1. A sub-circuit matching method for an analog integrated circuit is characterized by comprising the following steps:
s1, reading a circuit netlist file, and defining node labels for element nodes in the sub-circuit and the analog integrated circuit to distinguish different types of elements;
s2, respectively carrying out topology on the elements in the sub-circuit and the analog integrated circuit, and generating directed circuit topological graphs of the sub-circuit and the analog integrated circuit;
s3, sequencing the node searching sequence of the sub-circuit, dynamically selecting a plurality of nodes of the analog integrated circuit according to the node searching sequence of the sub-circuit, respectively organizing the nodes of the sub-circuit and the nodes of the analog integrated circuit into a plurality of node pairs, organizing a search tree according to the node pairs, wherein one tree node in the search tree represents a sub-graph state;
s4, adding the node pair into the tree node to form a new sub-graph state, wherein when the node pair consisting of the node of the same sub-circuit and the node of different analog integrated circuits is added, the search tree forms different branches; and
and S5, pruning invalid branches in the search tree, and thus carrying out quick matching identification on the nodes of the sub-circuit and the analog integrated circuit.
2. The method of claim 1, wherein the step S1 of defining node labels for the sub-circuits and the component nodes in the analog integrated circuit specifically comprises:
defining signal end node labels, and defining the node labels of the power supply node and the ground node as 0 and N respectively; and
defining a component node label, and giving a unique node label to a specific port of the component.
3. The method according to claim 1, wherein the step S2 of performing topology on the elements in the sub-circuit and the analog integrated circuit respectively specifically includes: and establishing the topological structure of the element by taking the ports of the element as nodes and taking the connection relation among the ports of the element as edges.
4. The method according to claim 3, characterized in that said step of establishing the topology of said elements comprises in particular:
establishing a topological structure of an active device, wherein all ports of the active device are connected in a unilateral and directional manner, and all ports of the active device are connected with ports of other elements in a bilateral and directional manner; and
and establishing a topological structure of the passive device, wherein the ports of the passive device are connected in a bilateral directional mode.
5. The method according to claim 4, wherein the step S2 of generating the directed circuit topology diagrams of the sub-circuits and the analog integrated circuit specifically comprises: and sequencing and labeling the port nodes of each element in a mode of increasing the serial number.
6. The method of claim 5, further comprising, after the step S2 and before the step S3: and carrying out classification labeling on port nodes of the elements of different types, adopting the same label for the same port node of the elements of the same type, and generating a circuit topology label graph of the sub-circuit and the analog integrated circuit.
7. The method according to claim 1, wherein the step S3 of sorting the node matching order of the sub-circuits in the search tree specifically comprises:
calculating the probability, namely calculating the number of corresponding nodes which have the same node labels with the nodes of the sub-circuit and are found in the analog integrated circuit, wherein the smaller the number of the corresponding nodes in the analog integrated circuit is, the higher the probability of finding the corresponding nodes meeting the isomorphic requirement of the sub-circuit is, and the higher the searching priority of the nodes corresponding to the sub-circuit is; and
comparing the node degrees, and calculating the out-degree and the in-degree of the sub-circuit nodes, wherein the higher the out-degree and the in-degree is, the higher the node search priority corresponding to the sub-circuit is;
wherein the priority of the probability calculation is greater than the priority of the comparison node degree.
8. The method of claim 1, wherein the step S3 of dynamically selecting the plurality of nodes of the analog integrated circuit according to the node search order of the sub-circuit comprises: according to the node searching sequence of the sub-circuit, the last searching node is determined to be a father node of the current searching node, so that the candidate node searched at present is selected in the node searching process of the analog integrated circuit, wherein the selection principle of the candidate node is as follows:
the sequential relationship of the current search node of the sub-circuit with its parent node is the same as the sequential relationship of the candidate node with its parent node.
9. The method according to claim 1, wherein the pruning the invalid branch of the search tree in the step S5 specifically includes: and judging whether the subgraph state of the currently searched tree node meets feasibility rules, if not, judging the tree node to be an invalid node and giving up the search of the tree node branch.
10. The method according to claim 9, wherein the feasibility rule specifically comprises:
after the new node pair is added to the tree node of the search tree, the node labels of the corresponding nodes in the analog integrated circuit and the sub-circuit are all the same, and the current sub-graph state, the sub-graph state of the next step and the sub-graph states of the next two steps of the search tree are all kept in a consistent state, wherein the consistent state is specifically represented as:
and after adding the new node pairs into the tree nodes of the search tree, all the node pairs in the current subgraph state meet the subgraph isomorphic relation.
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