CN113972262B - Gallium oxide-two-dimensional P-type van der Waals tunneling transistor, dual-band photoelectric detection device and preparation method - Google Patents

Gallium oxide-two-dimensional P-type van der Waals tunneling transistor, dual-band photoelectric detection device and preparation method Download PDF

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CN113972262B
CN113972262B CN202111209155.2A CN202111209155A CN113972262B CN 113972262 B CN113972262 B CN 113972262B CN 202111209155 A CN202111209155 A CN 202111209155A CN 113972262 B CN113972262 B CN 113972262B
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gallium oxide
oxide layer
dimensional material
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王湛
刘朋源
孙静
关云鹤
刘翔泰
陆琴
王少青
贾一凡
陈海峰
马晓华
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Xian University of Posts and Telecommunications
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Abstract

The invention relates to a gallium oxide-two-dimensional P-type van der Waals tunneling transistor, a dual-band photoelectric detection device and a preparation method thereof, which solve the problem that Ga is caused in the preparation of the existing UWBG material transistor/photoelectric detection device 2 O 3 The technical problem that P-type doping is lacking, and PN junction deep ultraviolet-infrared dual-band detection of a tunneling transistor and grid voltage modulation cannot be achieved simultaneously is solved. The transistor and the photoelectric detection device comprise a back gate electrode, a dielectric oxide layer, a gallium oxide electrode forming ohmic contact, a P-type two-dimensional material layer, a P-type two-dimensional material electrode forming ohmic contact and a dielectric passivation layer; the gallium oxide layer and the P-type two-dimensional material layer are partially overlapped to form a heterojunction; the gallium oxide layer being unintentionally doped or doped Ga 2 O 3 A quasi-two-dimensional crystal thin film; the P-type two-dimensional material layer is a black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film. In addition, the invention also provides a preparation method of the transistor and the dual-band photoelectric detection device.

Description

Gallium oxide-two-dimensional P-type van der Waals tunneling transistor, dual-band photoelectric detection device and preparation method
Technical Field
The invention relates to a transistor/photoelectric detector and a preparation method thereof, in particular to a quasi-two-dimensional gallium oxide (Ga) based on grid voltage regulation 2 O 3 ) Two-dimensional P-type van der waals tunneling transistor and dual-band deep ultraviolet-infrared (DUV-IR) photodetector and method of fabrication.
Background
Gallium oxide has received extensive attention as a novel Ultra Wide Band Gap (UWBG) semiconductor material with a collimated band gap of 4.6-4.9eV, up to 2X 10 7 cm/s electron saturation drift velocity, and light response peak corresponding to solar blind wave band (250-270 nm), ga 2 O 3 Has important application value in the fields of power electronics, solar blind deep ultraviolet detection and the like.
The preparation of the Field Effect Transistor (FET) device with larger switching ratio and steep Subthreshold Swing (SS) has great significance for improving the response speed of the device and reducing the energy consumption, and the SS of the device can be effectively reduced by structures such as negative capacitance field effect transistors (NC-FETs), tunneling Field Effect Transistors (TFETs) and the like.
In Ga 2 O 3 In terms of FETs, fe-NCFETs based on ferroelectric gates have been reported, but ferroelectric gate devices still need to provide an initial polarization signal, their holding capability is only somewhat time-efficient, and they reduce the saturation current value of the FET device. Due to Ga 2 O 3 Wider bandgap and greater affinity, heterojunction-based Ga 2 O 3 TFET reports less.
In Ga 2 O 3 DUV-related, schottky (SB) barrier-based metal-semiconductor-metal (MSM) and phototransistor DUV photovoltaics have proven to be more robustThe high responsivity and the high light-dark current ratio are achieved, but the ultraviolet light blocking of the metal in the MSM structure is not beneficial to the improvement of detection performance, and the dark current of the common phototransistor is high. Meanwhile, compared with single spectrum detection, the dual-band detection has higher sensitivity and communication accuracy, and the DUV-IR dual-band detection is realized on the same system with higher practical value.
Furthermore, the lack of P-type doping hinders Ga 2 O 3 The development of PN structure, PN structure with high quality based on crystal growth, tunneling device and photoelectric detection device thereof, and the development of Ga without chemical bond connection are urgently needed 2 O 3 The heterogeneous technology thus improves its gating and DUV detection capabilities.
The two-dimensional (2D) material has rich energy band structure, and by means of the inherent van der Waals (vdW) structure, the 2D material can form a PN junction, SB junction and other mixed heterostructures with ideal energy bands with a wide forbidden band semiconductor in a transfer mode. Currently based on Ga 2 O 3 Mixed heterojunctions of-2D have been reported, for example, ga 2 O 3 -metallic 2D material heterojunction: ga 2 O 3 Graphene (Gr) structures are capable of implementing SB, metal-semiconductor field effect transistor (MESFET), and optoelectronic MSM detection devices simultaneously, whereas Ga 2 O 3 The MSM structure of Gr has only the detection capability of the DUV band; ga 2 O 3 Niobium disulfide (NbS) 2 ) MESFETs have excellent gate control characteristics but do not exhibit photodetection capability. Ga 2 O 3 -P-type two-dimensional material heterojunction: ga 2 O 3 -Black Phosphorus (BP) and Ga 2 O 3 Molybdenum ditelluride (MoTe) 2 ) The PN Junction Field Effect Transistor (JFET) device has the advantages that the SS can be lower, but the off-state electric leakage of the JFET device is larger, the SS cannot be further reduced due to the limitation of a higher energy band structure, meanwhile, the device has higher requirements on the quality of a heterojunction interface, and in addition, the DUV/IR or dual-band detection based on the common PN is not provided with the charge accumulation function of grid voltage regulation, so that the external quantum efficiency and the responsivity of photoelectric detection are still lower.
Disclosure of Invention
The inventionThe aim is to solve the problem that Ga is used in the preparation of the transistor/photoelectric detector made of the existing UWBG material 2 O 3 The technical problems that P-type doping is lacking and PN junction dual-band photoelectric detection of TFET and grid voltage modulation cannot be achieved simultaneously are solved, and a gallium oxide-two-dimensional P-type Van der Waals tunneling transistor, a dual-band photoelectric detection device and a preparation method are provided.
The technical idea of the invention is as follows: in Ga 2 O 3 In the preparation of a base transistor/photoelectric detection device, the selection of a P-type two-dimensional material is further relaxed on the basis of breaking the strict energy band requirement of the JFET device, and the SS of the device can be further improved by using a tunneling structure without improving the leakage current of the device. The P-type two-dimensional semiconductor material selected by the P-type two-dimensional material layer can be: the band gap of Black Phosphorus (BP) is 0.3-0.4eV, or the band gap of beta-phase simple substance tellurium (Te) is 0.35-0.5eV, or 2H phase MoTe 2 Band gap of 0.9-1eV, or tungsten diselenide (WSe) 2 ) Band gap of 1-1.1eV, or platinum diselenide (PdSe) 2 ) The band gap is 0-1.2eV, and the affinity energy of the five is about 4eV, and the two satisfy the requirement of Ga 2 O 3 Tunneling and Near Infrared (NIR)/mid-infrared (MIR) luminescence conditions, ga formed 2 O 3 -BP is a type I heterojunction tunneling device and a DUV-MIR detector; ga 2 O 3 Te is a type II heterojunction tunneling device and a DUV-MIR detector; ga 2 O 3 -MoTe 2 、Ga 2 O 3 -WSe 2 And Ga 2 O 3 -PdSe 2 Are type II heterojunction tunneling devices and DUV-NIR detectors.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
the gallium oxide-two-dimensional P-type van der Waals tunneling transistor is characterized in that: the transistor unit comprises a dielectric oxide layer, a dielectric passivation layer, a back gate electrode and a transistor unit arranged on the upper surface of the dielectric oxide layer;
the transistor unit comprises an active region gallium oxide layer, a P-type two-dimensional material layer, a gallium oxide electrode and a P-type two-dimensional material electrode, wherein the gallium oxide electrode and the P-type two-dimensional material electrode are respectively connected with the gallium oxide layer and the P-type two-dimensional material layer;
the gallium oxide layer and the P-type two-dimensional material layer are partially overlapped to form a heterojunction; the gallium oxide electrode and the gallium oxide layer form ohmic contact; the P-type two-dimensional material electrode and the P-type two-dimensional material layer form ohmic contact;
the medium passivation layer is positioned on the upper surface of the whole body formed by the gallium oxide layer, the P-type two-dimensional material layer, the gallium oxide electrode, the P-type two-dimensional material electrode and the medium oxidation layer;
the back gate electrode is arranged on the lower surface of the dielectric oxide layer;
the gallium oxide layer is unintentionally doped Ga 2 O 3 Quasi-two-dimensional crystal thin film, or Si-or Ge-or Sn-doped Ga 2 O 3 A quasi-two-dimensional crystal thin film;
the P-type two-dimensional material layer is a black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film which is transferred on the upper surface of the dielectric oxide layer or part of the gallium oxide layer by a wet method or a dry method.
Further, the distance between the gallium oxide electrode and the P-type two-dimensional material electrode is larger than 2 mu m;
the back gate electrode is made of N-type or P-type heavily doped Si, and Au or Cu evaporated on the lower surface of the heavily doped Si, or an ITO conductive glass or Cu conductive adhesive tape or a C conductive adhesive tape stuck on the lower surface of the heavily doped Si.
Further, the gallium oxide electrode comprises a first bottom layer contact metal and a first top layer metal; the first bottom contact metal and the gallium oxide layer form ohmic contact; the first bottom layer contact metal is made of Ti or Cr, and the first top layer contact metal is made of Au;
the P-type two-dimensional material electrode comprises a second bottom layer contact metal and a second top layer metal; the second bottom contact metal and the P-type two-dimensional material layer form ohmic contact; the material of the second bottom layer contact metal is Pd, and the material of the second top layer contact metal is Au;
the dielectric oxide layer is made of SiO 2 Or Al 2 O 3 Or HfO 2 Or ZrO(s) 2 ；
The material of the medium passivation layer is h-BN or SiO 2 Or Al 2 O 3 Or HfO 2 Or Si (or) 3 N 4 。
Further, the thickness of the gallium oxide layer is 10-350nm;
the thickness of the P-type two-dimensional material layer is 5-60nm;
the thickness of the dielectric oxide layer is 30-300nm;
the thickness of the dielectric passivation layer is 10-50nm;
the thickness of the first bottom layer contact metal is 50-200nm, and the thickness of the first top layer metal Au is 100-300nm;
the thickness of the second bottom layer contact metal is 6-30nm, and the thickness of the second top layer metal Au is 60-100nm.
Meanwhile, the invention also provides a preparation method of the gallium oxide-two-dimensional P-type van der Waals tunneling transistor, which is characterized by comprising the following steps:
step 1, selecting a substrate containing heavily doped Si and a dielectric oxide layer formed on the upper surface of the substrate, and cleaning the substrate;
step 2, preparing a transistor unit on the upper surface of the dielectric oxide layer;
2.1 Beta-phase-unintentionally doped Ga 2 O 3 Thin films, or stripping Si-or Ge-or Sn-doped Ga 2 O 3 The crystal film is adhered on the dielectric oxide layer to obtain a quasi-two-dimensional gallium oxide layer of 10-350nm;
2.2 Preparing a gallium oxide electrode on the dielectric oxide layer, and forming ohmic contact with the gallium oxide layer after high-temperature rapid annealing of the gallium oxide electrode;
2.3 Peeling or growing a P-type two-dimensional material layer of a black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film with the wavelength of 5-60nm; transferring the P-type two-dimensional material layer to the dielectric oxide layer by a wet method or a dry method, so that the P-type two-dimensional material layer and the gallium oxide layer are partially overlapped to form a heterojunction;
2.4 Preparing a P-type two-dimensional material electrode on the dielectric oxide layer to form ohmic contact with the P-type two-dimensional material layer;
step 3, growing or transferring the dielectric passivation layer to the upper surface of the transistor unit and the integral formed by the dielectric oxide layer;
and 4, processing the heavily doped Si substrate on the lower surface of the dielectric oxide layer to prepare a back gate electrode, thereby completing the preparation of the gallium oxide-two-dimensional P-type van der Waals tunneling transistor.
In addition, the invention also provides a dual-band photoelectric detection device, which is characterized in that: the transistor unit comprises a dielectric oxide layer, a back gate electrode, a dielectric passivation layer and a transistor unit arranged on the upper surface of the dielectric oxide layer;
the transistor unit comprises an n multiplied by m die array formed by dies, and a gallium oxide electrode and a P-type two-dimensional material electrode which are correspondingly connected with the die array, wherein n and m are integers more than or equal to 1; the row spacing and the column spacing of the die array are both greater than 20 μm;
the die comprises an active area gallium oxide layer and a P-type two-dimensional material layer; the gallium oxide layer and the P-type two-dimensional material layer are partially overlapped to form a heterojunction; the gallium oxide electrode and the gallium oxide layer form ohmic contact; the P-type two-dimensional material electrode and the P-type two-dimensional material layer form ohmic contact;
the dielectric passivation layer is positioned on the upper surface of the whole body formed by the die array, the gallium oxide electrode, the P-type two-dimensional material electrode and the dielectric oxide layer;
the back gate electrode is arranged on the lower surface of the dielectric oxide layer;
the gallium oxide layer is unintentionally doped Ga 2 O 3 Quasi-two-dimensional crystal thin film, or Si-or Ge-or Sn-doped Ga 2 O 3 A quasi-two-dimensional crystal thin film;
the P-type two-dimensional material layer is a black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film which is transferred on the upper surface of the dielectric oxide layer or part of the gallium oxide layer by a wet method or a dry method.
Further, the gallium oxide layers of at least 1 column of the dies in the transistor unit share one gallium oxide electrode, or the P-type two-dimensional material layers share one P-type two-dimensional material electrode;
or the gallium oxide layers of at least 1 column of the dies in the transistor unit share one gallium oxide electrode, and the P-type two-dimensional material layers of at least 1 column of the dies in the rest dies share one P-type two-dimensional material electrode;
or the gallium oxide layers of at least 1 line of dies in the transistor unit share one gallium oxide electrode, or the P-type two-dimensional material layers share one P-type two-dimensional material electrode;
alternatively, the gallium oxide layers of at least 1 row of dies in the transistor unit share one gallium oxide electrode, and the P-type two-dimensional material layers of at least 1 row of dies in the rest of dies share one P-type two-dimensional material electrode.
Further, the gallium oxide electrode comprises a first bottom layer contact metal and a first top layer metal; the first bottom contact metal and the gallium oxide layer form ohmic contact; the first bottom layer contact metal is made of Ti or Cr, and the first top layer contact metal is made of Au;
the P-type two-dimensional material electrode comprises a second bottom layer contact metal and a second top layer metal; the second bottom contact metal and the P-type two-dimensional material layer form ohmic contact; the material of the second bottom layer contact metal is Pd, and the material of the second top layer contact metal is Au;
the material of the back gate electrode is N-type or P-type heavily doped Si, and Au or Cu evaporated on the lower surface of the heavily doped Si, or an ITO conductive glass or Cu conductive adhesive tape or C conductive adhesive tape stuck on the lower surface of the heavily doped Si;
the dielectric oxide layer is made of SiO 2 Or Al 2 O 3 Or HfO 2 Or ZrO(s) 2 ；
The material of the medium passivation layer is h-BN or SiO 2 Or Al 2 O 3 Or HfO 2 Or Si (or) 3 N 4 。
Further, the thickness of the gallium oxide layer is 10-350nm;
the thickness of the P-type two-dimensional material layer is 5-60nm;
the thickness of the dielectric oxide layer is 30-300nm;
the thickness of the dielectric passivation layer is 10-50nm;
the thickness of the first bottom layer contact metal is 50-200nm, and the thickness of the first top layer metal Au is 100-300nm;
the thickness of the second bottom layer contact metal is 6-30nm, and the thickness of the second top layer metal Au is 60-100nm.
Meanwhile, the invention also provides a preparation method of the dual-band photoelectric detector, which is characterized by comprising the following steps:
step 1, selecting a substrate containing heavily doped Si and a dielectric oxide layer formed on the upper surface of the substrate, and cleaning the substrate;
step 2, preparing a transistor unit on the upper surface of the dielectric oxide layer:
2.1 Stripping unintentional doping of Ga 2 O 3 Or Ga doped with Si or Ge or Sn 2 O 3 The crystal film is adhered on the dielectric oxide layer to obtain a quasi-two-dimensional gallium oxide layer of 10-350nm; realization of Ga using contact lithography or hard mask method 2 O 3 Patterning of thin films, etching Ga using IPC 2 O 3 A thin film implementation array;
2.2 Preparing a gallium oxide electrode on the dielectric oxide layer, and forming ohmic contact with the gallium oxide layer after high-temperature rapid annealing of the gallium oxide electrode;
2.3 Using the grown 5-60nm black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film as a P-type two-dimensional material layer; patterning the P-type two-dimensional film by using a contact lithography or hard mask method, and etching the P-type two-dimensional film by using IPC to realize an array; transferring the P-type two-dimensional material layer onto the dielectric oxide layer by a wet method or a dry method, and partially overlapping the P-type two-dimensional material layer and the gallium oxide layer to form a heterojunction;
2.4 Preparing a P-type two-dimensional material electrode on the dielectric oxide layer to form ohmic contact with the P-type two-dimensional material layer;
step 3, preparing a dielectric passivation layer on the upper surface of the whole formed by the transistor unit and the dielectric oxide layer;
and 4, processing the heavily doped Si substrate on the lower surface of the dielectric oxide layer to prepare a back gate electrode, thereby completing the preparation of the dual-band photoelectric detection device.
Compared with the prior art, the invention has the beneficial effects that:
1) The gallium oxide-two-dimensional P-type van der Waals tunneling transistor and the dual-band photoelectric detection device are manufactured by constructing Ga 2 O 3 And (3) forming a tunneling van der Waals energy band structure by the P-type two-dimensional (2D) material heterojunction, so that the leakage current and subthreshold swing of the prepared TFET are reduced under the condition that the on-state current is not obviously reduced.
2) The gallium oxide-two-dimensional P-type van der Waals tunneling transistor and the dual-band photoelectric detector of the invention are due to Ga 2 O 3 The band gap is wider, the band gap of the selected P-type 2D material is smaller, the selected P-type 2D material is an infrared light-emitting material, and the heterojunction formed can realize dual-band DUV-IR detection; moreover, because the PN junction built-in electric field capable of being regulated and controlled by the grid voltage is constructed under the condition of externally adding the back electrode, the response time of the detector can be effectively reduced, and the responsiveness, sensitivity and communication accuracy of the dual-band DUV-IR detector are improved.
3) The gallium oxide-two-dimensional P-type van der Waals tunneling transistor and the dual-band photoelectric detection device have simple preparation process and are easy to realize array integration.
Drawings
Fig. 1 is a schematic diagram of a gallium oxide-two-dimensional P-type van der waals tunneling transistor according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along A-A of FIG. 1;
FIG. 3 is a schematic illustration of a preparation process according to a first embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a dual band photodetector according to an embodiment of the present invention, the dual band photodetector being implemented using a 4×4 array;
fig. 5 is a schematic structural diagram of a three-dual-band photodetector according to an embodiment of the present invention, where the illustrated dual-band photodetector is implemented using a 4×4 array, where P-type two-dimensional material layers of two left-side die each share a P-type two-dimensional material electrode, and gallium oxide layers of two right-side die each share a gallium oxide electrode.
Reference numerals illustrate:
the semiconductor device comprises a 1-dielectric oxide layer, a 2-gallium oxide layer, a 3-P type two-dimensional material layer, a 4-gallium oxide electrode, a 5-P type two-dimensional material electrode, a 6-back gate electrode and a 7-dielectric passivation layer.
Detailed Description
In order to more clearly illustrate the technical scheme of the invention, the invention is described in detail below with reference to the accompanying drawings and specific embodiments.
The gallium oxide-two-dimensional P-type van der Waals tunneling transistor comprises a dielectric oxide layer, a gallium oxide layer, a P-type two-dimensional material layer, a gallium oxide electrode, a P-type two-dimensional material electrode, a back gate electrode and a dielectric passivation layer. The dual-band photodetector may be a single gallium oxide-two-dimensional P-type van der Waals tunneling transistor or a transistor array composed of a plurality of gallium oxide-two-dimensional P-type van der Waals tunneling transistors.
Example 1
A gallium oxide-two-dimensional P-type van der waals tunneling transistor, as shown in fig. 1 and 2, comprises a dielectric oxide layer 1, a dielectric passivation layer 7, a back gate electrode 6 and a transistor unit, wherein the transistor unit comprises a gallium oxide layer 2, a P-type two-dimensional material layer 3, a gallium oxide electrode 4 and a P-type two-dimensional material electrode 5. The gallium oxide layer 2 and the P-type two-dimensional material layer 3 are positioned on the upper surface of the dielectric oxide layer 1; the gallium oxide layer 2 and the P-type two-dimensional material layer 3 form a heterojunction; ohmic contact is formed between the gallium oxide layer 2 and the gallium oxide electrode 4, and between the P-type two-dimensional material layer 3 and the P-type two-dimensional material electrode 5; the gallium oxide electrode 4 is not contacted with the P-type two-dimensional material electrode 5; the dielectric passivation layer 7 is positioned on the upper surface of the whole formed by the dielectric oxide layer 1, the gallium oxide layer 2, the P-type two-dimensional material layer 3, the gallium oxide electrode 4, the P-type two-dimensional material electrode 5 and the dielectric oxide layer 1; the back gate electrode 6 is located on the lower surface of the dielectric oxide layer 1 and is used for connecting with a back gate signal control part.
Wherein the material of the dielectric oxide layer 1 is SiO 2 May also beAl 2 O 3 、HfO 2 、ZrO 2 The lower surface of the dielectric material is used as a back gate oxide layer; the thickness of the dielectric oxide layer 1 is 30-300nm.
The gallium oxide layer 2 material is exfoliated beta-phase-unintentionally doped Ga 2 O 3 Quasi two-dimensional crystal film or Ga doped with any one element of Si, ge and Sn 2 O 3 A quasi-two-dimensional crystal thin film; the thickness of the gallium oxide layer 2 is 10-350nm.
The P-type two-dimensional material layer 3 is Black Phosphorus (BP), beta-phase tellurium (Te) simple substance and 2H-phase molybdenum ditelluride (MoTe) which are transferred on the gallium oxide layer 2 by a wet method or a dry method 2 ) Tungsten diselenide (WSe) 2 ) Platinum diselenide (PdSe) 2 ) A few-layer thin film crystal with equal affinity energy of 3-4.5eV and energy band width of less than 1 eV; the thickness of the P-type two-dimensional material layer 3 is 5-60nm.
The gallium oxide electrode 4 comprises a first bottom layer contact metal and a first top layer metal, wherein the first bottom layer contact metal is made of Ti or Cr, ohmic contact is formed between the first bottom layer contact metal and the gallium oxide layer 2, and the first top layer metal is Au; the thickness of the first bottom contact metal of the gallium oxide layer electrode 4 is 50-200nm, and the thickness of the first top metal Au is 100-300nm.
The P-type two-dimensional material electrode 5 comprises a second bottom layer contact metal and a second top layer metal, wherein the second bottom layer contact metal is Pd, ohmic contact is formed between the second bottom layer contact metal and the P-type two-dimensional material layer 3, and the second top layer metal is Au; the gallium oxide electrode 4 and the P-type two-dimensional material electrode 5 are not overlapped, and the interval between the gallium oxide electrode and the P-type two-dimensional material electrode is larger than 2 mu m; the thickness of the contact metal of the second bottom layer of the P-type two-dimensional material layer 5 is 6-30nm, and the thickness of the Au of the second top layer is 60-100nm.
The back gate electrode 6 includes N-type or P-type heavily doped Si, and a connection layer connected to the back gate signal control portion, where the connection manner between the connection layer and the heavily doped Si may be: plating Au and Cu metals on the surface of the heavily doped Si, or pasting ITO conductive glass or pasting Cu and C conductive adhesive tapes, and connecting the back gate electrode with the back gate signal control part through a probe and the like.
The material of the medium passivation layer 7 (also called medium anti-reflection layer) is h-BN, siO 2 、Si 3 N 4 、HfO 2 Or Al 2 O 3 The thickness of the material is 10-50nm.
As shown in fig. 3, the specific manufacturing steps of the gallium oxide-two-dimensional P-type van der waals tunneling transistor of the present embodiment are as follows:
1) Cleaning oxide layer substrate
Respectively ultrasonically cleaning the heavily doped Si/oxide layer substrate for 5-10min by using acetone, isopropanol and deionized water, and then using a plasma cleaning instrument O 2 100sccm 250W is processed for 3-5min, the upper surface is used as a dielectric oxide layer 1, and the lower surface is used as a back gate oxide layer.
2)Ga 2 O 3 Material stripping
Mechanical stripping of beta-Ga using tape 2 O 3 The material takes a small amount of Ga 2 O 3 The crystal is adhered to the upper surface of the medium oxide layer 1 after being folded for 5-10 times by the adhesive tape to obtain the quasi-two-dimensional Ga of 10-350nm 2 O 3 The layer (gallium oxide layer 2) is heated by a hot plate at 100deg.C for 10-15min to enhance adhesion, and is ultrasonically cleaned by acetone for 8-10min to clean excessive residual gum.
3)Ga 2 O 3 Preparation of electrode of material (gallium oxide electrode 4)
Designing and preparing Ga using electron beam lithography 2 O 3 Electrode pattern, wherein the thickness of selected photoresist is more than 900 μm, the accelerating voltage is more than 25KV, such as spin coating of photoresist PMMA617.08/PMMA672.06, 4000-6000r/min respectively, heating at 180deg.C for 2min, accelerating voltage of 30KV, and exposure metering of 100-300 μm/cm 2 Developing for 1-3min to make the exposed pattern area clear and sharp, and treating O with oxygen plasma 2 And removing residual glue in the pattern exposure area at 100sccm 250W for 3-5 min.
Continuously evaporating 50-200nm Ti metal and 100-300nm Au metal in one evaporation process by using electron beam evaporation or thermal evaporator at evaporation rate of 0.1nm/min, and ultrasonically stripping with acetone for 10-15min to obtain Ga 2 O 3 Electrodes of the material.
And (3) rapidly annealing for 1-2min at 450-530 ℃ by using a rapid annealing furnace to obtain 2-ohm contact with the gallium oxide layer.
4) Stripping of P-type two-dimensional material
Mechanically stripping the P-type two-dimensional material by using an adhesive tape, and taking a small amount of crystals of the P-type two-dimensional material, such as BP, beta-phase Te simple substance and 2H-phase MoTe 2 Or WSe 2 Or PdSe 2 And (3) adhering the adhesive tape to another cleaned heavily doped Si/oxide layer substrate after multiple folds (10-20 times) of the adhesive tape to obtain a thin layer of 5-60nm P-type two-dimensional material, heating the material for 5-10min at 80 ℃ by using a hot plate to enhance the adhesion, and soaking the material for 5-8min at 70 ℃ by using acetone to remove redundant residual adhesive.
5) Transfer of P-type two-dimensional material
Spin-coating a supporting layer such as PMMA and PPC on a heavily doped Si/oxide layer substrate containing a P-type two-dimensional material, heating at 80 ℃ for 2-5min for solidification, immersing the substrate/the P-type two-dimensional material/the supporting layer in water, and slightly picking up the P-type two-dimensional material/the supporting layer by using tweezers to enable the P-type two-dimensional material/the supporting layer to be separated from the substrate in a hydrophilic manner; using a two-dimensional material transfer platform to move XY and a corner axis theta to transfer the P-type two-dimensional material/support layer and quasi-two-dimensional Ga 2 O 3 The material, electrode/substrate (gallium oxide layer 2, gallium oxide electrode 4/dielectric oxide layer 1) are aligned, then pressed down and fixed and heated at 80 ℃ for 5-10min to form a heterojunction, and acetone is used for soaking at 70 ℃ for 5-8min to remove all the support layer.
6) Preparation of electrode 5 of P-type two-dimensional material
Quasi-two-dimensional Ga using electron beam lithography 2 O 3 Preparing a graph for realizing a P-type two-dimensional material electrode 5 on a dielectric oxide layer 1 (containing an electrode) heterojunction with the P-type two-dimensional material, and Ga 2 O 3 The electrode is not contacted with the electrode 5 of the P-type two-dimensional material, the thickness of the photoresist using the electron beam is more than 200nm, and the accelerating voltage is not more than 20KV; such as spin-coating photoresist PMMA679.03, 2000-3000r/min, heating at 180deg.C for 2min, accelerating voltage 20KV, and exposure metering of 50-200 μm/cm 2 Developing for 10-60s to make the exposed pattern area clear and sharp;
and (3) continuously evaporating 6-30nm of Ti metal and 60-100nm of Au metal in a primary evaporation process by using an electron beam evaporation or thermal evaporation instrument, wherein the evaporation rate is 0.05nm/min, and performing ultrasonic stripping for 5-10min by using acetone after evaporation to obtain the pattern electrode of the P-type two-dimensional material.
7) Protection of passivation layer (dielectric passivation layer 7)
Using BN crystals mechanically stripped by an adhesive tape as a passivation layer, taking a small amount of BN crystals, adhering the BN crystals on a new cleaned heavily doped Si/oxide layer substrate after multiple folds (10-15 times) of the adhesive tape to obtain a BN layer with a thin layer of 10-50nm, heating the BN layer for 5-10min by using a hot plate at 80 ℃ to enhance the adhesion, soaking the BN crystal in acetone at 70 ℃ for 5-8min to remove redundant residual glue, and transferring the BN to the upper surface of an integral device formed by the whole tunneling heterojunction by using the method in the step 5.
8) Preparation of bottom electrode (Back Gate electrode 6)
Spin-coating 500nm photoresist on the upper surface of the prepared device for protection, immersing the heavily doped Si part on the back of the heavily doped Si/oxide layer substrate in 10-20% HF hydrofluoric acid solution for 10-30s to remove SiO on the back surface of the heavily doped Si 2 Washing with pure water for 1-2min, respectively ultrasonically cleaning with acetone and isopropanol for 5-10min to remove the upper surface protective layer, and adhering Cu conductive tape on the lower surface of the Si substrate to connect with the signal control part.
Example two
A dual-band photoelectric detector is realized in an n multiplied by m array form, wherein n and m are integers greater than or equal to 1. As shown in FIG. 4, the array is included in the example in a form of 4X 4, and the array lateral-longitudinal spacing is greater than 20 μm. Of course, other array forms can be designed, and the larger the array scale is, the wider the detection area is.
The array type dual-band photoelectric detection device comprises a dielectric oxide layer 1, a back gate electrode 6, a dielectric passivation layer 7 and a transistor unit arranged on the upper surface of the dielectric oxide layer 1.
The material of the dielectric oxide layer 1 is SiO 2 May also be Al 2 O 3 、HfO 2 、ZrO 2 The lower surface of the dielectric material is used as a back gate oxide layer; the thickness of the dielectric oxide layer 1 is 30-300nm.
The transistor unit comprises a 4×4 die array, and a gallium oxide electrode 4 and a P-type two-dimensional material electrode 5 connected with the die array respectively. Each die comprises a gallium oxide layer 2 and a P-type two-dimensional material layer 3; the gallium oxide layer 2 and the P-type two-dimensional material layer 3 are partially overlapped to form a heterojunction; the gallium oxide electrode 4 forms ohmic contact with the gallium oxide layer 2; the P-type two-dimensional material electrode 5 and the P-type two-dimensional material layer 3 form ohmic contact; the gallium oxide electrode 4 is not in contact with the P-type two-dimensional material electrode 5. The lateral and longitudinal spacing of the die array is greater than 20 μm.
Wherein the gallium oxide layer 2 is exfoliated beta-phase-unintentionally doped Ga 2 O 3 A quasi-two-dimensional crystal thin film, or Ga doped with Si or Ge or Sn 2 O 3 A quasi-two-dimensional crystal thin film; the thickness of the gallium oxide layer 2 is 10-350nm; the P-type two-dimensional material layer 3 is a black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film which is transferred on the gallium oxide layer 2 by a wet method or a dry method; the thickness of the P-type two-dimensional material layer 3 is 5-60nm.
The gallium oxide electrode 4 comprises a first bottom layer contact metal and a first top layer metal, wherein the first bottom layer contact metal is made of Ti or Cr, ohmic contact is formed between the first bottom layer contact metal and the gallium oxide layer 2, and the first top layer metal is Au; the thickness of the first bottom contact metal of the gallium oxide layer electrode 4 is 50-200nm, and the thickness of the first top metal Au is 100-300nm.
The P-type two-dimensional material electrode 5 comprises a second bottom layer contact metal and a second top layer metal, wherein the second bottom layer contact metal is Pd, ohmic contact is formed between the second bottom layer contact metal and the P-type two-dimensional material layer 3, and the second top layer metal is Au; the gallium oxide electrode 4 and the P-type two-dimensional material electrode 5 are not overlapped, and the interval between the gallium oxide electrode and the P-type two-dimensional material electrode is larger than 2 mu m; the thickness of the contact metal of the second bottom layer of the P-type two-dimensional material layer 5 is 6-30nm, and the thickness of the Au of the second top layer is 60-100nm.
The dielectric passivation layer 7 is positioned on the upper surface of the transistor unit and the integral body formed by the dielectric oxide layer 1, and is made of h-BN and SiO 2 、Si 3 N 4 、HfO 2 Or Al 2 O 3 The thickness of the material is 10-50nm.
The back gate electrode 6 is arranged on the lower surface of the dielectric oxide layer 1 and is used for connecting a back gate signal control part; the material of the back gate electrode 6 is N-type or P-type heavily doped Si, and Au or Cu evaporated on the lower surface of the N-type or P-type heavily doped Si, or stuck ITO conductive glass, or stuck Cu or C conductive adhesive tape.
The specific manufacturing steps of the dual-band photoelectric detection device provided by the embodiment are as follows:
1) Cleaning oxide layer substrate
Respectively ultrasonically cleaning the heavily doped Si/oxide layer substrate for 5-10min by using acetone, isopropanol and deionized water, and then using a plasma cleaning instrument O 2 100sccm 250W is processed for 3-5min, the upper surface is used as a dielectric oxide layer 1, and the lower surface is used as a back gate oxide layer.
2)Ga 2 O 3 Material array acquisition
Stripping large area Ga using hydrogen ion knife or the like 2 O 3 300-400nm of film as Ga 2 O 3 Layer (gallium oxide layer 2) and transferred to the upper surface of dielectric oxide layer 1, ga is realized using contact lithography or hard mask method 2 O 3 Patterning of thin films, etching Ga using ICP (inductively coupled plasma etcher) 2 O 3 The film is used for realizing a pattern array, and the array spacing is larger than 20 mu m. Specific parameters are as follows: BCl (binary coded decimal) 3 /Cl 2 Etching gas with power of 30-50W/10-20W and gas flow of 10-25sccm/5-10sccm. And removing the etching glue by using acetone ultrasonic for 10-15 min. Continuing to etch Ga using ICP 2 O 3 The surface of the film array is made to have a surface roughness of less than 0.5nm.
3)Ga 2 O 3 Preparation of electrode of Material array (gallium oxide electrode 4)
Designing and using contact lithography or hard mask methods to realize Ga 2 O 3 Electrode pattern, wherein the thickness of the photoresist is greater than 1 μm, such as continuous spin coating SF6/AZ701 photoresist, 2000-5000r/min,200 deg.C 3min/90 deg.C 1min, exposure time 10-20s, development time 50-80s, O treatment with oxygen plasma 2 And removing residual glue in the pattern area 100sccm 250W3-5 min.
Continuously evaporating 50-200nm Ti metal and 100-300nm Au metal in one evaporation process by using electron beam evaporation or thermal evaporator at evaporation rate of 0.1nm/min, and ultrasonically stripping with acetone for 10-15min to obtain Ga 2 O 3 And a patterned electrode of the array.
And (3) rapidly annealing for 1-2min at 450-530 ℃ by using a rapid annealing furnace to obtain 2-ohm contact with the gallium oxide layer.
4) Preparation of P-type two-dimensional material array
Transferring a P-type two-dimensional thin film material (thickness 5-60 nm) prepared by CVD (chemical vapor deposition) onto another cleaned heavily doped Si/oxide layer substrate, wherein the P-type two-dimensional thin film material comprises BP, beta-phase Te simple substance and 2H-phase MoTe 2 Or WSe 2 Or PdSe 2 The film is heated at 80deg.C for 5-10min to enhance adhesion, and soaked in acetone at 70deg.C for 5-8min to remove excessive residual gum.
Patterning of the P-type two-dimensional film is achieved by using a contact lithography or hard mask method, patterning arrays are achieved by etching the P-type two-dimensional film by using ICP, and the array spacing is larger than 20 mu m, wherein etching parameters are as follows: SF (sulfur hexafluoride) 6 Etching gas with power of 5-20W and gas flow of 10-25sccm.
5) Transfer of P-type two-dimensional material arrays
Spin-coating a supporting layer such as PMMA (polymethyl methacrylate) and PPC (polymethyl methacrylate) on a heavily doped Si/oxide layer substrate containing a P-type two-dimensional material array, heating at 80 ℃ for 2-5min, immersing the substrate/the P-type two-dimensional material array/the supporting layer in water, and slightly lifting the P-type two-dimensional material array/the supporting layer by using tweezers to enable the P-type two-dimensional material array/the supporting layer to be hydrophilic and separated from the substrate; moving XY and corner axis θ using a two-dimensional material transfer stage to align a P-type two-dimensional material array/support layer with a quasi-two-dimensional Ga 2 O 3 The material array, electrodes/substrate (gallium oxide layer 2, gallium oxide electrode 4/dielectric oxide layer 1) are aligned, then pressed down and fixed and heated at 80 ℃ for 5-10min to form a heterojunction array, and acetone is used for soaking at 70 ℃ for 5-8min to remove all supporting layers.
6) Preparation of electrode of P-type two-dimensional material array (P-type two-dimensional material electrode 5)
Use of electron beam lithography to contain quasi-two-dimensional Ga 2 O 3 Preparing a P-type two-dimensional material electrode 5 graph and Ga on a dielectric oxide layer 1 of a heterojunction array of the P-type two-dimensional material 2 O 3 The electrode is not contacted with the electrode 5 of the P-type two-dimensional material, wherein the thickness of photoresist using electron beams is more than 200nm, and the accelerating voltage is not more than 20KV; such as spin-on photoresist PMMA679.03 2000-3000r/min, heating at 180deg.C for 2min, accelerating voltage of 20KV, and exposure metering of 50-200 μm/cm 2 Developing for 10-60s to make the exposed pattern area clear and sharp;
and (3) continuously evaporating 6-30nm of Ti metal and 60-100nm of Au metal in a primary evaporation process by using an electron beam evaporator or a thermal evaporator, wherein the evaporation rate is 0.05nm/min, and performing ultrasonic stripping for 5-10min by using acetone after evaporation so as to obtain the pattern electrode of the P-type two-dimensional material array.
7) Preparation of passivation layer (dielectric passivation layer 7)
With ozone and Hf [ N (CH) 3 ) 2 ] 4 As a source, passivating 10-50nm of HfO by atomic force deposition (ALD) standard process at a growth temperature of 150-350 DEG C 2 And the film is used for covering the whole upper surface of the device array formed by the whole tunneling heterojunction array.
8) Preparation of bottom electrode (Back Gate electrode 6)
Spin-coating 500nm photoresist on the upper surface of the prepared device array for protection, immersing the heavily doped Si part on the back of the heavily doped Si/oxide layer substrate in 10-20% HF hydrofluoric acid solution for 10-30s to remove SiO on the back surface of the heavily doped Si 2 Washing with pure water for 1-2min and blow-drying; evaporating Cu metal at 100-300nm on the lower surface of the Si substrate by using a thermal evaporator, wherein the evaporation rate is 1nm/min; respectively ultrasonically cleaning the device array for 5-10min by using acetone and isopropanol to remove the surface protection layer on the device array; and a Cu conductive adhesive tape is stuck on the lower surface of the Cu metal and is connected with the signal control part.
Example III
As shown in fig. 5, the difference between the present embodiment and the second embodiment is that: in order to save wiring and chip space, two left-side tube cores in the tube core array of the transistor unit respectively share one P-type two-dimensional material electrode 5, and two right-side tube cores respectively share one gallium oxide electrode 4. In other embodiments, it may be designed that one gallium oxide electrode 4 or one P-type two-dimensional material electrode 5 is shared by one die, and other electrode sharing manners may be adopted as the practical wiring space allows.
The gallium oxide-two-dimensional P-type Van der Waals provided by the inventionThe preparation process of the tunneling transistor and the dual-band photoelectric detector is simple, and the array integration is easy to realize; by setting up Ga 2 O 3 -P-type two-dimensional (2D) material heterojunction forming a tunnelable van der waals band structure reducing leakage current and subthreshold swing; because gallium oxide has wider band gap, is a deep ultraviolet luminescent material, the band gap of the selected P-type two-dimensional material is smaller, and is an infrared luminescent material, the heterojunction can realize dual-band DUV-IR detection; and a PN junction built-in electric field capable of being regulated and controlled by grid voltage is constructed under the condition of externally adding a back electrode, so that the response time of the detector can be effectively reduced, and the responsivity, sensitivity and communication accuracy of the dual-band DUV-IR detector are improved.
The foregoing description of the preferred embodiments of the present invention is provided for illustration only and not for limitation, and any modifications by those skilled in the art based on the main technical concept of the present invention will fall within the technical scope of the present invention.

Claims (10)

1. A gallium oxide-two-dimensional P-type van der waals tunneling transistor, characterized by: the transistor comprises a dielectric oxide layer (1), a dielectric passivation layer (7), a back gate electrode (6) and a transistor unit arranged on the upper surface of the dielectric oxide layer (1);
the transistor unit comprises an active region gallium oxide layer (2), a P-type two-dimensional material layer (3), and a gallium oxide electrode (4) and a P-type two-dimensional material electrode (5) which are respectively connected with the gallium oxide layer (2) and the P-type two-dimensional material layer (3);
the gallium oxide layer (2) is partially overlapped with the P-type two-dimensional material layer (3) to form a heterojunction; the gallium oxide electrode (4) and the gallium oxide layer (2) form ohmic contact; the P-type two-dimensional material electrode (5) and the P-type two-dimensional material layer (3) form ohmic contact;
the medium passivation layer (7) is positioned on the upper surface of the whole formed by the gallium oxide layer (2), the P-type two-dimensional material layer (3), the gallium oxide electrode (4), the P-type two-dimensional material electrode (5) and the medium oxidation layer (1);
the back gate electrode (6) is arranged on the lower surface of the dielectric oxide layer (1);
the gallium oxide layer (2) is unintentionally dopedGa of (2) 2 O 3 Quasi-two-dimensional crystal thin film, or Si-or Ge-or Sn-doped Ga 2 O 3 A quasi-two-dimensional crystal thin film;
the P-type two-dimensional material layer (3) is a black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film which is transferred on the upper surfaces of the dielectric oxide layer (1) and the partial gallium oxide layer (2) by a wet method or a dry method.
2. Gallium oxide-two-dimensional P-type van der waals tunneling transistor according to claim 1, wherein:
the distance between the gallium oxide electrode (4) and the P-type two-dimensional material electrode (5) is larger than 2 mu m;
the back gate electrode (6) is made of N-type or P-type heavily doped Si, and Au or Cu evaporated on the lower surface of the heavily doped Si, or an ITO conductive glass or Cu conductive adhesive tape or a C conductive adhesive tape stuck on the lower surface of the heavily doped Si.
3. Gallium oxide-two-dimensional P-type van der waals tunneling transistor according to claim 1 or 2, characterized in that:
the gallium oxide electrode (4) comprises a first bottom layer contact metal and a first top layer metal; the first bottom contact metal and the gallium oxide layer (2) form ohmic contact; the first bottom layer contact metal is made of Ti or Cr, and the first top layer contact metal is made of Au;
the P-type two-dimensional material electrode (5) comprises a second bottom layer contact metal and a second top layer metal; the second bottom contact metal forms ohmic contact with the P-type two-dimensional material layer (3); the material of the second bottom layer contact metal is Pd, and the material of the second top layer contact metal is Au;
the material of the dielectric oxide layer (1) is SiO 2 Or Al 2 O 3 Or HfO 2 Or ZrO(s) 2 ；
The material of the medium passivation layer (7) is h-BN or SiO 2 Or Al 2 O 3 Or HfO 2 Or Si (or) 3 N 4 。
4. A gallium oxide-two-dimensional P-type van der waals tunneling transistor according to claim 3, wherein:
the thickness of the gallium oxide layer (2) is 10-350nm;
the thickness of the P-type two-dimensional material layer (3) is 5-60nm;
the thickness of the dielectric oxide layer (1) is 30-300nm;
the thickness of the medium passivation layer (7) is 10-50nm;
the thickness of the first bottom layer contact metal is 50-200nm, and the thickness of the first top layer metal Au is 100-300nm;
the thickness of the second bottom layer contact metal is 6-30nm, and the thickness of the second top layer metal Au is 60-100nm.
5. The preparation method of the gallium oxide-two-dimensional P-type van der Waals tunneling transistor is characterized by comprising the following steps of:
step 1, selecting a substrate containing heavily doped Si and a dielectric oxide layer (1) formed on the upper surface, and cleaning;
step 2, preparing a transistor unit on the upper surface of the dielectric oxide layer (1);
2.1 Beta-phase-unintentionally doped Ga 2 O 3 Thin films, or stripping Si-or Ge-or Sn-doped Ga 2 O 3 The crystal film is adhered on the medium oxide layer (1) to obtain a quasi-two-dimensional gallium oxide layer (2) with the thickness of 10-350nm;
2.2 Preparing a gallium oxide electrode (4) on the dielectric oxide layer (1), and forming ohmic contact with the gallium oxide layer (2) after high-temperature rapid annealing of the gallium oxide electrode (4);
2.3 Peeling or growing a P-type two-dimensional material layer (3) of a black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film with the wavelength of 5-60nm; transferring the P-type two-dimensional material layer (3) onto the dielectric oxide layer (1) by a wet method or a dry method, so that the P-type two-dimensional material layer and the gallium oxide layer (2) are partially overlapped to form a heterojunction;
2.4 Preparing a P-type two-dimensional material electrode (5) on the dielectric oxide layer (1) to form ohmic contact with the P-type two-dimensional material layer (3);
step 3, growing or transferring the dielectric passivation layer (7) to the upper surface of the transistor unit and the integral formed by the dielectric oxide layer (1);
and 4, processing the heavily doped Si substrate on the lower surface of the dielectric oxide layer (1) to prepare a back gate electrode (6), thereby completing the preparation of the gallium oxide-two-dimensional P-type Van der Waals tunneling transistor.
6. A dual band photodetector device, characterized by: the transistor comprises a dielectric oxide layer (1), a back gate electrode (6), a dielectric passivation layer (7) and a transistor unit arranged on the upper surface of the dielectric oxide layer (1);
the transistor unit comprises an n multiplied by m die array formed by dies, and a gallium oxide electrode (4) and a P-type two-dimensional material electrode (5) which are correspondingly connected with the die array, wherein n and m are integers which are more than or equal to 1; the row spacing and the column spacing of the die array are both greater than 20 μm;
the die comprises an active area gallium oxide layer (2) and a P-type two-dimensional material layer (3); the gallium oxide layer (2) is partially overlapped with the P-type two-dimensional material layer (3) to form a heterojunction; the gallium oxide electrode (4) and the gallium oxide layer (2) form ohmic contact; the P-type two-dimensional material electrode (5) and the P-type two-dimensional material layer (3) form ohmic contact;
the dielectric passivation layer (7) is positioned on the upper surface of the whole formed by the die array, the gallium oxide electrode (4), the P-type two-dimensional material electrode (5) and the dielectric oxide layer (1);
the back gate electrode (6) is arranged on the lower surface of the dielectric oxide layer (1);
the gallium oxide layer (2) is unintentionally doped Ga 2 O 3 Quasi-two-dimensional crystal thin film, or Si-or Ge-or Sn-doped Ga 2 O 3 A quasi-two-dimensional crystal thin film;
the P-type two-dimensional material layer (3) is a black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten diselenide or platinum diselenide film which is transferred on the upper surfaces of the dielectric oxide layer (1) and the partial gallium oxide layer (2) by a wet method or a dry method.
7. The dual band photodetector device of claim 6, wherein:
the gallium oxide layers (2) of at least 1 column of dies in the transistor unit share one gallium oxide electrode (4), or the P-type two-dimensional material layers (3) share one P-type two-dimensional material electrode (5);
or the gallium oxide layers (2) of at least 1 column of the tube cores in the transistor unit share one gallium oxide electrode (4), and the P-type two-dimensional material layers (3) of at least 1 column of the tube cores in the rest tube cores share one P-type two-dimensional material electrode (5);
or the gallium oxide layers (2) of at least 1 row of dies in the transistor unit share one gallium oxide electrode (4), or the P-type two-dimensional material layers (3) share one P-type two-dimensional material electrode (5);
or the gallium oxide layers (2) of at least 1 row of the dies in the transistor unit share one gallium oxide electrode (4), and the P-type two-dimensional material layers (3) of at least 1 row of the dies in the rest dies share one P-type two-dimensional material electrode (5).
8. The dual band photodetector device of claim 6 or 7, wherein:
the gallium oxide electrode (4) comprises a first bottom layer contact metal and a first top layer metal; the first bottom contact metal and the gallium oxide layer (2) form ohmic contact; the first bottom layer contact metal is made of Ti or Cr, and the first top layer contact metal is made of Au;
the P-type two-dimensional material electrode (5) comprises a second bottom layer contact metal and a second top layer metal; the second bottom contact metal forms ohmic contact with the P-type two-dimensional material layer (3); the material of the second bottom layer contact metal is Pd, and the material of the second top layer contact metal is Au;
the material of the back gate electrode (6) is N-type or P-type heavily doped Si, and Au or Cu evaporated on the lower surface of the heavily doped Si, or an ITO conductive glass or Cu conductive adhesive tape or C conductive adhesive tape stuck on the lower surface of the heavily doped Si;
the material of the dielectric oxide layer (1) is SiO 2 Or Al 2 O 3 Or HfO 2 Or ZrO(s) 2 ；
The material of the medium passivation layer (7) is h-BN or SiO 2 Or Al 2 O 3 Or HfO 2 Or Si (or) 3 N 4 。
9. The dual band photodetector device of claim 8, wherein:
the thickness of the gallium oxide layer (2) is 10-350nm;
the thickness of the P-type two-dimensional material layer (3) is 5-60nm;
the thickness of the dielectric oxide layer (1) is 30-300nm;
the thickness of the medium passivation layer (7) is 10-50nm;
the thickness of the first bottom layer contact metal is 50-200nm, and the thickness of the first top layer metal Au is 100-300nm;
the thickness of the second bottom layer contact metal is 6-30nm, and the thickness of the second top layer metal Au is 60-100nm.
10. The preparation method of the dual-band photoelectric detection device is characterized by comprising the following steps of:
step 1, selecting a substrate containing heavily doped Si and a dielectric oxide layer (1) formed on the upper surface, and cleaning;
step 2, preparing a transistor unit on the upper surface of the dielectric oxide layer (1):
2.1 Stripping unintentional doping of Ga 2 O 3 Or Ga doped with Si or Ge or Sn 2 O 3 The crystal film is adhered on the medium oxide layer (1) to obtain a quasi-two-dimensional gallium oxide layer (2) with the thickness of 10-350nm; realization of Ga using contact lithography or hard mask method 2 O 3 Patterning of thin films, etching Ga using IPC 2 O 3 A thin film implementation array;
2.2 Preparing a gallium oxide electrode (4) on the dielectric oxide layer (1), and forming ohmic contact with the gallium oxide layer (2) after high-temperature rapid annealing of the gallium oxide electrode (4);
2.3 Using a grown 5-60nm black phosphorus or beta-phase tellurium simple substance or 2H-phase molybdenum ditelluride or tungsten ditelluride or platinum ditelluride as a P-type two-dimensional material layer (3), using a contact photoetching or hard mask method to realize the patterning of the P-type two-dimensional film, and using IPC to etch the P-type two-dimensional film to realize an array; transferring the P-type two-dimensional material layer (3) onto the dielectric oxide layer (1) by a wet method or a dry method, and enabling the P-type two-dimensional material layer to partially overlap with the gallium oxide layer (2) to form a heterojunction;
2.4 Preparing a P-type two-dimensional material electrode (5) on the dielectric oxide layer (1) to form ohmic contact with the P-type two-dimensional material layer (3);
step 3, preparing a dielectric passivation layer (7) on the upper surface of the transistor unit and the integral body formed by the dielectric oxide layer (1);
and 4, processing the heavily doped Si substrate on the lower surface of the dielectric oxide layer (1) to prepare a back gate electrode (6) so as to complete the preparation of the dual-band photoelectric detection device.
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