CN113965288A - Method and device for improving precision time protocol PTP time synchronization precision - Google Patents

Method and device for improving precision time protocol PTP time synchronization precision Download PDF

Info

Publication number
CN113965288A
CN113965288A CN202111245859.5A CN202111245859A CN113965288A CN 113965288 A CN113965288 A CN 113965288A CN 202111245859 A CN202111245859 A CN 202111245859A CN 113965288 A CN113965288 A CN 113965288A
Authority
CN
China
Prior art keywords
offset
time
ptp
drift
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111245859.5A
Other languages
Chinese (zh)
Other versions
CN113965288B (en
Inventor
蒋华
李占斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kungao New Core Microelectronics Jiangsu Co ltd
Original Assignee
Kungao New Core Microelectronics Jiangsu Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kungao New Core Microelectronics Jiangsu Co ltd filed Critical Kungao New Core Microelectronics Jiangsu Co ltd
Priority to CN202111245859.5A priority Critical patent/CN113965288B/en
Publication of CN113965288A publication Critical patent/CN113965288A/en
Application granted granted Critical
Publication of CN113965288B publication Critical patent/CN113965288B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0638Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658Clock or time synchronisation among packet nodes
    • H04J3/0661Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention provides a method and a device for improving precision time synchronization precision of a Precision Time Protocol (PTP), wherein the method comprises the following steps: the chip MAC/PHY module detects and identifies the PTP message and records a time stamp of the PTP message, wherein the time stamp of receiving the Sync message is t 2; the PTP protocol stack calculates a time Offset and a frequency Offset Drift based on the PTP message timestamp, and sends the calculated time Offset and frequency Offset Drift to the chip PTP module; the chip PTP module receives the time stamp t2, the time Offset and the frequency Offset Drift sent by the PTP protocol stack, acquires the current time stamp t2', and compensates the time Offset based on the time stamps t2 and t2' and the frequency Offset Drift to acquire a new time Offsetnew(ii) a Chip PTP module setting frequency deviation Drift and new time deviation OffsetnewTo the chip. The invention effectively improves the precision of PTP time synchronization by compensating the time offset error caused by the delay of software calculation and hardware configuration and the frequency offset.

Description

Method and device for improving precision time protocol PTP time synchronization precision
Technical Field
The invention relates to the technical field of Ethernet time synchronization, in particular to a method and a device for improving the precision of precision time protocol PTP time synchronization.
Background
PTP (precision time protocol) defined by IEEE1588 is a time synchronization technical solution widely used at present to meet the requirement of time synchronization of a distribution network for measurement and control applications. The network clock synchronization mainly comprises frequency synchronization and time synchronization, and the PTP calculates and restores a local clock and frequency by recording timestamps of specific PTP protocol messages entering and leaving equipment. High-precision time synchronization can be realized through hardware assistance, and with the improvement of software and hardware technologies, the time synchronization precision of the PTP can reach tens of nanoseconds.
The PTP calculates the path delay and the time offset between the master device and the slave device by recording the time stamp generated when the event message is exchanged between the master device and the slave device, thereby realizing the time and frequency synchronization between the master device and the slave device.
At present, there are two ways to realize the time synchronization of PTP: the latency request response E2E (End to End) calculates the time difference according to the overall path latency between the master and slave clocks, and the Peer latency P2P (Peer to Peer) calculates the time difference according to each link latency between the master and slave clocks.
However, in practice, a certain time delay is generated from the time Offset and the frequency Offset Drift calculated by running the PTP software protocol stack on the CPU to the clock correction module configured with the FPGA or ASIC chip, the time Offset is not accurate when the clock correction module configured with the chip is configured due to the frequency Offset Drift, and the time synchronization precision is not high enough due to errors introduced by software calculation and hardware configuration delay.
Disclosure of Invention
The invention mainly solves the problem of how to compensate the time offset error caused by the delay of software calculation and hardware configuration and frequency offset in a PTP time synchronization system, thereby improving the precision of PTP time synchronization. In order to solve the technical problems, the invention discloses a method and a device for improving the precision of PTP time synchronization of a precision time protocol, which can improve the precision of PTP time synchronization by compensating time offset errors caused by software calculation, delay of hardware configuration and frequency offset when time offset is configured in hardware in a PTP time synchronization system.
In order to achieve the above object, the technical solution of the present invention provides a method for improving precision time synchronization precision of precision time protocol PTP, which comprises the following steps:
the chip MAC/PHY module detects and identifies the PTP message and records a time stamp of the PTP message, wherein the time stamp of receiving the Sync message is t 2;
the PTP protocol stack calculates a time Offset and a frequency Offset Drift based on the PTP message timestamp, and sends the calculated time Offset and frequency Offset Drift to the chip PTP module;
the chip PTP module receives the time stamp t2, the time Offset and the frequency Offset Drift sent by the PTP protocol stack, acquires the current time stamp t2', and compensates the time Offset based on the time stamps t2 and t2' and the frequency Offset Drift to acquire a new time Offsetnew
Chip PTP module setting frequency deviation Drift and new time deviation OffsetnewTo the chip.
In a further aspect, a new time Offset is obtainednewThe method comprises the following steps:
the time deviation due to the frequency deviation Drift over the [ t2, t2' ] period is calculated as:
Offset' = (t2'-t2)*Drift;
the time offset that the actual hardware needs to be configured is thus:
Offsetnew= Offset + Offset' = Offset +(t2'-t2)* Drift。
in a further technical solution, the PTP message timestamp includes: sync message transmission timestamp t1, Sync message arrival timestamp t2, Delay _ Req message transmission timestamp t3, and Delay _ Req message reception timestamp t 4.
In a further aspect, calculating the time Offset includes:
the average path delay between the master and slave devices is calculated as: delay = [ (t 2-t 1) + (t 4-t 3) ]/2 = [ (t 4-t 1) - (t 3-t 2) ]/2; and
calculating the time deviation of the master device and the slave device as follows:
Offset = t2-t1-Delay = [(t2 – t1) + (t3 – t4)]/2。
in a further aspect, calculating the frequency deviation Drift includes:
and sending a Sync message to the slave node at regular time by the master device, and comparing the sending time interval delta 1 of the Sync message and the time interval delta 2 of reaching the slave device for multiple times to obtain the frequency deviation of the master device and the slave device as Drift = (delta 2-delta 1)/delta 2.
The technical scheme of the invention also provides a device for improving the precision of the precision time protocol PTP time synchronization, which comprises:
the PTP message timestamp recording module is used for detecting and identifying a PTP message through the chip MAC/PHY module and recording a PTP message timestamp, wherein the timestamp of receiving a Sync message is t 2;
the Offset calculation module is used for calculating the time Offset and the frequency Offset Drift based on the PTP message timestamp through the PTP protocol stack and sending the calculated time Offset and the calculated frequency Offset Drift to the chip PTP module;
a time deviation compensation module, configured to receive the time stamp t2, the time deviation Offset, and the frequency deviation Drift sent by the PTP protocol stack through the chip PTP module, obtain a current time stamp t2', and then compensate the time deviation Offset by the chip PTP module based on the time stamps t2 and t2' and the frequency deviation Drift to obtain a new time deviation Offsetnew
A deviation setting module for setting a frequency deviation Drift and a new time deviation Offset through the chip PTP modulenewTo the chip.
In a further aspect, a new time Offset is obtained in the time Offset compensation modulenewThe method comprises the following steps:
the time deviation due to the frequency deviation Drift over the [ t2, t2' ] period is calculated as:
Offset' = (t2'-t2)*Drift;
the time offset that the actual hardware needs to be configured is thus:
Offsetnew= Offset + Offset' = Offset +(t2'-t2)* Drift。
in a further technical solution, the PTP message timestamp recorded by the PTP message timestamp recording module includes: sync message transmission timestamp t1, Sync message arrival timestamp t2, Delay _ Req message transmission timestamp t3, and Delay _ Req message reception timestamp t 4.
In a further aspect, in the Offset calculation module, calculating the time Offset includes:
the average path delay between the master and slave devices is calculated as: delay = [ (t 2-t 1) + (t 4-t 3) ]/2 = [ (t 4-t 1) - (t 3-t 2) ]/2; and
calculating the time deviation of the master device and the slave device as follows:
Offset = t2-t1-Delay = [(t2 – t1) + (t3 – t4)]/2。
in a further aspect, the calculating the frequency deviation Drift in the deviation calculating module includes:
and sending a Sync message to the slave node at regular time by the master device, and comparing the sending time interval delta 1 of the Sync message and the time interval delta 2 of reaching the slave device for multiple times to obtain the frequency deviation of the master device and the slave device as Drift = (delta 2-delta 1)/delta 2.
The invention compensates the time offset error caused by software calculation, hardware configuration delay and frequency offset when the hardware configuration time offset in the PTP time synchronization system, thereby effectively improving the precision of PTP time synchronization.
Drawings
FIG. 1 is a schematic diagram of a time synchronization manner of a delay request corresponding E2E mechanism;
FIG. 2 is a schematic diagram of the time synchronization manner of the peer delay P2P mechanism;
FIG. 3 is a schematic diagram of a frequency synchronization scheme;
fig. 4 is a flowchart of the time offset compensation method of the present invention.
Detailed Description
The technical solution of the present invention will be further described with reference to the following specific examples, but the present invention is not limited to these examples.
The PTP calculates the path delay and the time offset between the master device and the slave device by recording the time stamp generated when the event message is exchanged between the master device and the slave device, thereby realizing the time and frequency synchronization between the master device and the slave device.
At present, there are two ways to realize the time synchronization of PTP: the latency request response E2E (End to End) calculates the time difference according to the overall path latency between the master and slave clocks, and the Peer latency P2P (Peer to Peer) calculates the time difference according to each link latency between the master and slave clocks. Referring to fig. 1 and 2, an E2E time synchronization manner and a P2P time synchronization manner are shown, respectively.
Specifically, referring to fig. 1, taking E2E time synchronization as an example, the average path Delay between the master device and the slave device is calculated by the device obtaining four timestamps t1, t2, t3, and t4 sent and received by Sync and Delay _ Req packets:
Delay = [(t2 – t1) + (t4 – t3)]/2 = [(t4 – t1) – (t3 – t2)]/2
and further calculating the time offset of the master device and the slave device as follows:
Offset = t2-t1-Delay = [(t2 – t1) + (t3 – t4)]/2。
the slave device then uses this time offset to correct the local clock so that the time between the master and slave devices is synchronized.
Referring to fig. 3, in the frequency synchronization, a master device sends a Sync message to a slave node at regular time, and compares a sending time interval Δ 1 of the Sync message with a time interval Δ 2 of reaching the slave device multiple times, so as to obtain a frequency offset of the master device and the slave device as follows:
Drift = (Δ2 -Δ1)/Δ2。
however, as mentioned in the background section, in practice, there is a certain delay from the time Offset and the frequency Offset Drift calculated by running the PTP software protocol stack on the CPU to the clock correction module configured with the FPGA or ASIC chip, the time Offset when the clock correction module configured with the chip is inaccurate due to the frequency Offset Drift, and the time synchronization accuracy is not high enough due to the error introduced by the delay of the software calculation and the hardware configuration.
Therefore, the invention provides a method for improving the precision of PTP time synchronization by compensating the time offset error caused by software calculation, hardware configuration delay and frequency offset when the hardware configuration time offset is configured in a PTP time synchronization system.
Assuming that the time when the chip MAC/PHY module receives the Sync message is t2, the actual time when the PTP software protocol stack calculates the time Offset and the frequency Offset Drift according to the sending and receiving times of the PTP messages and sends the calculated time Offset and frequency Offset Drift to the chip PTP module is t2', the time Offset error caused by the frequency Offset Drift in the [ t2, t2' ] time period is:
Offset' = (t2'-t2)*Drift
the time offset that the actual hardware needs to be configured is thus:
Offsetnew= Offset + Offset’ = Offset +(t2'-t2)* Drift
the Offset, t2 and Drift parameters are calculated by the PTP software protocol stack and sent to the chip PTP hardware module, and the t2' parameter is a current timestamp obtained when the chip PTP hardware module receives the software protocol stack configuration parameters.
Referring to fig. 4, there is shown a method of compensating for time offset errors introduced by delays and frequency offsets due to software calculations and hardware configuration in a PTP time synchronization system of the present invention, comprising several processing steps including:
(1) and the chip MAC/PHY module detects and identifies the PTP message.
(2) And the chip PTP module records the arrival time stamp of the PTP message, and the Sync message is t 2.
(3) The PTP software protocol stack receives the Sync message t2 timestamp and other message timestamps, calculates the offset and the Drift, and sends the offset and the Drift to the chip PTP module.
(4) The chip PTP module receives t2, Offset and Drift sent by the software protocol stack, acquires the current timestamp t2', and compensates and calculates the new time Offsetnew= Offset+(t2'-t2)*Drift。
(5) Chip PTP module set Drift and new OffsetnewTo the chip.
In an embodiment of the present invention, a method for improving precision of precision time protocol PTP time synchronization is provided, which includes the following steps:
the chip MAC/PHY module detects and identifies the PTP message and records a time stamp of the PTP message, wherein the time stamp of receiving the Sync message is t 2;
the PTP protocol stack calculates a time Offset and a frequency Offset Drift based on the PTP message timestamp, and sends the calculated time Offset and frequency Offset Drift to the chip PTP module;
the chip PTP module receives the time stamp t2, the time Offset and the frequency Offset Drift sent by the PTP protocol stack, acquires the current time stamp t2', and compensates the time Offset based on the time stamps t2 and t2' and the frequency Offset Drift to acquire a new time Offsetnew
Chip PTP module setting frequency deviation Drift and new time deviation OffsetnewTo the chip.
In a further aspect, a new time Offset is obtainednewThe method comprises the following steps:
the time deviation due to the frequency deviation Drift over the [ t2, t2' ] period is calculated as:
Offset' = (t2'-t2)*Drift;
the time offset that the actual hardware needs to be configured is thus:
Offsetnew= Offset + Offset' = Offset +(t2'-t2)* Drift。
in a further technical solution, the PTP message timestamp includes: sync message transmission timestamp t1, Sync message arrival timestamp t2, Delay _ Req message transmission timestamp t3, and Delay _ Req message reception timestamp t 4.
In a further aspect, calculating the time Offset includes:
the average path delay between the master and slave devices is calculated as: delay = [ (t 2-t 1) + (t 4-t 3) ]/2 = [ (t 4-t 1) - (t 3-t 2) ]/2; and
calculating the time deviation of the master device and the slave device as follows:
Offset = t2-t1-Delay = [(t2 – t1) + (t3 – t4)]/2。
in a further aspect, calculating the frequency deviation Drift includes:
and sending a Sync message to the slave node at regular time by the master device, and comparing the sending time interval delta 1 of the Sync message and the time interval delta 2 of reaching the slave device for multiple times to obtain the frequency deviation of the master device and the slave device as Drift = (delta 2-delta 1)/delta 2.
In another embodiment of the present invention, there is provided an apparatus for improving precision time synchronization precision of a precision time protocol PTP, including:
the PTP message timestamp recording module is used for detecting and identifying a PTP message through the chip MAC/PHY module and recording a PTP message timestamp, wherein the timestamp of receiving a Sync message is t 2;
the Offset calculation module is used for calculating the time Offset and the frequency Offset Drift based on the PTP message timestamp through the PTP protocol stack and sending the calculated time Offset and the calculated frequency Offset Drift to the chip PTP module;
a time deviation compensation module, configured to receive the time stamp t2, the time deviation Offset, and the frequency deviation Drift sent by the PTP protocol stack through the chip PTP module, obtain a current time stamp t2', and then compensate the time deviation Offset by the chip PTP module based on the time stamps t2 and t2' and the frequency deviation Drift to obtain a new time deviation Offsetnew
A deviation setting module for setting a frequency deviation Drift and a new time deviation Offset through the chip PTP modulenewTo the chip.
In a further aspect, a new time Offset is obtained in the time Offset compensation modulenewThe method comprises the following steps:
the time deviation due to the frequency deviation Drift over the [ t2, t2' ] period is calculated as:
Offset' = (t2'-t2)*Drift;
the time offset that the actual hardware needs to be configured is thus:
Offsetnew= Offset + Offset' = Offset +(t2'-t2)* Drift。
in a further technical solution, the PTP message timestamp recorded by the PTP message timestamp recording module includes: sync message transmission timestamp t1, Sync message arrival timestamp t2, Delay _ Req message transmission timestamp t3, and Delay _ Req message reception timestamp t 4.
In a further aspect, in the Offset calculation module, calculating the time Offset includes:
the average path delay between the master and slave devices is calculated as: delay = [ (t 2-t 1) + (t 4-t 3) ]/2 = [ (t 4-t 1) - (t 3-t 2) ]/2; and
calculating the time deviation of the master device and the slave device as follows:
Offset = t2-t1-Delay = [(t2 – t1) + (t3 – t4)]/2。
in a further aspect, the calculating the frequency deviation Drift in the deviation calculating module includes:
and sending a Sync message to the slave node at regular time by the master device, and comparing the sending time interval delta 1 of the Sync message and the time interval delta 2 of reaching the slave device for multiple times to obtain the frequency deviation of the master device and the slave device as Drift = (delta 2-delta 1)/delta 2.
In a further embodiment of the present invention, there is also provided a PTP time synchronization system which uses the method as described above to achieve time synchronization between a master device and a slave device.
The invention compensates the time offset error caused by software calculation, hardware configuration delay and frequency offset when the hardware configuration time offset in the PTP time synchronization system, thereby effectively improving the precision of PTP time synchronization.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.

Claims (8)

1. A method for improving precision time protocol PTP time synchronization precision is characterized by comprising the following steps:
the chip MAC/PHY module detects and identifies the PTP message and records a time stamp of the PTP message, wherein the time stamp of receiving the Sync message is t 2;
the PTP protocol stack calculates a time Offset and a frequency Offset Drift based on the PTP message timestamp, and sends the calculated time Offset and frequency Offset Drift to the chip PTP module;
the chip PTP module receives the time stamp t2, the time Offset and the frequency Offset Drift sent by the PTP protocol stack, acquires the current time stamp t2', and the chip PTP module is based on timeThe timestamps t2 and t2' and the frequency Offset Drift are compensated for the time Offset to obtain a new time Offsetnew
Chip PTP module setting frequency deviation Drift and new time deviation OffsetnewTo the chip; wherein the content of the first and second substances,
obtaining a new time OffsetnewThe method comprises the following steps:
the time deviation due to the frequency deviation Drift over the [ t2, t2' ] period is calculated as:
Offset' = (t2'-t2)*Drift;
the time offset that the actual hardware needs to be configured is thus:
Offsetnew= Offset + Offset' = Offset +(t2'-t2)* Drift。
2. the method of claim 1, wherein the PTP message timestamp comprises: sync message transmission timestamp t1, Sync message arrival timestamp t2, Delay _ Req message transmission timestamp t3, and Delay _ Req message reception timestamp t 4.
3. The method of claim 2, wherein calculating the time Offset comprises:
the average path delay between the master and slave devices is calculated as: delay = [ (t 2-t 1) + (t 4-t 3) ]/2 = [ (t 4-t 1) - (t 3-t 2) ]/2; and
calculating the time deviation of the master device and the slave device as follows:
Offset = t2-t1-Delay = [(t2 – t1) + (t3 – t4)]/2。
4. the method of claim 3, wherein calculating the frequency deviation Drift comprises:
and sending a Sync message to the slave node at regular time by the master device, and comparing the sending time interval delta 1 of the Sync message and the time interval delta 2 of reaching the slave device for multiple times to obtain the frequency deviation of the master device and the slave device as Drift = (delta 2-delta 1)/delta 2.
5. An apparatus for improving precision of precision time protocol PTP time synchronization, comprising:
the PTP message timestamp recording module is used for detecting and identifying a PTP message through the chip MAC/PHY module and recording a PTP message timestamp, wherein the timestamp of receiving a Sync message is t 2;
the Offset calculation module is used for calculating the time Offset and the frequency Offset Drift based on the PTP message timestamp through the PTP protocol stack and sending the calculated time Offset and the calculated frequency Offset Drift to the chip PTP module;
a time deviation compensation module, configured to receive the time stamp t2, the time deviation Offset, and the frequency deviation Drift sent by the PTP protocol stack through the chip PTP module, obtain a current time stamp t2', and then compensate the time deviation Offset by the chip PTP module based on the time stamps t2 and t2' and the frequency deviation Drift to obtain a new time deviation Offsetnew
A deviation setting module for setting a frequency deviation Drift and a new time deviation Offset through the chip PTP modulenewTo the chip; wherein the content of the first and second substances,
obtaining a new time OffsetnewThe method comprises the following steps:
the time deviation due to the frequency deviation Drift over the [ t2, t2' ] period is calculated as:
Offset' = (t2'-t2)*Drift;
the time offset that the actual hardware needs to be configured is thus:
Offsetnew= Offset + Offset' = Offset +(t2'-t2)* Drift。
6. the apparatus of claim 5, wherein the PTP message timestamps recorded by the PTP message timestamp recording module include: sync message transmission timestamp t1, Sync message arrival timestamp t2, Delay _ Req message transmission timestamp t3, and Delay _ Req message reception timestamp t 4.
7. The apparatus of claim 6, wherein in the Offset calculation module, calculating the time Offset comprises:
the average path delay between the master and slave devices is calculated as: delay = [ (t 2-t 1) + (t 4-t 3) ]/2 = [ (t 4-t 1) - (t 3-t 2) ]/2; and
calculating the time deviation of the master device and the slave device as follows:
Offset = t2-t1-Delay = [(t2 – t1) + (t3 – t4)]/2。
8. the apparatus of claim 7, wherein in the deviation calculation module, calculating the frequency deviation Drift comprises:
and sending a Sync message to the slave node at regular time by the master device, and comparing the sending time interval delta 1 of the Sync message and the time interval delta 2 of reaching the slave device for multiple times to obtain the frequency deviation of the master device and the slave device as Drift = (delta 2-delta 1)/delta 2.
CN202111245859.5A 2021-10-26 2021-10-26 Method and device for improving precision time protocol PTP time synchronization precision Active CN113965288B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111245859.5A CN113965288B (en) 2021-10-26 2021-10-26 Method and device for improving precision time protocol PTP time synchronization precision

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111245859.5A CN113965288B (en) 2021-10-26 2021-10-26 Method and device for improving precision time protocol PTP time synchronization precision

Publications (2)

Publication Number Publication Date
CN113965288A true CN113965288A (en) 2022-01-21
CN113965288B CN113965288B (en) 2023-08-22

Family

ID=79466915

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111245859.5A Active CN113965288B (en) 2021-10-26 2021-10-26 Method and device for improving precision time protocol PTP time synchronization precision

Country Status (1)

Country Link
CN (1) CN113965288B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115347972A (en) * 2022-10-18 2022-11-15 杭州聆巡科技有限公司 Sonar clock synchronization method, device, equipment and storage medium
WO2024047177A1 (en) * 2022-09-01 2024-03-07 OTN Systems N.V. A method for delay monitoring
CN117938298A (en) * 2024-02-02 2024-04-26 中国科学院精密测量科学与技术创新研究院 Device and method for improving PTP time synchronization precision

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101834712A (en) * 2010-04-19 2010-09-15 浙江大学 Method for realizing accurate time synchronization by utilizing IEEE1588 protocol
CN102104476A (en) * 2011-02-21 2011-06-22 中兴通讯股份有限公司 Clock synchronization device and method
US20150092793A1 (en) * 2013-10-01 2015-04-02 Khalifa University of Science, Technology, and Research Method and devices for synchronization
US20170366287A1 (en) * 2015-12-24 2017-12-21 Shenyang Institute of Automation, the Chinese Academy of Sciences Time synchronization error compensation method for multi-hop wireless backhaul network based on ptp

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101834712A (en) * 2010-04-19 2010-09-15 浙江大学 Method for realizing accurate time synchronization by utilizing IEEE1588 protocol
CN102104476A (en) * 2011-02-21 2011-06-22 中兴通讯股份有限公司 Clock synchronization device and method
US20150092793A1 (en) * 2013-10-01 2015-04-02 Khalifa University of Science, Technology, and Research Method and devices for synchronization
US20170366287A1 (en) * 2015-12-24 2017-12-21 Shenyang Institute of Automation, the Chinese Academy of Sciences Time synchronization error compensation method for multi-hop wireless backhaul network based on ptp

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024047177A1 (en) * 2022-09-01 2024-03-07 OTN Systems N.V. A method for delay monitoring
CN115347972A (en) * 2022-10-18 2022-11-15 杭州聆巡科技有限公司 Sonar clock synchronization method, device, equipment and storage medium
CN115347972B (en) * 2022-10-18 2024-01-16 杭州聆巡科技有限公司 Sonar clock synchronization method, device, equipment and storage medium
CN117938298A (en) * 2024-02-02 2024-04-26 中国科学院精密测量科学与技术创新研究院 Device and method for improving PTP time synchronization precision

Also Published As

Publication number Publication date
CN113965288B (en) 2023-08-22

Similar Documents

Publication Publication Date Title
CN113965288B (en) Method and device for improving precision time protocol PTP time synchronization precision
CN102577194B (en) System and method of synchronizing clocks in a distributed network
CN103929293B (en) Asymmetrically-delayed time synchronization method and system
US10868664B2 (en) Minimizing timestamp error in PTP systems
US9112631B2 (en) Method and devices for frequency distribution
US20090086764A1 (en) System and method for time synchronization on network
US9671822B2 (en) Method and devices for time transfer using end-to-end transparent clocks
US9860004B2 (en) Network distributed packet-based synchronization
KR20170095234A (en) Method of synchronising clocks of network devices
US11700072B2 (en) Timing synchronization over cable networks
WO2017101528A1 (en) Method and device for clock link switching and base station
CN104836630A (en) IEEE1588 clock synchronization system and implementation method therefor
JPWO2009119599A1 (en) Clock synchronization system, node, clock synchronization method and program
CN101827098A (en) Processing method and device for time synchronization
EP3044891B1 (en) Method and devices for frequency distribution
WO2021004005A1 (en) Timestamp jitter compensation method and system
JP2012222833A (en) System and method to overcome wander accumulation to achieve precision clock distribution over large networks
CN114586297B (en) Synchronization method and equipment
WO2013086959A1 (en) Method, device, and system for line asymmetry compensation
JP2013098788A (en) Time synchronization system and time synchronization method
CN111342926A (en) Method for optimizing time synchronization of PTP (precision time protocol) in asymmetric network
EP3231110A1 (en) Method and devices for time transfer using end to end transparent clocks
KR20190072745A (en) Stable Network-based Time Synchronization Method
CN112887046B (en) Digital time synchronization method and system for boundary clock and common clock
JP2016152487A (en) Time synchronization method and time synchronization device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant