CN113964200B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113964200B CN113964200B CN202010706145.9A CN202010706145A CN113964200B CN 113964200 B CN113964200 B CN 113964200B CN 202010706145 A CN202010706145 A CN 202010706145A CN 113964200 B CN113964200 B CN 113964200B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000002955 isolation Methods 0.000 claims abstract description 142
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- 238000005192 partition Methods 0.000 claims abstract description 30
- 230000000149 penetrating effect Effects 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 57
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- 238000000151 deposition Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 8
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- 238000004891 communication Methods 0.000 description 6
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- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
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- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000006227 byproduct Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
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- 238000004519 manufacturing process Methods 0.000 description 4
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
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- -1 for example Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 2
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a method for forming the semiconductor structure, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises an isolation region, and a plurality of mutually separated fin parts are arranged on the substrate; forming a first dielectric structure on the substrate and on the surface of the fin part, wherein a plurality of grid openings crossing the fin part are formed in the first dielectric structure, and the grid openings cross the isolation region; forming 1 gate structure within each gate opening; removing the gate structure on the isolation region, and forming a first opening penetrating through the gate structure in the first dielectric structure on the isolation region; removing at least part of the first medium structure between the adjacent first openings, forming a second opening communicated with the first opening between the adjacent first openings, wherein the first opening and the second opening form a partition opening; a strained layer is formed at least within the partition opening. Thus, performance and reliability of the semiconductor structure are improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the semiconductor structure.
Background
In the field of semiconductor technology, as the feature size of integrated circuits is continuously reduced and higher signal transmission speeds of integrated circuits are required, transistors need to have higher drive currents while the size is gradually reduced.
In order to make the semiconductor device have a higher driving current while the size is gradually reduced, a fin field effect transistor structure is generally employed. Because the fin field effect transistor is a similar three-dimensional structure on the substrate, the feature size of the fin field effect transistor is smaller, and the requirement of high integration level can be met. In addition, the grid electrode of the fin field effect transistor is opposite to the upper surface of the fin part, and the two opposite side wall surfaces of the grid electrode and the fin part are opposite, so that when the fin field effect transistor works, a channel region can be formed by the upper surface of the fin part contacted with the grid electrode and the two opposite side wall surfaces, and the mobility of carriers is improved.
However, the performance and reliability of semiconductor devices remain to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a method for forming the semiconductor structure, which are used for improving the performance and the reliability of a semiconductor device.
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: the semiconductor device comprises a substrate, a first semiconductor layer and a second semiconductor layer, wherein the substrate comprises an isolation region, and a plurality of mutually separated fin parts are arranged on the substrate; a plurality of gate structures spanning the fin; the first dielectric structure is positioned on the substrate and is also positioned on the surfaces of the fin part and the gate structure; a partition opening in the first dielectric structure on the isolation region, the partition opening penetrating through the plurality of gate structures along the extending direction of the fin portion, the partition opening including a first opening exposing the sidewall of the gate structure and a second opening located between adjacent first openings and communicating with the first openings; at least a strained layer located within the partition opening.
Optionally, the material of the strained layer comprises silicon nitride.
Optionally, the second opening bottom surface is higher than the first opening bottom surface communicating with the second opening.
Optionally, the second opening bottom surface is lower than or flush with the first opening bottom surface in communication with the second opening.
Optionally, the method further comprises: and the second dielectric structure is positioned on the surface of the strain layer, and the surface of the second dielectric structure is flush with the surface of the first dielectric structure outside the isolation region.
Optionally, the surface of the first dielectric structure on the isolation region is lower than the surface of the first dielectric structure outside the isolation region.
Optionally, the strained layer is further located on a surface of the first dielectric structure on the isolation region.
Optionally, the method further comprises: and the first interconnection structure is positioned in the first dielectric structure and the second dielectric structure, and spans the isolation region and the fins.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises an isolation region, and a plurality of mutually separated fin parts are arranged on the substrate; forming a first dielectric structure on the substrate and on the surface of the fin part, wherein a plurality of grid openings crossing the fin part are formed in the first dielectric structure, and the grid openings cross the isolation region; forming 1 gate structure within each gate opening; removing the gate structure on the isolation region, and forming a first opening penetrating through the gate structure in the first dielectric structure on the isolation region; removing at least part of the first medium structure between the adjacent first openings, forming a second opening communicated with the first opening between the adjacent first openings, wherein the first opening and the second opening form a partition opening; a strained layer is formed at least within the partition opening.
Optionally, the method for removing the gate structure on the isolation region includes: forming a first mask structure on the surface of the first dielectric structure and the surface of the gate structure, wherein the first mask structure exposes the first dielectric structure and the top surface of the gate structure of the isolation region; and etching the gate structure on the isolation region by taking the first mask structure as a mask until the gate structure on the isolation region is removed.
Optionally, the process of etching the gate structure on the isolation region is a plasma etching process.
Optionally, the plasma etching process for etching the gate structure on the isolation region by using the first mask structure as a mask includes: and the etching treatment comprises etching the gate structure on the isolation region by taking the first mask structure as a mask, and the deposition treatment comprises depositing the material of the first dielectric structure on the top surface of the first dielectric structure of the isolation region.
Optionally, the process parameters of the etching treatment include: the etching gas comprises BCl 3、Cl2、He、N2 and O 2, the pressure range is 5 millitorr-100 millitorr, the source radio frequency power is 50 watt-500 watt, the bias voltage is 50 volt-500 volt, and the time is 5 seconds-60 seconds.
Optionally, the process parameters of the deposition process include: the adopted gas comprises CH 4、CH3F、CH3 and Ar, the pressure range is 10 millitorr-100 millitorr, the source radio frequency power is 50 watts-500 watts, and the time is 2 seconds-60 seconds.
Optionally, the method for forming the second opening includes: and etching the first medium structure between the adjacent first openings on the isolation region by taking the first mask structure as a mask.
Optionally, the process of etching the first dielectric structure between adjacent first openings on the isolation region is a plasma etching process.
Optionally, the process parameters of etching the first dielectric structure between adjacent first openings on the isolation region include: the etching gas comprises CF 4、CH3F、N2、O2 and CH 2F2, the pressure range is 5 millitorr-100 millitorr, the source radio frequency power is 50 watts-500 watts, and the bias voltage is 50 volts-500 volts.
Optionally, the method for forming the strain layer includes: forming an initial strain layer on the surface of the first medium structure and in the partition opening; forming an initial second dielectric structure on the surface of the initial strain layer, wherein the surface of the initial second dielectric structure is higher than the surface of the initial strain layer; and flattening the initial second dielectric structure and the initial strain layer until the surface of the first dielectric structure outside the isolation region is exposed, forming the strain layer, and forming a second dielectric structure on the surface of the strain layer of the isolation region.
Optionally, the strained layer is further located on a surface of the first dielectric structure on the isolation region.
Optionally, the method further comprises: forming a third opening in the first dielectric structure and the second dielectric structure, wherein the third opening spans the isolation region and the fin part, and the third opening exposes the top surface of the fin part; a first interconnect structure is formed within the third opening.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
According to the semiconductor structure provided by the technical scheme of the invention, as the strain layer is positioned in the isolation opening, and each first opening penetrates through 1 gate structure, the strain layer is connected with the gate structure penetrated by the first opening, so that the fin part is not only stressed by the gate structure, but also stressed by the strain layer, and meanwhile, as the semiconductor structure comprises the strain layer at least positioned in the isolation opening, the shape of the strain layer can be adjusted by adjusting the position of the bottom surface of the second opening, and therefore, the stress suffered by the fin part is adjusted by adjusting the shape of the strain layer, so as to adjust the electron mobility in the fin part and adjust the starting voltage of the transistor, so that the performance and the reliability of the semiconductor device are improved.
According to the method for forming the semiconductor structure, the first opening penetrating the gate structure is formed in the first medium structure on the isolation region, the second opening communicated with the first opening is formed between the adjacent first openings, the first opening and the second opening form the isolation opening, and the strain layer is formed at least in the isolation opening, so that the strain layer is connected with the gate structure penetrated by the first opening, and the fin portion is subjected to stress provided by the gate structure and also subjected to stress provided by the strain layer. Meanwhile, at least part of the first medium structure between the adjacent first openings is removed to form a second opening, and the second opening is communicated with the first opening, so that the height of the bottom surface of the second opening can be adjusted by adjusting the first medium structure between the removed first openings, and the shape of the isolation opening can be adjusted. The strain layer is formed at least in the isolation opening, so that the shape of the strain layer can be adjusted by adjusting the shape of the isolation opening, and the stress born by the fin part can be adjusted by adjusting the shape of the strain layer so as to adjust the electron mobility of the fin part and the turn-on voltage of the transistor, thereby improving the performance and reliability of the semiconductor device.
Further, since the first mask structure is used as a mask, the plasma etching process for etching the gate structure on the isolation region includes: the etching treatment and the deposition treatment are circulated for a plurality of times, so that the damage to the surface of the first dielectric structure caused by each etching treatment can be repaired through the deposition treatment, and the loss of the first dielectric structure is reduced, and the top surface of the first dielectric structure is flattened after the first opening is formed. Meanwhile, through the deposition treatment circularly carried out with the etching treatment, a first dielectric structure material with thinner thickness can be formed on the top surface of the first dielectric structure during each deposition treatment, so that the first dielectric structure material formed on the top surface of the first dielectric structure can be uniformly lost during each deposition treatment, the top surface of the first dielectric structure after the first opening is formed is more beneficial to being flat, the shape precision of a strain layer formed subsequently can be improved, and the difficulty in adjusting the stress born by the fin part can be reduced.
Further, by adjusting the process parameters of the plasma etching process, when the first mask structure is used as a mask to etch the first dielectric structures on the isolation region, fewer etching byproducts are formed on the surfaces of the first dielectric structures between the first openings, and more etching byproducts are formed on the surfaces of the other first dielectric structures, so that the first dielectric structures between adjacent first openings on the isolation region are etched, and the purpose of adjusting the second openings is achieved.
Drawings
FIGS. 1-3 are schematic diagrams illustrating steps in a process for forming a semiconductor structure;
Fig. 4 to 17 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, performance and reliability of semiconductor structures remain to be improved. The analysis will now be described with reference to specific examples.
Note that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1 to 3 are schematic structural views of steps in a process of forming a semiconductor structure.
Referring to fig. 1 to 2, fig. 1 is a schematic top view of a semiconductor structure, fig. 2 is a schematic cross-sectional view along A-A1 in fig. 1, a substrate 100 is provided, the substrate 100 includes an isolation region B, and the substrate 100 has a plurality of fin structures 101 separated from each other; the first dielectric structure 120 and the plurality of gate structures 110 crossing the fin structure 101 are formed, the first dielectric structure 120 is located on the surfaces of the fin structure 101 and the gate structures 110, and 2 gate structures 110 in the plurality of gate structures 110 cross the isolation region B.
Referring to fig. 3 on the basis of fig. 1, a mask structure (not shown) is formed on the surfaces of the gate structure 110 and the first dielectric structure 120, and the mask structure exposes the gate structure 110 of the isolation region B; etching the gate structure 110 of the isolation region B with the mask structure as a mask until the gate structure 110 of the isolation region B is removed to form an opening (not shown); after the openings are formed, a second dielectric structure (not shown) is formed within the openings, on the surface of the first dielectric structure 120 and on the surface of the gate structure 110.
It should be noted that, for ease of understanding, the first dielectric structure 120 is not shown in fig. 2 and 3.
However, in the above-mentioned scheme, since the gate structures 110 on both sides of the isolation region B are spaced apart by forming the opening, the material structure inside the gate structures 110 after forming the opening, etc. are changed, and thus the stress of the gate structures 110 on both sides of the isolation region B on the fin structure 101 is changed, and thus the electron mobility in the fin structure 101 is changed, so that the turn-on voltage of the transistor is affected, resulting in the performance of the semiconductor structure being affected, and the reliability of the semiconductor structure is reduced.
In order to solve the technical problem, the embodiment of the invention provides a method for forming a semiconductor structure, which forms a strain layer with an adjustable shape by forming a second opening with an adjustable bottom surface height, thereby adjusting the stress born by a fin part to adjust the electron mobility in the fin part and the starting voltage of a transistor to improve the performance and the reliability of a semiconductor device.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 17 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 4 is a schematic top view of a semiconductor structure according to an embodiment of the present invention, and fig. 5 is a schematic cross-sectional view of an isolation region P in a direction X-X1 in fig. 4, where a substrate 200 is provided, and the substrate 200 includes the isolation region P, and a plurality of fins 201 are separated from each other on the substrate 200.
The material of the substrate 200 is a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Wherein the multi-component semiconductor material formed by III-V elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In this embodiment, the method for forming the plurality of fins 201 that are separated from each other includes: providing an initial substrate (not shown); forming a fin layer patterning layer (not shown) on the initial substrate surface, the fin layer exposing a portion of the initial substrate surface; and etching the initial substrate by taking the fin layer patterning layer as a mask until the substrate 200 and a plurality of mutually separated fins 201 on the substrate 200 are formed.
In this embodiment, the process of etching the initial substrate: including a dry etching process or a wet etching process.
Referring to fig. 6 and 7, fig. 6 is a schematic top view of a semiconductor structure according to an embodiment of the present invention, and fig. 7 is a schematic cross-sectional view of an isolation region P in the X-X1 direction in fig. 6, a first dielectric structure 210 is formed on the substrate 200 and on a surface of the fin 201, and a plurality of gate openings 211 crossing the fin 201 are formed in the first dielectric structure 210, where the plurality of gate openings 211 cross the isolation region P.
In this embodiment, the first dielectric structure 210 further includes a plurality of gate openings 211 outside the plurality of gate openings 211 crossing the fin 201.
The gate opening 211 provides space and support for the subsequent formation of a gate structure.
Specifically, in the present embodiment, the number of gate openings 211 crossing the isolation region P is 2.
In other embodiments, the number of gate openings across the isolation region may also be 3 or more than 3.
The purpose of crossing the plurality of gate openings 211 over the isolation region P is to enable a plurality of first openings penetrating the gate structure to be formed subsequently on the isolation region P, so that adjacent first openings can have a first dielectric structure 210 located in the isolation region P, so that a second opening with an adjustable bottom surface height can be formed subsequently in the isolation region P.
The method for forming the first dielectric structure 210 and the gate opening 211 includes: forming a lower layer first dielectric structure (not shown) on the surface of the substrate 200 and a part of the sidewall surface of the fin 201; forming a plurality of dummy gate structures (not shown) crossing the fin 201 on the surface of the lower first dielectric structure, wherein the dummy gate structures cover the top and side wall surfaces of part of the fin 201; forming an initial upper layer first dielectric structure (not shown) on the surface of the lower layer first dielectric structure, wherein the initial upper layer first dielectric structure covers the surface of the fin 201 and the surface of the dummy gate structure; flattening the initial upper first dielectric structure until the top surface of the dummy gate structure is exposed to form an upper first dielectric structure, wherein the lower first dielectric structure and the upper first dielectric structure form the first dielectric structure 210; after the first dielectric structure 210 is formed, the dummy gate structure is removed, and a gate opening 211 is formed in the first dielectric structure 210.
The dummy gate structure has the following functions: space is occupied for the subsequent formation of the gate structure by the post-gate process. The gate opening 211 is used to provide space for the subsequent formation of a gate structure.
The method for forming the pseudo gate structure comprises the following steps: forming a pseudo gate material film covering the surface of the fin 201 on the lower first dielectric structure; and patterning the dummy gate material film until the surface of the lower first dielectric structure is exposed, and forming a dummy gate structure crossing the fin 201 on the surface of the lower first dielectric structure, wherein the top surface of the dummy gate structure is higher than the top surface of the fin 201.
In this embodiment, the method for forming a semiconductor structure further includes: after the dummy gate structure is formed, before the upper first dielectric structure is formed, source-drain doped layers (not shown in the figure) are formed in the fin portions 201 at two sides of the dummy gate structure.
The method for forming the source-drain doped layer comprises the following steps: source and drain openings (not shown) are formed in the fin portions 201 at two sides of the dummy gate structure; and forming a source-drain doping layer in the source-drain opening by adopting an epitaxial process.
In this embodiment, the material of the first dielectric structure 210 includes silicon oxide.
Referring to fig. 8 and 9, fig. 8 is a schematic top view of a semiconductor structure according to an embodiment of the invention, and fig. 9 is a schematic cross-sectional view of the isolation region P in the X-X1 direction in fig. 8, wherein 1 gate structure 220 is formed in each gate opening 211 (as shown in fig. 7).
The method of forming the gate structure 220 includes: forming a gate dielectric material film (not shown) on the bottom and sidewall surfaces of each gate opening 211 and the surface of the first dielectric structure 210; forming a gate material film (not shown) on the surface of the gate dielectric material film, wherein the gate material film fills the gate opening 211; the gate dielectric material film and gate material film are planarized until the first dielectric structure 210 surface is exposed, forming 1 gate structure 220 within each gate opening 211.
The gate structure 220 includes: a gate dielectric layer (not shown) located on the top and side wall surfaces of part of fin 201 and a gate layer (not shown) located on the surface of the gate dielectric layer; the gate dielectric layer comprises the following materials: the high-K dielectric material, the material of the gate layer includes: and (3) metal.
The high-K (dielectric constant greater than 3.9) dielectric material comprises: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.
In this embodiment, the material of the gate dielectric layer is hafnium oxide.
The metal comprises: copper, tungsten, aluminum, titanium, nickel, titanium nitride, and tantalum nitride.
In this embodiment, the material of the gate layer is tungsten.
Next, the gate structure 220 on the isolation region P is removed, and a first opening penetrating the gate structure 220 is formed in the first dielectric structure 210 on the isolation region P. The detailed process of removing the gate structure 220 on the isolation region P is shown in fig. 10 to 13.
Referring to fig. 10 on the basis of fig. 9, a first mask structure 230 is formed on the surface of the first dielectric structure 210 and the surface of the gate structure 220, and the first mask structure 230 exposes the top surfaces of the first dielectric structure 210 and the gate structure 220 of the isolation region P.
The method of forming the first mask structure 230 includes: forming a first mask structure material layer (not shown) on the surface of the first dielectric structure 210 and the surface of the gate structure 220; forming a first patterned layer 231 on the surface of the first mask structure material layer, wherein the first patterned layer 231 exposes the surface of the first mask structure material layer on the isolation region P; the first patterned layer 231 is used as a mask to etch the first mask structure material layer until the surface of the first dielectric structure 210 and the surface of the gate structure 220 are exposed.
The material of the first patterned layer 231 is photoresist, and the first patterned layer 231 with a pattern is formed by using a spin-coating process and a photolithography process.
The materials of the first mask structure 230 include: silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide or titanium dioxide.
In this embodiment, after the first mask structure 230 is formed, an ashing process is used to remove the first patterned layer.
Next, the gate structure 220 on the isolation region P is etched using the first mask structure 230 as a mask until the gate structure 220 on the isolation region P is removed.
In this embodiment, the process of etching the gate structure 220 on the isolation region P is a plasma etching process, which includes: several cycles of etching and deposition processes. For a detailed procedure of the etching process and the deposition process, please refer to fig. 11 and 12.
Referring to fig. 11, the etching process is performed, including: and etching the gate structure 220 on the isolation region P by using the first mask structure 230 as a mask.
The technological parameters of the etching treatment comprise: the etching gas comprises BCl 3、Cl2、He、N2 and O 2, the pressure range is 5 millitorr-100 millitorr, the source radio frequency power is 50 watt-500 watt, the bias voltage is 50 volt-500 volt, and the time is 5 seconds-60 seconds.
Referring to fig. 12, the deposition process is performed, including: a material 212 of the first dielectric structure 210 is deposited on top of the first dielectric structure 210 of the isolation region P.
The technological parameters of the deposition treatment comprise: the adopted gas comprises CH 4、CH3F、CH3 and Ar, the pressure range is 10 millitorr-100 millitorr, the source radio frequency power is 50 watts-500 watts, and the time is 2 seconds-60 seconds.
Since the first mask structure 230 is used as a mask, the plasma etching process for etching the gate structure 220 on the isolation region P includes: the etching process and the deposition process are circulated several times, and thus, damage to the surface of the first dielectric structure 210 caused by each etching process can be repaired by the deposition process, and loss of the first dielectric structure 210 is reduced, so that the top surface of the first dielectric structure 210 is planarized after the first opening is formed. Meanwhile, through the deposition process performed in the etching process cycle, during each deposition process, the material 212 of the first dielectric structure 210 with a thinner thickness can be formed on the top surface of the first dielectric structure 210, so that during each deposition process, the material 212 of the first dielectric structure 210 formed on the top surface of the first dielectric structure 210 can be uniformly consumed, and therefore, the top surface of the first dielectric structure 210 after the first opening is formed is more beneficial to be flat, and the shape accuracy of a strain layer formed subsequently can be improved, so that the difficulty in adjusting the stress suffered by the fin 201 can be reduced. Note that, since the effect is generated in the plasma etching process because the etching process and the deposition process are cyclically and alternately performed, the order between the etching process and the deposition process does not affect the effect of the plasma etching process, that is, the etching process is performed first or the deposition process is performed first in the whole plasma etching process without affecting the effect. In this embodiment, the etching process is performed first in the whole plasma etching process. In other embodiments, the deposition process is performed first throughout the plasma etch process.
For ease of understanding, fig. 11 and 12 show the state of the semiconductor structure during the etching process and the deposition process of the gate structure 220 on the isolation region P.
In this embodiment, the etching process and the deposition process are performed on the same machine, so that the plasma etching process can be performed in a vacuum-free environment, thereby reducing the risk of oxidation and contamination of the semiconductor structure material, and reducing the manufacturing time of the semiconductor structure.
Referring to fig. 13, the gate structure 220 on the isolation region P is etched with the first mask structure 230 as a mask until the gate structure 220 on the isolation region P is removed, and a first opening 241 penetrating the gate structure 220 is formed in the first dielectric structure 210 on the isolation region P.
The first openings 241 provide space and support for the subsequent formation of a strained layer.
In this embodiment, by removing the gate structure 220 and simultaneously consuming the exposed first dielectric structure 210 on the isolation region P, the surface of the first dielectric structure 210 on the isolation region P can be lower than the surface of the first dielectric structure 210 outside the isolation region P, so that the strain layer can be formed on the surface of the first dielectric structure 210 later, so as to ensure that the formed strain layer can completely penetrate the gate structure 220 on the isolation region P, and better transfer the stress provided by the strain layer to the fin 201.
In other embodiments, the first dielectric structure surface is flush within the isolation region and outside the isolation region.
Referring to fig. 14, at least a portion of the first dielectric structure 210 between adjacent first openings 241 is removed, and a second opening 242 communicating with the first openings 241 is formed between the adjacent first openings 241, where the first openings 241 and the second openings 242 form a partition opening 240.
Since the first opening 241 penetrating the gate structure 220 is formed in the first dielectric structure 210 on the isolation region P and the second opening 242 communicating with the first opening 241 is formed between the adjacent first openings 241, the first opening 241 and the second opening 242 constitute the isolation opening 240, and the strained layer is subsequently formed at least in the isolation opening 240, the strained layer is connected to the gate structure 220 penetrated by the first opening 241, and thus the fin 201 is subjected to not only the stress provided by the gate structure 220 but also the stress provided by the strained layer. Meanwhile, since at least part of the first dielectric structures 210 between the adjacent first openings 241 is removed to form the second openings 242, and the second openings 242 are communicated with the first openings 241, the shape of the isolation openings 240 can be adjusted by adjusting the heights of the bottom surfaces of the second openings 242 by adjusting the first dielectric structures 210 between the removed first openings 241. Since the strain layer is formed at least in the isolation opening 240 later, the shape of the strain layer can be adjusted by adjusting the shape of the isolation opening 240, so that the stress applied to the fin 201 can be adjusted by adjusting the shape of the strain layer to adjust the electron mobility of the fin 201, adjust the turn-on voltage of the transistor, and improve the performance and reliability of the semiconductor device.
The height of the bottom surface of the second opening 242 is adjusted depending on the amount of stress required by the fin 201, that is, depending on the shape of the strained layer to be formed.
In this embodiment, the bottom surface of the second opening 242 is higher than the bottom surface of the first opening 241 communicating with the second opening 242.
In other embodiments, the second opening bottom surface may also be lower than or flush with the first opening bottom surface in communication with the second opening.
In this embodiment, the method for forming the second opening 242 includes: the first dielectric structure 210 between adjacent first openings 241 on the isolation region P is etched using the first mask structure 230 as a mask.
In this embodiment, the process of etching the first dielectric structure 210 between adjacent first openings 241 on the isolation region P is a plasma etching process.
In this embodiment, the process parameters for etching the first dielectric structure 241 between adjacent first openings 241 on the isolation region P include: the etching gas comprises CF 4、CH3F、N2、O2 and CH 2F2, the pressure range is 5 millitorr-100 millitorr, the source radio frequency power is 50 watts-500 watts, and the bias voltage is 50 volts-500 volts.
Specifically, by adjusting the process parameters of the plasma etching process, when the first mask structure 230 is used as a mask to etch the first dielectric structure 210 on the isolation region P, fewer etching byproducts are formed on the surface of the first dielectric structure 210 between the first openings 241, and more etching byproducts are formed on the surface of the first dielectric structure 210 exposed in addition, so that the purpose of etching the first dielectric structure 210 between adjacent first openings 241 on the isolation region P and adjusting the second openings 242 is achieved.
It should be noted that, due to the loss of the first mask structure 230 caused by the etching process for removing the gate structure 220 of the isolation region P and the etching process for forming the second opening 242, the thickness of the first mask structure 230 in the substrate normal direction is reduced after the formation of the partition opening 240 compared to the first mask structure 230 before the removal of the gate structure 220 of the isolation region P.
Subsequently, after the formation of the partition openings 240, a strained layer is formed at least within the partition openings 240. The process of forming the strained layer is shown in fig. 15 to 16.
Referring to fig. 15, an initial strain layer 250 is formed on the surface of the first dielectric structure 210 and in the partition opening 240; an initial second dielectric structure 260 is formed on the surface of the initial strained layer 250, and the surface of the initial second dielectric structure 260 is higher than the surface of the initial strained layer 250.
Specifically, in this embodiment, the initial strain layer 250 is located on the surface of the first dielectric structure 210 and on the side wall surface and the bottom surface of the partition opening 240.
In other embodiments, the initial strained layer can also fill the partition openings and the initial second dielectric structure is not formed, and correspondingly, the second dielectric structure is not subsequently formed.
In other embodiments, the initially strained layer can also be filled when the second opening floor is lower than the first opening floor in communication with the second opening: the second opening is lower than the opening part of the bottom surface of the first opening communicated with the second opening, and is positioned on the bottom surface and the side wall surface of the first opening.
It should be noted that whether the initial strained layer 250 needs to fill the isolation opening depends on the amount of stress required by the fin 201, i.e., on the shape of the strained layer to be formed, so as to adjust the shape of the strained layer.
Specifically, in this embodiment, the initial second dielectric structure 260 fills the partition openings 240.
In this embodiment, the first mask structure 230 is not removed before the initial strain layer 250 is formed, so that forming the initial strain layer 250 on the surface of the first dielectric structure 210 means forming the initial strain layer 250 on the surface of the first mask structure 230 on the surface of the first dielectric structure 210. Thus, the first mask structure 230 is removed together with the planarization process while the initial second dielectric structure 260 and the initial strained layer 250 are planarized later, which reduces the process steps for manufacturing the semiconductor structure and saves the time for manufacturing the semiconductor structure.
In other embodiments, the first mask structure is removed after the formation of the partition openings and before the formation of the initial strain layer.
The initial strained layer 250 provides material for subsequent formation of the strained layer.
In this embodiment, the material of the initial strained layer 250 comprises silicon nitride. Accordingly, the material of the strained layer comprises silicon nitride.
In the present embodiment, the process of forming the initial strain layer 250 includes a deposition process, for example, a chemical vapor deposition process (CVD), a physical vapor deposition Process (PVD), an atomic layer deposition process (ALD), or the like.
The initial second dielectric structure 260 provides material for subsequent formation of the second dielectric structure.
In this embodiment, the material of the initial second dielectric structure 260 includes silicon oxide. Correspondingly, the material of the second dielectric structure comprises silicon oxide.
Referring to fig. 16, the initial second dielectric structure 260 and the initial strained layer 250 are planarized until the surface of the first dielectric structure 210 outside the isolation region P is exposed, forming a strained layer 251, and forming a second dielectric structure 261 on the surface of the strained layer 251 in the isolation region P.
In this embodiment, since the top surface of the first dielectric structure 210 on the isolation region P is lower than the surface of the first dielectric structure 210 outside the isolation region P, the strained layer 251 is not only located in the isolation opening 240, but also located on the surface of the first dielectric structure 210 on the isolation region P.
In other embodiments, the strained layer is located within the isolation opening because the first dielectric structure surface is flush within the isolation region and outside the isolation region.
In other embodiments, the second dielectric structure is not formed when the strained layer fills the partition opening.
Specifically, in this embodiment, the surface of the second dielectric structure 261 is flush with the surface of the first dielectric structure 210 outside the isolation region P.
Referring to fig. 17, a third opening (not shown) is formed in the first dielectric structure 210 and the second dielectric structure 261, the third opening spans the isolation region P and the fin 201, and the third opening exposes the top surface of the fin 201; a first interconnect structure 270 is formed within the third opening, the first interconnect structure 270 being electrically interconnected with the fin 201.
In this embodiment, the method for forming the third opening includes: forming a protective layer 280 on the surface of the first dielectric structure 210, the surface of the second dielectric structure 261 and the surface of the strained layer 251; forming a third dielectric structure 290 on the surface of the protective layer 280; forming a second mask structure on the surface of the third dielectric structure 290, wherein the second mask structure exposes a part of the third structure 290; and etching the third dielectric structure 290, the protection layer 280, the first dielectric structure 210 and the second dielectric structure 261 with the second mask structure as a mask until the top surface of the fin 201 is exposed.
Since the strained layer 251 is made of a different material from the first dielectric structure 210 and the second dielectric structure 261, the first dielectric structure 210 and the second dielectric structure 261 can be selectively etched during the etching process of the first dielectric structure 210 and the second dielectric structure 261.
In this embodiment, the method of forming the first interconnect structure 270 in the third opening includes: forming a first interconnect structure material layer (not shown) within the third opening and on the surface of the third dielectric structure 290; the first interconnect structure material layer is planarized until the third dielectric structure 290 surface is exposed, forming the first interconnect structure 270.
In this embodiment, the material of the first interconnect structure 270 includes a metal, for example, copper, tungsten, or aluminum.
In this embodiment, the process of forming the first interconnect structure material layer includes a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, or a metal plating process.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, please continue to refer to fig. 17, which includes: a substrate 200, wherein the substrate 200 includes an isolation region P, and the substrate 200 has a plurality of fins 201 (as shown in fig. 4) that are separated from each other; a plurality of gate structures 220 (shown in fig. 8) that span across the fin 201; the first dielectric structure 210 is located on the substrate, and the first dielectric structure 210 is also located on the surfaces of the fin 201 and the gate structure 220; a partition opening 240 (shown in fig. 14) located in the first dielectric structure 210 on the isolation region P, where the partition opening 240 penetrates through the plurality of gate structures 220 along the extending direction of the fin 201, and the partition opening 240 includes a first opening 241 (shown in fig. 14) exposing a sidewall of the gate structure 220 and a second opening 242 (shown in fig. 14) located between adjacent first openings 241 and communicating with the first openings 241; at least the strained layer 251 within the partition opening 240.
Since the strained layer 251 is located within the isolation opening 240 and each first opening 241 penetrates 1 gate structure 220, the strained layer 251 is connected to the gate structure 220 penetrated by the first openings 241, and thus the fin 201 is not only stressed by the gate structure 220 but also by the strained layer 251, and at the same time, since the semiconductor structure includes the strained layer 251 located at least within the isolation opening 240, the shape of the strained layer 251 can be adjusted by adjusting the position of the bottom surface of the second opening 242, and thus the stress to which the fin 201 is subjected by adjusting the shape of the strained layer 251 to adjust the electron mobility within the fin 201, and the turn-on voltage of the transistor can be adjusted, so that the performance and reliability of the semiconductor device can be improved.
Specifically, the material of the substrate 200 is a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
Specifically, in this embodiment, the number of gate structures 220 crossing over the fin 201 is 2.
In other embodiments, the number of gate structures across the fin may also be 3 or more than 3.
In this embodiment, the gate structure 220 includes: a gate dielectric layer (not shown) located on the top and side wall surfaces of part of fin 201 and a gate layer (not shown) located on the surface of the gate dielectric layer; the gate dielectric layer comprises the following materials: the high-K dielectric material, the material of the gate layer includes: and (3) metal.
The high-K (dielectric constant greater than 3.9) dielectric material comprises: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.
In this embodiment, the material of the gate dielectric layer is hafnium oxide.
The metal comprises: copper, tungsten, aluminum, titanium, nickel, titanium nitride, and tantalum nitride.
In this embodiment, the material of the gate layer is tungsten.
In this embodiment, the first dielectric structure 210 includes: a lower first dielectric structure (not shown) located on the surface of the substrate 200 and a portion of the sidewall surface of the fin 201, where the gate structure 220 is further located on the surface of the lower first dielectric structure; and an upper layer first dielectric structure (not shown) located on the surface of the lower layer first dielectric structure and covering the surface of the fin 201 and the sidewall surface of the gate structure 220.
In this embodiment, the material of the first dielectric structure 210 includes silicon oxide.
The height of the bottom surface of the second opening 242 is adjusted according to the amount of stress required by the fin 201, that is, according to the shape required by the strained layer 251, so as to adjust the shape of the strained layer 251.
In this embodiment, the bottom surface of the second opening 242 is higher than the bottom surface of the first opening 241 communicating with the second opening 242.
In other embodiments, the second opening bottom surface may also be lower than or flush with the first opening bottom surface in communication with the second opening.
In this embodiment, the surface of the first dielectric structure 210 on the isolation region P is lower than the surface of the first dielectric structure 210 outside the isolation region P.
In other embodiments, the first dielectric structure surface is flush within the isolation region and outside the isolation region.
In this embodiment, since the top surface of the first dielectric structure 210 on the isolation region P is lower than the surface of the first dielectric structure 210 outside the isolation region P, the strained layer 251 is not only located in the isolation opening 240, but also located on the surface of the first dielectric structure 210 on the isolation region P. Thus, it can be ensured that the strained layer 251 completely penetrates the gate structure 220 on the isolation region P to better transfer the stress provided by the strained layer 251 to the fin 201.
In other embodiments, the strained layer is located within the isolation opening because the first dielectric structure surface is flush within the isolation region and outside the isolation region.
Specifically, in this embodiment, the strained layer 251 is located on the surface of the first dielectric structure 210 and on the side wall surface and the bottom surface of the partition opening 240.
In other embodiments, the strained layer also fills the partition openings.
In other embodiments, the strained layer is located on the sidewall and bottom surfaces of the partition opening when the second opening bottom surface is lower than the first opening bottom surface in communication with the second opening.
In other embodiments, the strained layer can also be filled when the second opening floor is lower than the first opening floor in communication with the second opening: the second opening is lower than the opening part of the bottom surface of the first opening communicated with the second opening, and is positioned on the bottom surface and the side wall surface of the first opening.
It should be noted that whether the strained layer needs to fill the isolation opening depends on the amount of stress required by the fin 201, i.e., the shape required by the strained layer 251, so as to adjust the shape of the strained layer 251.
In this embodiment, the material of the strained layer 251 includes silicon nitride.
In this embodiment, the semiconductor structure further includes: a second dielectric structure 261 is located on the surface of strained layer 251.
In this embodiment, the surface of the second dielectric structure 261 is flush with the surface of the first dielectric structure 210 outside the isolation region P.
In other embodiments, the semiconductor structure does not include the second dielectric structure when the strained layer fills the partition opening.
In this embodiment, the material of the second dielectric structure 261 includes silicon oxide.
In this embodiment, the semiconductor structure further includes: a first interconnect structure 270 located within the first dielectric structure 210 and the second dielectric structure 261, the first interconnect structure 270 crossing the isolation region P and the fin 201.
Specifically, in this embodiment, the semiconductor structure further includes: a protective layer 280 located on the surface of the first dielectric structure 210, the surface of the second dielectric structure 261, and the surface of the strained layer 251; and a third dielectric structure 290 positioned on the surface of the protective layer 280.
The first interconnect structure 270 penetrates the third dielectric structure 290 and the protection layer 280 and is located in the first dielectric structure 210 and the second dielectric structure 261, and the first interconnect structure 270 is electrically interconnected with the fin 201.
In this embodiment, the material of the first interconnect structure 270 includes a metal, for example, copper, tungsten, or aluminum.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein the substrate comprises an isolation region, and a plurality of mutually separated fin parts are arranged on the substrate; forming a first dielectric structure on the substrate and on the surface of the fin part, wherein a plurality of grid openings crossing the fin part are formed in the first dielectric structure, and the grid openings cross the isolation region;
Forming 1 gate structure within each gate opening;
removing the gate structure on the isolation region, and forming a first opening penetrating through the gate structure in the first dielectric structure on the isolation region;
removing at least part of the first medium structure between the adjacent first openings, forming a second opening communicated with the first opening between the adjacent first openings, wherein the first opening and the second opening form a partition opening;
Forming a strain layer at least within the partition opening;
The method for removing the gate structure on the isolation region comprises the following steps: forming a first mask structure on the surface of the first dielectric structure and the surface of the gate structure, wherein the first mask structure exposes the first dielectric structure and the top surface of the gate structure of the isolation region; etching the gate structure on the isolation region by taking the first mask structure as a mask until the gate structure on the isolation region is removed;
The plasma etching process for etching the gate structure on the isolation region by taking the first mask structure as a mask comprises the following steps: and the etching treatment comprises etching the gate structure on the isolation region by taking the first mask structure as a mask, and the deposition treatment comprises depositing the material of the first dielectric structure on the top surface of the first dielectric structure of the isolation region.
2. The method of forming a semiconductor structure of claim 1, wherein the process parameters of the etching process comprise: the etching gas comprises BCl 3、Cl2、He、N2 and O 2, the pressure range is 5 millitorr-100 millitorr, the source radio frequency power is 50 watt-500 watt, the bias voltage is 50 volt-500 volt, and the time is 5 seconds-60 seconds.
3. The method of forming a semiconductor structure of claim 1, wherein the process parameters of the deposition process comprise: the adopted gas comprises CH 4、CH3F、CH3 and Ar, the pressure range is 10 millitorr-100 millitorr, the source radio frequency power is 50 watts-500 watts, and the time is 2 seconds-60 seconds.
4. The method of forming a semiconductor structure of claim 1, wherein the method of forming the second opening comprises: and etching the first medium structure between the adjacent first openings on the isolation region by taking the first mask structure as a mask.
5. The method of claim 4, wherein the process of etching the first dielectric structure between adjacent first openings on the isolation region is a plasma etching process.
6. The method of forming a semiconductor structure of claim 5, wherein etching the first dielectric structure between adjacent first openings over the isolation region comprises: the etching gas comprises CF 4、CH3F、N2、O2 and CH 2F2, the pressure range is 5 millitorr-100 millitorr, the source radio frequency power is 50 watts-500 watts, and the bias voltage is 50 volts-500 volts.
7. The method of forming a semiconductor structure of claim 1, wherein the method of forming the strained layer comprises: forming an initial strain layer on the surface of the first medium structure and in the partition opening; forming an initial second dielectric structure on the surface of the initial strain layer, wherein the surface of the initial second dielectric structure is higher than the surface of the initial strain layer; and flattening the initial second dielectric structure and the initial strain layer until the surface of the first dielectric structure outside the isolation region is exposed, forming the strain layer, and forming a second dielectric structure on the surface of the strain layer of the isolation region.
8. The method of claim 7, wherein said strained layers within said isolation openings are all located on a surface of said first dielectric structure.
9. The method of forming a semiconductor structure of claim 7, further comprising: forming a third opening in the first dielectric structure and the second dielectric structure, wherein the third opening spans the isolation region and the fin part, and the third opening exposes the top surface of the fin part; a first interconnect structure is formed within the third opening.
10. A semiconductor structure formed by the method of forming a semiconductor structure according to any one of claims 1 to 9.
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| DE102018124814A1 (en) * | 2017-11-15 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate structure and process for its preparation |
| KR102636464B1 (en) * | 2018-06-12 | 2024-02-14 | 삼성전자주식회사 | Semiconductor device having gate isolation layer and method of manufacturing the same |
| US11211293B2 (en) * | 2018-07-31 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and methods of forming the same |
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| CN109216354A (en) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Metal gate structure cutting technique |
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